Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24068

1

T1

20

T3

16

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3441

1

T2

1

T4

9

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21178

1

T1

20

T2

1

T3

16

auto[1]

6331

1

T5

1

T6

1

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	332	1			T15	1		T138	8		T54	7
values[0]	48	1			T201	11		T155	20		T292	17
values[1]	950	1			T15	7		T127	15		T128	27
values[2]	670	1			T2	1		T11	1		T24	15
values[3]	575	1			T6	1		T7	21		T9	2
values[4]	640	1			T7	8		T127	15		T37	4
values[5]	645	1			T12	14		T54	16		T128	2
values[6]	549	1			T6	1		T14	7		T24	19
values[7]	704	1			T4	9		T10	7		T24	7
values[8]	3027	1			T5	1		T6	1		T8	25
values[9]	1046	1			T127	1		T128	17		T131	1
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	653	1			T15	7		T127	15		T128	27
values[1]	723	1			T2	1		T6	1		T11	1
values[2]	596	1			T7	21		T9	2		T16	6
values[3]	727	1			T7	8		T12	14		T127	15
values[4]	541	1			T54	16		T128	2		T151	11
values[5]	661	1			T6	1		T10	7		T14	7
values[6]	2918	1			T4	9		T5	1		T6	1
values[7]	691	1			T9	1		T12	1		T128	17
values[8]	1078	1			T127	1		T138	8		T54	7
values[9]	156	1			T15	1		T133	19		T135	26
minimum	18765	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T201	12		T153	4		T83	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	6		T127	1		T128	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	1		T219	10		T140	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T6	1		T24	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	11		T9	2		T54	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	3		T37	1		T136	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T127	1		T258	11		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	3		T12	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T54	11		T151	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T128	1		T130	8		T257	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T24	2		T28	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	5		T14	5		T24	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T5	1		T6	1		T8	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	1		T129	1		T19	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T78	1		T268	5		T22	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	1		T12	1		T128	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T138	8		T54	3		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T127	1		T132	23		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T133	10		T135	13		T43	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T15	1		T250	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18327	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T151	1		T219	13		T141	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T201	9		T153	7		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	1		T127	14		T128	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T219	10		T165	9		T33	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T24	3		T43	1		T153	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	10		T54	13		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T16	3		T37	3		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T127	14		T136	9		T238	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	5		T12	13		T38	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T54	5		T151	10		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T128	1		T223	1		T78	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T24	5		T28	4		T151	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	2		T14	2		T24	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T26	22		T149	14		T159	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	8		T129	12		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T78	13		T268	10		T22	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T128	8		T218	7		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T54	4		T44	1		T155	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T201	12		T245	3		T234	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T133	9		T135	13		T43	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T219	10		T155	9		T329	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	8		T54	3		T40	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T15	1		T227	1		T34	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T201	1		T292	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T155	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T48	18		T152	17		T153	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T15	6		T127	1		T128	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	1		T201	12		T140	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T24	12		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	11		T9	2		T54	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T6	1		T16	3		T136	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T127	1		T151	1		T258	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	3		T37	1		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T54	11		T194	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	1		T128	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	1		T28	11		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	5		T24	9		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	2		T132	10		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	1		T10	5		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T5	1		T6	1		T8	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	1		T12	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T131	1		T133	10		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T127	1		T128	9		T132	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T54	4		T155	3		T220	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T227	4		T34	8		T198	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T201	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T155	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T48	2		T152	16		T153	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	1		T127	14		T128	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T201	9		T165	9		T190	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	3		T165	11		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	10		T54	13		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T16	3		T136	9		T153	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T127	14		T151	10		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	5		T37	3		T38	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T54	5		T135	13		T147	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	13		T128	1		T235	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T28	4		T151	10		T152	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	2		T24	10		T40	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	5		T178	1		T218	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	8		T10	2		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T26	22		T149	14		T159	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T218	7		T136	13		T82	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T133	9		T135	13		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T128	8		T201	12		T245	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T201	10		T153	8		T83	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	6		T127	15		T128	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	1		T219	11		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T6	1		T24	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	11		T9	2		T54	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	6		T37	4		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T127	15		T258	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	6		T12	14		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T54	6		T151	11		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T128	2		T130	1		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	1		T24	6		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	7		T14	7		T24	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T5	1		T6	1		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	9		T129	13		T19	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T78	14		T268	13		T22	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	1		T12	1		T128	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T138	1		T54	5		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T127	1		T132	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T133	10		T135	14		T43	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T15	1		T250	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18450	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T151	1		T219	11		T141	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T201	11		T153	3		T247	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	1		T128	11		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T219	9		T140	14		T216	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T24	11		T215	13		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	10		T54	14		T132	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T136	2		T20	1		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T258	10		T136	10		T238	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	2		T38	1		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T54	10		T135	12		T147	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	7		T257	2		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T24	1		T28	10		T130	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T24	8		T141	10		T40	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T8	23		T29	24		T45	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T19	1		T156	15		T287	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T268	2		T22	1		T302	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T128	8		T218	7		T136	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T138	7		T54	2		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T132	22		T201	10		T217	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T133	9		T135	12		T43	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	17		T152	16		T20	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T219	12		T141	9		T155	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T138	1		T54	5		T40	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T15	1		T227	5		T34	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T201	11		T292	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T155	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T48	3		T152	17		T153	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T15	6		T127	15		T128	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T201	10		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T24	4		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	11		T9	2		T54	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	1		T16	6		T136	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T127	15		T151	11		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	6		T37	4		T38	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T54	6		T194	1		T135	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	14		T128	2		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T28	5		T151	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	7		T24	11		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T24	6		T132	1		T178	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	9		T10	7		T129	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T5	1		T6	1		T8	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	1		T12	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T131	1		T133	10		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T127	1		T128	9		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	7		T54	2		T252	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T34	4		T272	4		T330	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T292	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T155	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T48	17		T152	16		T153	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T15	1		T128	11		T219	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T201	11		T140	14		T216	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T24	11		T215	13		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	10		T54	14		T219	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T136	2		T153	14		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T258	10		T166	13		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	2		T38	1		T17	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T54	10		T135	12		T147	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T130	7		T172	8		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T28	10		T130	3		T215	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T24	8		T257	2		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T24	1		T132	9		T218	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T254	10		T252	9		T19	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T8	23		T29	24		T45	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T218	7		T136	12		T217	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T133	9		T135	12		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T128	8		T132	22		T201	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20