Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23972

1

T1

20

T3

16

T4

9

auto[ADC_CTRL_FILTER_COND_OUT]

3537

1

T2

1

T6

2

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

20

T2

1

T3

16

auto[1]

5910

1

T5

1

T7

29

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	225	1			T4	9		T54	28		T186	1
values[0]	19	1			T14	7		T151	11		T145	1
values[1]	795	1			T37	4		T128	27		T129	13
values[2]	678	1			T2	1		T6	1		T28	15
values[3]	700	1			T7	21		T127	15		T16	1
values[4]	2867	1			T5	1		T8	25		T35	1
values[5]	594	1			T9	1		T130	4		T165	10
values[6]	685	1			T9	1		T15	1		T219	23
values[7]	996	1			T6	1		T12	1		T24	7
values[8]	680	1			T15	1		T128	17		T151	1
values[9]	947	1			T6	1		T7	8		T9	1
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	768	1			T37	4		T128	27		T129	13
values[1]	615	1			T2	1		T6	1		T7	21
values[2]	656	1			T127	30		T16	1		T54	23
values[3]	2805	1			T5	1		T8	25		T35	1
values[4]	768	1			T9	2		T130	4		T216	7
values[5]	584	1			T6	1		T15	1		T16	2
values[6]	1065	1			T12	1		T24	7		T15	7
values[7]	654	1			T12	14		T15	1		T128	17
values[8]	888	1			T6	1		T7	8		T10	7
values[9]	102	1			T4	9		T9	1		T141	13
minimum	18604	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T129	1		T38	5		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	1		T128	12		T252	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	1		T7	11		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T28	11		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T127	1		T139	1		T166	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T127	1		T16	1		T54	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T5	1		T8	25		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	9		T131	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	2		T130	4		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T216	7		T143	1		T245	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	1		T194	1		T140	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T16	1		T219	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T24	2		T15	6		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	1		T172	9		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	1		T128	9		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	1		T219	10		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	3		T10	5		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	1		T11	1		T138	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T4	1		T141	13		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T9	1		T276	13		T248	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18229	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T14	5		T135	13		T156	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T129	12		T38	14		T261	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T37	3		T128	15		T251	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	10		T151	10		T218	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T28	4		T37	2		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	14		T220	5		T230	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	14		T54	9		T17	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T24	3		T26	22		T149	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T24	10		T238	12		T165	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T147	4		T84	7		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T245	3		T78	14		T82	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T226	10		T22	3		T98	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	1		T219	10		T126	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T24	5		T15	1		T129	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T135	13		T136	13		T165	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T128	8		T136	9		T80	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	13		T219	10		T201	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	5		T10	2		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T218	7		T40	3		T155	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T4	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T276	8		T248	10		T249	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T14	2		T135	13		T246	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T4	1		T54	15		T152	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T186	1		T40	6		T286	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T151	1		T145	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T14	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T129	1		T215	5		T216	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T37	1		T128	12		T135	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T151	1		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T28	11		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	11		T130	8		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T127	1		T16	1		T54	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T5	1		T8	25		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T24	9		T131	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T130	4		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	1		T143	1		T245	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	1		T15	1		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T219	13		T126	10		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T24	2		T15	6		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	1		T12	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	1		T128	9		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T219	10		T172	9		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	3		T10	5		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T6	1		T9	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T4	8		T54	13		T152	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T40	3		T233	8		T276	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T151	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T14	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T129	12		T153	14		T261	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	3		T128	15		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T151	10		T38	14		T218	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	4		T48	2		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	10		T220	5		T230	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T127	14		T54	9		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T24	3		T26	22		T127	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T24	10		T238	12		T17	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T147	4		T236	2		T224	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T165	9		T245	3		T82	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T84	7		T226	10		T306	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T219	10		T126	9		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T24	5		T15	1		T129	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T16	1		T135	13		T136	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T128	8		T136	9		T80	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T219	10		T136	13		T201	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	5		T10	2		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	13		T218	7		T155	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T129	13		T38	18		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	4		T128	16		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	1		T7	11		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	1		T28	5		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T127	15		T139	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T127	15		T16	1		T54	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T5	1		T8	2		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	11		T131	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	2		T130	1		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T216	1		T143	1		T245	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	1		T194	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T16	2		T219	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T24	6		T15	6		T129	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T12	1		T172	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	1		T128	9		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	14		T219	11		T201	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T7	6		T10	7		T16	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T11	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T4	9		T141	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T9	1		T276	9		T248	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18374	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	7		T135	14		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T38	1		T217	16		T196	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T128	11		T252	9		T251	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	10		T130	7		T218	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	10		T48	17		T152	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T166	13		T233	7		T213	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T54	12		T253	10		T140	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T8	23		T24	11		T29	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T24	8		T238	13		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T130	3		T147	9		T254	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T216	6		T245	6		T82	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T140	14		T22	2		T271	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T219	12		T126	9		T133	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T24	1		T15	1		T132	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T172	8		T135	12		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T128	8		T257	2		T136	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T219	9		T44	2		T223	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	2		T54	14		T258	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T138	7		T218	7		T40	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T141	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T276	12		T249	13		T331	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T215	4		T216	17		T287	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T135	12		T156	15		T246	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T4	9		T54	14		T152	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T186	1		T40	5		T286	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T151	11		T145	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T14	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T129	13		T215	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T37	4		T128	16		T135	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	1		T151	11		T38	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T28	5		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	11		T130	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T127	15		T16	1		T54	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T5	1		T8	2		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T24	11		T131	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T130	1		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T165	10		T143	1		T245	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	1		T15	1		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T219	11		T126	10		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T24	6		T15	6		T129	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T6	1		T12	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T15	1		T128	9		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T219	11		T172	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T7	6		T10	7		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	1		T9	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T54	14		T152	16		T141	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T40	4		T233	7		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T215	4		T216	17		T153	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T128	11		T135	12		T156	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	1		T218	2		T201	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T28	10		T48	17		T152	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	10		T130	7		T233	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T54	12		T253	10		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T8	23		T24	11		T29	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T24	8		T238	13		T140	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T130	3		T147	9		T254	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T245	6		T82	11		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T140	14		T84	8		T306	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T219	12		T126	9		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T24	1		T15	1		T132	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T135	12		T136	10		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T128	8		T136	2		T252	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T219	9		T172	8		T136	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	2		T258	10		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T138	7		T218	7		T252	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20