Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24106

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3403

1

T6

2

T9

2

T10

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21422

1

T1

20

T2

1

T3

16

auto[1]

6087

1

T4

9

T5

1

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	791	1			T6	1		T7	2		T10	2
values[0]	33	1			T7	21		T244	1		T214	1
values[1]	663	1			T6	1		T24	15		T151	1
values[2]	3128	1			T5	1		T8	25		T9	2
values[3]	695	1			T4	9		T7	8		T11	1
values[4]	736	1			T12	14		T37	3		T128	17
values[5]	648	1			T28	15		T127	15		T215	5
values[6]	568	1			T2	1		T54	16		T151	11
values[7]	639	1			T6	1		T9	1		T10	7
values[8]	623	1			T14	7		T37	4		T126	19
values[9]	1127	1			T24	7		T16	4		T138	8
minimum	17858	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	600	1			T6	1		T24	15		T151	12
values[1]	3082	1			T5	1		T8	25		T9	2
values[2]	843	1			T4	9		T7	8		T11	1
values[3]	626	1			T28	15		T37	3		T129	7
values[4]	672	1			T127	15		T139	1		T186	1
values[5]	544	1			T2	1		T24	19		T54	16
values[6]	697	1			T6	1		T9	1		T10	7
values[7]	536	1			T14	7		T37	4		T126	19
values[8]	1150	1			T24	7		T15	9		T127	15
values[9]	181	1			T6	1		T135	26		T201	11
minimum	18578	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T24	12		T151	2		T130	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	1		T129	1		T218	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T5	1		T8	25		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	1		T12	1		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	1		T7	3		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	1		T128	10		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T28	11		T37	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T129	1		T215	5		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T127	1		T139	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T186	1		T166	1		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T24	9		T54	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	1		T130	4		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	1		T128	12		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	1		T10	5		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	5		T37	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T126	10		T165	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T15	1		T16	2		T138	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T24	2		T15	7		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T82	12		T227	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T6	1		T135	13		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18245	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T254	11		T196	4		T244	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	3		T151	10		T43	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T129	12		T218	7		T84	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T26	22		T149	14		T54	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T16	1		T222	11		T232	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	8		T7	5		T12	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T128	9		T261	10		T82	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T28	4		T37	2		T136	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	6		T155	12		T226	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	14		T153	7		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	9		T147	4		T233	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T24	10		T54	5		T201	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T151	10		T152	16		T190	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T128	15		T133	9		T178	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	2		T135	13		T235	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	2		T37	3		T218	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T126	9		T165	11		T222	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T16	2		T38	14		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T24	5		T15	1		T127	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T82	10		T227	4		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T135	13		T201	10		T226	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	10		T14	3		T15	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T196	3		T23	4		T277	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	551	1			T7	2		T10	2		T36	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T6	1		T15	7		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T7	11		T228	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T244	1		T214	1		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	12		T151	1		T130	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T129	1		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1696	1			T5	1		T8	25		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	1		T12	1		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	1		T7	3		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	1		T128	1		T215	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T37	1		T219	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T128	9		T129	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	11		T127	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T215	5		T132	10		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	1		T54	11		T132	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T151	1		T130	4		T152	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	1		T24	9		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	1		T10	5		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	5		T37	1		T218	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T126	10		T194	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T16	2		T138	8		T48	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T24	2		T54	15		T219	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17716	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T38	14		T238	12		T80	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	1		T127	14		T201	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T7	10		T228	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T23	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	3		T17	22		T40	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T129	12		T84	7		T196	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T26	22		T149	14		T54	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	1		T218	7		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	8		T7	5		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T128	1		T261	10		T82	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	13		T37	2		T219	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T128	8		T129	6		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T28	4		T127	14		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T136	9		T233	8		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T54	5		T201	12		T44	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T151	10		T152	16		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T24	10		T128	15		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T10	2		T135	13		T78	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	2		T37	3		T218	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T126	9		T235	11		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T16	2		T48	2		T245	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T24	5		T54	13		T219	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T24	4		T151	12		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	1		T129	13		T218	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T5	1		T8	2		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	1		T12	1		T16	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	9		T7	6		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	1		T128	11		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T28	5		T37	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T129	7		T215	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T127	15		T139	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T186	1		T166	1		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T24	11		T54	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T151	11		T130	1		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T128	16		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	1		T10	7		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	7		T37	4		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T126	10		T165	12		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T15	1		T16	4		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T24	6		T15	7		T127	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T82	11		T227	5		T198	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T6	1		T135	14		T201	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18415	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T254	1		T196	4		T244	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T24	11		T130	7		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T218	7		T216	6		T217	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T8	23		T29	24		T45	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T258	10		T141	12		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	2		T219	9		T223	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T128	8		T215	13		T82	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T28	10		T136	12		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T215	4		T132	9		T155	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T166	13		T153	3		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T136	10		T217	16		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T24	8		T54	10		T132	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T130	3		T152	16		T216	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T128	11		T133	9		T201	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	12		T140	14		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T218	2		T140	12		T19	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T126	9		T222	11		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T138	7		T38	1		T48	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T24	1		T15	1		T54	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T82	11		T239	10		T290	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T135	12		T240	15		T176	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T7	10		T17	9		T40	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T254	10		T196	3		T23	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	562	1			T7	2		T10	2		T36	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	1		T15	7		T127	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T7	11		T228	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T244	1		T214	1		T23	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T24	4		T151	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	1		T129	13		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T5	1		T8	2		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	1		T12	1		T16	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	9		T7	6		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T128	2		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	14		T37	3		T219	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T128	9		T129	7		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T28	5		T127	15		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T215	1		T132	1		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	1		T54	6		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T151	11		T130	1		T152	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T24	11		T128	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	1		T10	7		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	7		T37	4		T218	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T126	10		T194	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T16	4		T138	1		T48	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T24	6		T54	14		T219	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17858	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T38	1		T238	13		T80	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T15	1		T172	8		T235	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T7	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T23	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T24	11		T130	7		T17	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T217	9		T254	10		T84	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T8	23		T29	24		T45	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T258	10		T218	7		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	2		T43	1		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T215	13		T82	16		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T219	9		T136	12		T223	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T128	8		T155	13		T332	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T28	10		T153	3		T268	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T215	4		T132	9		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T54	10		T132	22		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T130	3		T152	16		T216	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T24	8		T128	11		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T135	12		T140	14		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T218	2		T136	2		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T126	9		T235	16		T252	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T138	7		T48	17		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T24	1		T54	14		T219	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20