Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T151	11		T129	13		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T14	7		T37	4		T128	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T7	11		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	1		T28	5		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T127	15		T132	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T127	15		T16	1		T54	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T5	1		T8	2		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	11		T131	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	2		T130	1		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T216	1		T143	1		T245	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T194	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	1		T16	2		T219	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T24	6		T15	1		T129	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T12	1		T172	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	6		T128	9		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	14		T219	11		T201	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T4	9		T7	6		T16	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T11	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T10	7		T141	1		T220	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T9	1		T142	1		T82	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18324	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T246	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T38	1		T215	4		T216	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T128	11		T135	12		T252	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	10		T130	7		T218	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T28	10		T48	17		T152	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T132	16		T166	13		T233	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	12		T253	10		T140	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T8	23		T24	11		T29	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T24	8		T238	13		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T130	3		T147	9		T254	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T216	6		T245	6		T82	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T140	14		T255	9		T256	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T219	12		T126	9		T133	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T24	1		T132	22		T136	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T172	8		T135	12		T136	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T15	1		T128	8		T257	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T219	9		T44	2		T223	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	2		T54	14		T258	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T138	7		T218	7		T40	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T141	12		T220	9		T247	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T82	16		T249	13		T259	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T246	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T244	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T145	1		T250	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T14	7		T135	14		T246	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T151	11		T129	13		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	4		T128	16		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	1		T151	11		T38	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	1		T28	5		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	11		T130	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T127	15		T16	1		T54	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T5	1		T8	2		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	11		T131	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	1		T24	4		T128	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T165	10		T143	1		T245	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	1		T15	1		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T219	11		T126	10		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T24	6		T15	6		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T6	1		T16	2		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	6		T15	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T172	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T4	9		T10	7		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T6	1		T9	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T135	12		T246	6		T231	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T215	4		T216	17		T153	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T128	11		T156	15		T251	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T38	1		T201	11		T242	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	10		T48	17		T152	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	10		T130	7		T218	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	12		T253	10		T223	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T8	23		T29	24		T45	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T24	8		T238	13		T140	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T24	11		T130	3		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T245	6		T82	11		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	14		T84	8		T222	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T219	12		T126	9		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	1		T15	1		T128	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T135	12		T136	10		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	2		T257	2		T252	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T172	8		T136	12		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T54	14		T258	10		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T138	7		T219	9		T218	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20