Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23778

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3731

1

T4

9

T6

1

T7

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21541

1

T1

20

T3

16

T4

9

auto[1]

5968

1

T2

1

T5

1

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T260	11		-	-		-	-
values[0]	43	1			T2	1		T6	1		T245	10
values[1]	766	1			T7	21		T24	19		T15	1
values[2]	605	1			T14	7		T54	28		T37	3
values[3]	750	1			T7	8		T127	16		T129	13
values[4]	699	1			T4	9		T9	1		T28	15
values[5]	824	1			T9	1		T12	14		T54	7
values[6]	629	1			T6	1		T9	1		T11	1
values[7]	735	1			T6	1		T15	7		T54	16
values[8]	613	1			T12	1		T24	7		T15	1
values[9]	3511	1			T5	1		T8	25		T10	7
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	854	1			T2	1		T6	1		T7	21
values[1]	659	1			T7	8		T14	7		T37	3
values[2]	705	1			T4	9		T127	16		T129	13
values[3]	890	1			T9	2		T28	15		T54	7
values[4]	749	1			T12	14		T37	4		T151	23
values[5]	568	1			T6	2		T9	1		T11	1
values[6]	3132	1			T5	1		T8	25		T12	1
values[7]	584	1			T15	1		T16	3		T138	8
values[8]	792	1			T10	7		T127	15		T128	2
values[9]	214	1			T24	15		T215	5		T134	1
minimum	18362	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	1		T6	1		T24	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	11		T16	2		T130	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	5		T37	1		T172	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	3		T128	9		T201	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T131	1		T136	13		T201	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	1		T127	2		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	2		T219	23		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T28	11		T54	3		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T151	1		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	1		T151	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	1		T9	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T11	1		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1736	1			T5	1		T8	25		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T54	11		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	1		T16	2		T138	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T129	1		T39	2		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	5		T128	1		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T127	1		T145	1		T132	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T215	5		T166	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T24	12		T134	1		T235	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18196	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T24	10		T54	13		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	10		T16	2		T135	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	2		T37	2		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	5		T128	8		T201	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T136	13		T201	9		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	8		T127	14		T129	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T219	20		T136	9		T230	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T28	4		T54	4		T38	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	13		T151	10		T133	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T37	3		T151	10		T223	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T178	1		T78	12		T221	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T128	15		T155	9		T222	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T24	5		T26	22		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T54	5		T261	10		T78	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	1		T152	2		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T129	6		T147	10		T196	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	2		T128	1		T165	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T127	14		T33	4		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T165	11		T262	2		T263	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T24	3		T235	11		T264	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	3		T15	6		T16	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T260	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T2	1		T6	1		T245	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T220	1		T214	1		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	9		T15	1		T130	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	11		T16	2		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	5		T54	15		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T128	9		T201	11		T17	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T136	13		T230	1		T222	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	3		T127	2		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T219	10		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	1		T28	11		T48	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	1		T12	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	3		T151	2		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	1		T9	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T37	1		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	6		T194	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T54	11		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	2		T15	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T129	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T5	1		T8	25		T10	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	458	1			T24	12		T127	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T260	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T245	3		T266	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T220	5		T267	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T24	10		T126	9		T223	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	10		T16	2		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T14	2		T54	13		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T128	8		T201	12		T17	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T136	13		T230	15		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	5		T127	14		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T219	10		T136	9		T201	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	8		T28	4		T48	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	13		T151	10		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T54	4		T151	10		T38	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T178	1		T218	2		T223	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	3		T128	15		T223	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	1		T78	14		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T54	5		T261	10		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T24	5		T16	1		T152	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	6		T147	10		T78	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T10	2		T26	22		T149	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T24	3		T127	14		T33	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	1		T6	1		T24	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	11		T16	4		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	7		T37	3		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	6		T128	9		T201	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	1		T136	14		T201	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	9		T127	16		T129	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	2		T219	22		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T28	5		T54	5		T38	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	14		T151	11		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T37	4		T151	12		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	1		T9	1		T178	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T11	1		T128	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T5	1		T8	2		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T54	6		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	1		T16	3		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T129	7		T39	2		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	7		T128	2		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T127	15		T145	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T215	1		T166	1		T165	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T24	4		T134	1		T235	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18350	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	8		T54	14		T130	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	10		T130	3		T215	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T172	8		T221	2		T268	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	2		T128	8		T201	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	12		T201	11		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T135	12		T136	2		T152	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T219	21		T136	10		T217	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	10		T54	2		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T133	9		T257	2		T223	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T84	8		T243	12		T232	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T140	2		T269	14		T270	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T128	11		T141	10		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T8	23		T24	1		T29	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	10		T141	12		T80	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T138	7		T132	22		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T233	14		T237	9		T22	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	9		T153	3		T34	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T132	16		T140	14		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T215	4		T262	7		T263	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T24	11		T235	10		T271	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T220	9		T266	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T260	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T2	1		T6	1		T245	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T220	6		T214	1		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T24	11		T15	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	11		T16	4		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	7		T54	14		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T128	9		T201	13		T17	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	14		T230	16		T222	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	6		T127	16		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	1		T219	11		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	9		T28	5		T48	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	1		T12	14		T151	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T54	5		T151	12		T38	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T9	1		T178	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T37	4		T128	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	6		T194	1		T78	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	1		T54	6		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T24	6		T15	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T129	7		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T5	1		T8	2		T10	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T24	4		T127	15		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T260	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T245	6		T266	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T267	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T24	8		T130	7		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	10		T130	3		T215	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T54	14		T172	8		T258	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T128	8		T201	10		T17	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T136	12		T222	11		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	2		T135	12		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T219	9		T136	10		T201	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T28	10		T48	17		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T219	12		T133	9		T155	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T54	2		T38	1		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T257	2		T218	2		T140	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T128	11		T243	12		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	1		T19	1		T156	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T54	10		T141	22		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T24	1		T138	7		T132	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T22	1		T105	10		T272	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T8	23		T29	24		T45	30
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T24	11		T132	16		T140	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20