Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23929

1

T1

20

T3

16

T4

9

auto[ADC_CTRL_FILTER_COND_OUT]

3580

1

T2

1

T6

2

T7

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21549

1

T1

20

T2

1

T3

16

auto[1]

5960

1

T5

1

T6

1

T7

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T131	1		T142	1		T271	13
values[0]	9	1			T168	1		T273	5		T274	2
values[1]	687	1			T6	1		T12	1		T24	15
values[2]	633	1			T9	1		T10	7		T15	7
values[3]	756	1			T6	1		T9	1		T54	7
values[4]	699	1			T2	1		T6	1		T7	21
values[5]	2946	1			T5	1		T8	25		T35	1
values[6]	757	1			T24	7		T127	15		T128	2
values[7]	492	1			T127	15		T16	1		T138	8
values[8]	950	1			T4	9		T12	14		T16	4
values[9]	1227	1			T7	8		T9	1		T11	1
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	768	1			T6	1		T24	15		T15	1
values[1]	635	1			T6	1		T9	2		T10	7
values[2]	925	1			T151	11		T129	13		T48	20
values[3]	3030	1			T2	1		T5	1		T6	1
values[4]	625	1			T24	7		T127	16		T151	11
values[5]	626	1			T127	15		T16	1		T172	9
values[6]	558	1			T12	14		T128	2		T219	20
values[7]	892	1			T4	9		T15	1		T16	4
values[8]	806	1			T7	8		T11	1		T24	19
values[9]	302	1			T9	1		T14	7		T16	2
minimum	18342	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	1		T24	12		T38	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	1		T139	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T12	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	1		T9	1		T10	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T151	1		T129	1		T257	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T48	18		T133	10		T40	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T5	1		T8	25		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T6	1		T7	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T127	1		T151	1		T215	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T24	2		T127	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T127	1		T16	1		T172	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T166	1		T140	13		T216	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T128	1		T219	10		T147	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	1		T215	14		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T4	1		T15	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T138	8		T54	15		T130	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	1		T151	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	3		T11	1		T24	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T9	1		T14	5		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T275	1		T243	8		T276	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18182	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T246	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T24	3		T38	14		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T245	3		T155	3		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T54	4		T37	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	2		T129	6		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T151	10		T129	12		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T48	2		T133	9		T40	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T26	22		T149	14		T159	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	10		T128	23		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T151	10		T223	1		T196	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	5		T127	14		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T127	14		T44	1		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T223	3		T224	1		T34	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T128	1		T219	10		T147	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	13		T178	1		T222	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	8		T16	2		T54	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T54	13		T136	9		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	2		T219	10		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	5		T24	10		T28	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T14	2		T16	1		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T243	7		T276	8		T277	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T246	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T131	1		T142	1		T271	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T273	5		T278	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T168	1		T274	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	1		T12	1		T24	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	1		T139	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T15	6		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	5		T129	1		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T54	3		T151	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	1		T9	1		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T139	1		T194	1		T152	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T6	1		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T5	1		T8	25		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T135	13		T201	1		T140	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T128	1		T151	1		T172	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T24	2		T127	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T127	1		T16	1		T219	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T138	8		T215	14		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T4	1		T16	2		T54	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T54	15		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T9	1		T14	5		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	411	1			T7	3		T11	1		T24	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T279	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T274	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	3		T38	14		T237	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T245	3		T233	18		T167	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T37	3		T126	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	2		T129	6		T135	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T54	4		T151	10		T129	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T78	12		T82	14		T196	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T152	2		T165	9		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	10		T128	23		T48	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T26	22		T149	14		T159	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T135	13		T201	10		T153	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T128	1		T151	10		T44	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T24	5		T127	14		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T127	14		T219	10		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T178	1		T223	3		T222	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	8		T16	2		T54	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	13		T54	13		T136	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	2		T16	1		T37	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	5		T24	10		T28	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	1		T24	4		T38	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	1		T139	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	1		T12	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T9	1		T10	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T151	11		T129	13		T257	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T48	3		T133	10		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T5	1		T8	2		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T6	1		T7	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T127	1		T151	11		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	6		T127	15		T135	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T127	15		T16	1		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T166	1		T140	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T128	2		T219	11		T147	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	14		T215	1		T178	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T4	9		T15	1		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T138	1		T54	14		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	3		T151	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	6		T11	1		T24	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T9	1		T14	7		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T275	1		T243	8		T276	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18324	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T246	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	11		T38	1		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T245	6		T155	3		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T54	2		T218	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T135	12		T252	6		T156	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T257	2		T136	2		T201	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	17		T133	9		T40	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T8	23		T29	24		T45	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	10		T128	19		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T215	4		T140	14		T196	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	1		T135	12		T140	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T172	8		T132	16		T44	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T140	12		T216	17		T223	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T219	9		T147	9		T80	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T215	13		T252	13		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T54	10		T132	9		T152	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T138	7		T54	14		T130	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T219	12		T84	8		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	2		T24	8		T28	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T280	10		T174	9		T281	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T243	7		T276	12		T282	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T246	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T131	1		T142	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T273	1		T278	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T168	1		T274	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	1		T12	1		T24	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	1		T139	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	1		T15	6		T37	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	7		T129	7		T135	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T54	5		T151	11		T129	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T9	1		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T139	1		T194	1		T152	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	1		T6	1		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T5	1		T8	2		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T135	14		T201	11		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T128	2		T151	11		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	6		T127	15		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T127	15		T16	1		T219	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	1		T215	1		T178	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T4	9		T16	4		T54	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	14		T54	14		T136	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T9	1		T14	7		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T7	6		T11	1		T24	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T271	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T273	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	11		T38	1		T132	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T245	6		T233	23		T167	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	1		T126	9		T218	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T135	12		T252	6		T155	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T54	2		T257	2		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T216	6		T217	9		T82	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T152	4		T254	10		T235	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	10		T128	19		T48	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T8	23		T29	24		T45	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T135	12		T140	2		T213	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T172	8		T132	16		T140	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	1		T140	12		T153	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T219	9		T147	9		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T138	7		T215	13		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T54	10		T132	9		T152	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T54	14		T136	10		T252	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T219	12		T217	16		T84	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T7	2		T24	8		T28	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20