Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21560

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

5949

1

T4

9

T5

1

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21548

1

T1

20

T2

1

T3

16

auto[1]

5961

1

T4

9

T5

1

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	354	1			T37	3		T151	11		T219	23
values[0]	11	1			T283	1		T180	1		T284	9
values[1]	748	1			T10	7		T14	7		T129	7
values[2]	677	1			T6	1		T54	16		T151	11
values[3]	758	1			T12	14		T24	15		T28	15
values[4]	640	1			T6	1		T9	2		T15	1
values[5]	760	1			T6	1		T11	1		T127	15
values[6]	613	1			T2	1		T4	9		T7	8
values[7]	791	1			T24	7		T16	1		T129	13
values[8]	668	1			T24	19		T127	1		T258	11
values[9]	3166	1			T5	1		T7	21		T8	25
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	641	1			T10	7		T129	7		T145	1
values[1]	3135	1			T5	1		T6	1		T8	25
values[2]	680	1			T12	14		T24	15		T28	15
values[3]	717	1			T6	1		T9	2		T15	1
values[4]	779	1			T2	1		T6	1		T11	1
values[5]	490	1			T4	9		T7	8		T9	1
values[6]	935	1			T24	7		T16	1		T129	13
values[7]	554	1			T24	19		T15	7		T127	1
values[8]	762	1			T7	21		T12	1		T138	8
values[9]	245	1			T219	23		T17	38		T153	29
minimum	18571	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T129	1		T145	1		T215	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	5		T139	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T54	11		T151	1		T186	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1808	1			T5	1		T6	1		T8	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T139	2		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T24	12		T28	11		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	1		T9	1		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	1		T215	5		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T6	1		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T127	1		T54	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T132	23		T142	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T7	3		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T24	2		T16	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T166	14		T39	2		T253	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	6		T133	10		T218	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T24	9		T127	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	11		T12	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T138	8		T37	1		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T219	13		T78	1		T285	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T17	16		T153	15		T243	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18227	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T140	13		T286	1		T283	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T129	6		T19	5		T167	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	2		T43	1		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T54	5		T151	10		T223	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1053	1			T26	22		T149	14		T159	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	13		T33	4		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T24	3		T28	4		T54	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T128	1		T153	7		T223	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T178	1		T80	2		T251	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	2		T128	8		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T127	14		T54	13		T128	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T147	10		T18	1		T196	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	8		T7	5		T127	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T24	5		T129	12		T38	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T44	1		T147	4		T221	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	1		T133	9		T218	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T24	10		T16	1		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	10		T37	3		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T37	2		T135	13		T245	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T219	10		T78	12		T285	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T17	22		T153	14		T243	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	5		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T222	10		T169	4		T287	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T151	1		T219	13		T141	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T37	1		T135	13		T17	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T283	1		T180	1		T284	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	5		T129	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	5		T140	13		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T54	11		T151	1		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	1		T126	10		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T139	2		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T24	12		T28	11		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	1		T9	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	1		T54	3		T216	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T16	2		T128	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T127	1		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T132	23		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	1		T7	3		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T24	2		T16	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T166	14		T39	2		T253	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T132	17		T218	8		T136	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T24	9		T127	1		T258	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	11		T12	1		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1668	1			T5	1		T8	25		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T151	10		T219	10		T270	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T37	2		T135	13		T17	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T284	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	2		T129	6		T78	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	2		T153	1		T82	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T54	5		T151	10		T236	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T126	9		T135	13		T152	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	13		T223	1		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T24	3		T28	4		T152	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	7		T223	1		T33	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T54	4		T251	1		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	2		T128	9		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T127	14		T128	15		T178	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T136	9		T201	10		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	8		T7	5		T127	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	5		T129	12		T38	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T165	11		T44	1		T147	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T218	7		T136	13		T201	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T24	10		T224	1		T233	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	10		T15	1		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1076	1			T26	22		T16	1		T149	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T129	7		T145	1		T215	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	7		T139	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T54	6		T151	11		T186	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1412	1			T5	1		T6	1		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	14		T139	2		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T24	4		T28	5		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	1		T9	1		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	1		T215	1		T178	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	1		T6	1		T16	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T127	15		T54	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	1		T142	1		T147	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T4	9		T7	6		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T24	6		T16	1		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T166	1		T39	2		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	6		T133	10		T218	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T24	11		T127	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	11		T12	1		T37	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T138	1		T37	3		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T219	11		T78	13		T285	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T17	29		T153	15		T243	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18365	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T140	1		T286	1		T283	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T215	13		T19	3		T167	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T43	1		T217	16		T82	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T54	10		T217	9		T223	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1449	1			T8	23		T29	24		T45	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T33	9		T155	16		T196	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	11		T28	10		T54	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T140	14		T141	9		T153	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T215	4		T216	17		T254	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T128	8		T218	2		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T54	14		T128	11		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T132	22		T196	10		T220	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	2		T48	17		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T24	1		T38	1		T130	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T166	13		T253	10		T140	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	1		T133	9		T218	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T24	8		T258	10		T238	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	10		T219	9		T257	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T138	7		T135	12		T245	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T219	12		T285	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T17	9		T153	14		T243	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T130	7		T156	15		T288	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T140	12		T222	11		T289	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T151	11		T219	11		T141	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	3		T135	14		T17	29
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	1		T180	1		T284	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	7		T129	7		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	7		T140	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T54	6		T151	11		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	1		T126	10		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	14		T139	2		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T24	4		T28	5		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T9	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T54	5		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	1		T16	4		T128	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	1		T127	15		T128	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	1		T132	1		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	9		T7	6		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T24	6		T16	1		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T166	1		T39	2		T253	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T132	1		T218	8		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T24	11		T127	1		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T7	11		T12	1		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1431	1			T5	1		T8	2		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T219	12		T141	10		T270	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T135	12		T17	9		T153	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T130	7		T215	13		T19	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T140	12		T217	16		T82	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	10		T236	7		T213	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T126	9		T132	9		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T217	9		T223	1		T155	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T24	11		T28	10		T152	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T140	14		T141	9		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T54	2		T216	17		T233	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T128	8		T218	2		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T128	11		T172	8		T215	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T132	22		T136	2		T196	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	2		T54	14		T48	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	1		T38	1		T130	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T166	13		T253	10		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	16		T218	7		T136	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	8		T258	10		T233	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	10		T15	1		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1313	1			T8	23		T29	24		T45	30

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20