Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23836

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3673

1

T7

29

T12

1

T24

41

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21530

1

T1

20

T2

1

T3

16

auto[1]

5979

1

T4

9

T5

1

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	57	1			T219	43		T225	13		T294	1
values[0]	59	1			T12	14		T134	1		T83	1
values[1]	938	1			T2	1		T6	1		T10	7
values[2]	3039	1			T5	1		T8	25		T35	1
values[3]	676	1			T7	8		T9	2		T130	4
values[4]	744	1			T15	8		T37	3		T172	9
values[5]	645	1			T6	1		T24	15		T15	1
values[6]	653	1			T4	9		T6	1		T7	21
values[7]	599	1			T11	1		T14	7		T127	1
values[8]	537	1			T128	27		T178	2		T39	2
values[9]	1239	1			T9	1		T12	1		T28	15
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1142	1			T2	1		T6	1		T10	7
values[1]	3013	1			T5	1		T8	25		T35	1
values[2]	715	1			T7	8		T9	2		T132	23
values[3]	636	1			T6	1		T15	8		T37	3
values[4]	734	1			T6	1		T24	15		T15	1
values[5]	633	1			T4	9		T7	21		T14	7
values[6]	654	1			T11	1		T16	4		T145	1
values[7]	456	1			T128	27		T178	2		T39	2
values[8]	978	1			T9	1		T12	1		T28	15
values[9]	176	1			T132	17		T173	1		T225	13
minimum	18372	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	1		T6	1		T10	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T24	9		T151	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1681	1			T5	1		T8	25		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	1		T17	16		T40	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	2		T132	23		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	3		T136	13		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T6	1		T37	1		T48	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	7		T151	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T15	1		T172	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T24	12		T129	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	1		T14	5		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	11		T24	2		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	1		T16	2		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	17		T165	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T128	12		T39	2		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T178	1		T140	3		T43	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T9	1		T38	5		T219	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T28	11		T127	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T225	1		T18	3		T220	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T132	17		T173	1		T295	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18198	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T98	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T10	2		T12	13		T54	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T24	10		T151	10		T238	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T26	22		T149	14		T37	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	22		T40	3		T153	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T196	3		T233	10		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	5		T136	13		T223	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T37	2		T48	2		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	1		T135	13		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T220	13		T296	9		T297	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T24	3		T129	12		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	8		T14	2		T128	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	10		T24	5		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	2		T147	4		T33	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T152	16		T165	9		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T128	15		T147	10		T190	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T178	1		T43	2		T82	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T38	14		T219	20		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T28	4		T127	28		T54	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T225	12		T18	1		T220	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T169	2		T22	1		T298	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T98	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T219	23		T225	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T12	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T134	1		T83	1		T277	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	1		T6	1		T10	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T24	9		T16	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1694	1			T5	1		T8	25		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T141	11		T216	18		T40	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	2		T130	4		T132	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	3		T136	13		T17	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T37	1		T172	9		T48	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	7		T134	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	1		T15	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T24	12		T151	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T6	1		T128	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	11		T24	2		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T14	5		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T127	1		T139	1		T257	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T128	12		T39	2		T147	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T178	1		T43	5		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T9	1		T38	5		T215	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T12	1		T28	11		T127	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T219	20		T225	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T12	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T277	12		T299	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	2		T54	9		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T24	10		T151	10		T238	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T26	22		T149	14		T37	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	3		T153	14		T234	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T233	10		T226	10		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	5		T136	13		T17	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	2		T48	2		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	1		T135	13		T165	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T220	13		T296	9		T300	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	3		T129	12		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	8		T128	8		T218	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	10		T24	5		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	2		T16	2		T129	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T152	16		T165	9		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T128	15		T147	4		T190	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T178	1		T43	2		T82	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	14		T44	1		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T28	4		T127	28		T54	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T2	1		T6	1		T10	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T24	11		T151	11		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T5	1		T8	2		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	1		T17	29		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	2		T132	1		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	6		T136	14		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	1		T37	3		T48	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T15	7		T151	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	1		T15	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T24	4		T129	13		T135	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	9		T14	7		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	11		T24	6		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	1		T16	4		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	17		T165	10		T154	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T128	16		T39	2		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T178	2		T140	1		T43	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	1		T38	18		T219	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T12	1		T28	5		T127	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T225	13		T18	4		T220	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T132	1		T173	1		T295	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18342	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T98	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T54	12		T126	9		T215	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T24	8		T258	10		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T8	23		T29	24		T45	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	9		T40	4		T153	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	22		T196	3		T233	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	2		T136	12		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T48	17		T155	10		T256	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	1		T132	9		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T172	8		T166	13		T156	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T24	11		T135	12		T136	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T128	8		T130	7		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	10		T24	1		T257	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T147	9		T33	9		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T152	16		T233	7		T22	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T128	11		T156	15		T213	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T140	2		T43	1		T82	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T38	1		T219	21		T215	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T28	10		T138	7		T54	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T220	9		T301	15		T177	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T132	16		T22	1		T302	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T133	9		T303	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T98	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T219	22		T225	13		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T12	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T134	1		T83	1		T277	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T2	1		T6	1		T10	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T24	11		T16	1		T151	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T5	1		T8	2		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T141	1		T216	1		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T130	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	6		T136	14		T17	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T37	3		T172	1		T48	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T15	7		T134	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	1		T15	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	4		T151	1		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	9		T6	1		T128	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	11		T24	6		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T14	7		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T127	1		T139	1		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T128	16		T39	2		T147	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T178	2		T43	6		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	1		T38	18		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T12	1		T28	5		T127	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T219	21		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T277	9		T299	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T54	12		T126	9		T215	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	8		T258	10		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T8	23		T29	24		T45	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T141	10		T216	17		T40	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T130	3		T132	22		T233	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	2		T136	12		T17	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T172	8		T48	17		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	1		T135	12		T217	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T156	13		T269	14		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T24	11		T132	9		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T128	8		T130	7		T218	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	10		T24	1		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	9		T235	10		T155	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T257	2		T152	16		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T128	11		T147	9		T304	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	1		T82	16		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T38	1		T215	4		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T28	10		T138	7		T54	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20