Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21506

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

6003

1

T4

9

T5

1

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21528

1

T1

20

T2

1

T3

16

auto[1]

5981

1

T4

9

T5

1

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	69	1			T219	23		T270	18		T305	1
values[0]	70	1			T283	1		T289	7		T105	17
values[1]	695	1			T10	7		T14	7		T129	7
values[2]	625	1			T6	1		T151	11		T132	10
values[3]	773	1			T24	15		T28	15		T15	1
values[4]	672	1			T6	1		T9	2		T12	14
values[5]	757	1			T6	1		T7	8		T11	1
values[6]	627	1			T2	1		T4	9		T9	1
values[7]	756	1			T24	7		T127	15		T16	1
values[8]	685	1			T7	21		T24	19		T127	1
values[9]	3457	1			T5	1		T8	25		T12	1
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	878	1			T6	1		T10	7		T151	11
values[1]	3146	1			T5	1		T8	25		T35	1
values[2]	631	1			T12	14		T24	15		T28	15
values[3]	805	1			T6	1		T9	2		T15	1
values[4]	697	1			T6	1		T7	8		T11	1
values[5]	602	1			T2	1		T4	9		T9	1
values[6]	812	1			T24	7		T16	1		T129	13
values[7]	580	1			T24	19		T15	7		T127	1
values[8]	746	1			T7	21		T12	1		T138	8
values[9]	282	1			T219	23		T153	29		T78	13
minimum	18330	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T151	1		T129	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	1		T10	5		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T54	11		T186	1		T217	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1855	1			T5	1		T8	25		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T139	2		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T24	12		T28	11		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	1		T9	1		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	1		T54	3		T215	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T16	2		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	3		T11	1		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T38	5		T132	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	1		T9	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T24	2		T16	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T166	14		T39	2		T253	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	6		T133	10		T218	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T24	9		T127	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	11		T12	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	8		T37	1		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T219	13		T78	1		T270	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T153	15		T243	11		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18186	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T151	10		T129	6		T78	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	2		T153	1		T261	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T54	5		T223	1		T236	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1049	1			T26	22		T149	14		T159	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	13		T33	4		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T24	3		T28	4		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T128	9		T153	7		T223	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T54	4		T178	1		T80	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	2		T218	2		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	5		T127	14		T128	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T38	14		T147	10		T196	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T4	8		T127	14		T54	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T24	5		T129	12		T40	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T221	3		T179	10		T22	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	1		T133	9		T218	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T24	10		T16	1		T165	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	10		T37	3		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T37	2		T135	13		T238	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T219	10		T78	12		T270	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T153	14		T243	10		T230	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	5		T15	6		T16	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T219	13		T270	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T305	1		T306	3		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T308	10		T309	3		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T283	1		T289	7		T105	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	5		T129	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	5		T126	10		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	1		T186	1		T223	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	1		T132	10		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	11		T139	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T24	12		T28	11		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	1		T9	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	1		T54	3		T216	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T16	2		T128	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	3		T11	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	1		T132	23		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	1		T9	1		T54	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T24	2		T16	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T127	1		T166	14		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	11		T132	17		T218	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	9		T127	1		T258	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	1		T15	6		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1743	1			T5	1		T8	25		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T219	10		T270	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T306	8		T307	12		T310	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T308	11		T309	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T105	7		T284	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	2		T129	6		T78	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	2		T126	9		T82	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T151	10		T223	1		T236	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T135	13		T201	12		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T54	5		T155	13		T196	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T24	3		T28	4		T152	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	13		T153	7		T223	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T54	4		T80	2		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	2		T128	9		T201	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	5		T127	14		T128	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T218	2		T136	9		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	8		T54	13		T48	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	5		T129	12		T38	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T127	14		T165	11		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	10		T218	7		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T24	10		T224	1		T233	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T15	1		T37	3		T151	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1185	1			T26	22		T16	1		T149	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T151	11		T129	7		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	1		T10	7		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T54	6		T186	1		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1412	1			T5	1		T8	2		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	14		T139	2		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	4		T28	5		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T9	1		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	1		T54	5		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	1		T16	4		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	6		T11	1		T127	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T38	18		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	9		T9	1		T127	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T24	6		T16	1		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T166	1		T39	2		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	6		T133	10		T218	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T24	11		T127	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	11		T12	1		T37	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T138	1		T37	3		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T219	11		T78	13		T270	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T153	15		T243	11		T230	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18330	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T130	7		T215	13		T19	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T140	12		T82	11		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T54	10		T217	9		T223	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1492	1			T8	23		T29	24		T45	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T33	9		T155	16		T196	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	11		T28	10		T152	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T128	8		T140	14		T141	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T54	2		T215	4		T216	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T218	2		T136	2		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	2		T128	11		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	1		T132	22		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T54	14		T48	17		T140	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T24	1		T130	3		T132	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T166	13		T253	10		T221	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	1		T133	9		T218	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T24	8		T258	10		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	10		T219	9		T257	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T138	7		T135	12		T238	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T219	12		T270	8		T174	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T153	14		T243	10		T304	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T219	11		T270	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T305	1		T306	9		T307	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T308	12		T309	11		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T283	1		T289	1		T105	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	7		T129	7		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	7		T126	10		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T151	11		T186	1		T223	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	1		T132	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T54	6		T139	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T24	4		T28	5		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	1		T9	1		T12	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	1		T54	5		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	1		T16	4		T128	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	6		T11	1		T127	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	1		T132	1		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	9		T9	1		T54	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T24	6		T16	1		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T127	15		T166	1		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	11		T132	1		T218	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	11		T127	1		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T12	1		T15	6		T37	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1560	1			T5	1		T8	2		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T219	12		T270	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T306	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T308	9		T309	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T289	6		T105	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	7		T215	13		T19	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T126	9		T140	12		T217	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T223	1		T236	7		T268	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T132	9		T135	12		T201	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T54	10		T217	9		T155	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T24	11		T28	10		T152	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T140	14		T141	9		T153	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T54	2		T216	17		T80	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T128	8		T156	13		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	2		T128	11		T172	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T132	22		T218	2		T136	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T54	14		T48	17		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	1		T38	1		T130	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T166	13		T253	10		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	10		T132	16		T218	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T24	8		T258	10		T233	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	1		T219	9		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1368	1			T8	23		T29	24		T45	30

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20