Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23744

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3765

1

T4

9

T6

1

T7

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21639

1

T1

20

T3

16

T4

9

auto[1]

5870

1

T2

1

T5

1

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	335	1			T24	15		T166	1		T165	12
values[0]	23	1			T2	1		T6	1		T20	2
values[1]	760	1			T7	21		T24	19		T15	1
values[2]	642	1			T7	8		T14	7		T54	28
values[3]	704	1			T4	9		T127	16		T129	13
values[4]	754	1			T9	2		T28	15		T54	7
values[5]	812	1			T12	14		T151	23		T38	19
values[6]	652	1			T9	1		T11	1		T37	4
values[7]	693	1			T6	2		T15	7		T54	16
values[8]	626	1			T12	1		T24	7		T15	1
values[9]	3185	1			T5	1		T8	25		T10	7
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	674	1			T2	1		T7	21		T24	19
values[1]	656	1			T7	8		T14	7		T37	3
values[2]	755	1			T4	9		T127	16		T129	13
values[3]	843	1			T9	2		T28	15		T54	7
values[4]	659	1			T12	14		T37	4		T151	23
values[5]	652	1			T6	2		T9	1		T11	1
values[6]	3095	1			T5	1		T8	25		T12	1
values[7]	597	1			T15	1		T16	3		T138	8
values[8]	846	1			T10	7		T24	15		T127	15
values[9]	160	1			T134	1		T165	12		T195	1
minimum	18572	1			T1	20		T3	16		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	1		T24	9		T15	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	11		T16	2		T130	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	5		T37	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	3		T128	9		T201	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T127	1		T219	10		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	1		T127	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	2		T219	13		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T28	11		T54	3		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T151	1		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T37	1		T151	2		T257	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T9	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T11	1		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1707	1			T5	1		T8	25		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T54	11		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	1		T16	2		T138	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T132	23		T39	2		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	5		T128	1		T215	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T24	12		T127	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T195	1		T311	1		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T134	1		T165	1		T271	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18252	1			T1	20		T3	16		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T216	7		T153	1		T312	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	10		T54	13		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	10		T16	2		T135	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	2		T37	2		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	5		T128	8		T201	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T127	14		T219	10		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	8		T129	12		T135	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T219	10		T155	13		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T28	4		T54	4		T38	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	13		T151	10		T133	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T37	3		T151	10		T223	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T178	1		T78	12		T221	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T128	15		T155	9		T222	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T24	5		T26	22		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	5		T129	6		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	1		T152	2		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T147	10		T196	1		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	2		T128	1		T165	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	3		T127	14		T33	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T23	4		T262	2		T313	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T165	11		T264	12		T262	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T153	1		T312	2		T96	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T166	1		T195	1		T286	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	12		T165	1		T33	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T2	1		T6	1		T20	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	9		T15	1		T130	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	11		T16	2		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	5		T54	15		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	3		T128	9		T201	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T127	1		T136	13		T152	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	1		T127	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	2		T219	10		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T28	11		T54	3		T48	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T151	1		T219	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T151	2		T38	5		T218	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	1		T178	1		T218	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T37	1		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	1		T15	6		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	1		T54	11		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T24	2		T15	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T129	1		T132	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T5	1		T8	25		T10	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T127	1		T145	1		T132	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T179	10		T246	11		T23	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T24	3		T165	11		T33	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T266	4		T314	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T24	10		T126	9		T223	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	10		T16	2		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	2		T54	13		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	5		T128	8		T201	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T127	14		T136	13		T152	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	8		T129	12		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T219	10		T201	9		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	4		T54	4		T48	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	13		T151	10		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T151	10		T38	14		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T178	1		T218	2		T223	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	3		T128	15		T223	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	1		T78	14		T221	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T54	5		T261	10		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T24	5		T16	1		T152	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T129	6		T147	10		T196	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T10	2		T26	22		T149	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T127	14		T18	1		T233	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T24	11		T15	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	11		T16	4		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	7		T37	3		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	6		T128	9		T201	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	15		T219	11		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	9		T127	1		T129	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	2		T219	11		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T28	5		T54	5		T38	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	14		T151	11		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T37	4		T151	12		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T9	1		T178	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T11	1		T128	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T5	1		T8	2		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T54	6		T129	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	1		T16	3		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T132	1		T39	2		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	7		T128	2		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T24	4		T127	15		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T195	1		T311	1		T23	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T134	1		T165	12		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18416	1			T1	20		T3	16		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T216	1		T153	2		T312	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T24	8		T54	14		T130	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	10		T130	3		T215	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T221	2		T268	2		T98	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	2		T128	8		T201	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T219	9		T136	12		T152	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	12		T136	2		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T219	12		T217	16		T252	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T28	10		T54	2		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T133	9		T223	1		T221	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T257	2		T84	8		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T140	2		T269	14		T270	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T128	11		T141	10		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T8	23		T24	1		T29	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	10		T141	12		T80	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T138	7		T152	4		T238	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T132	22		T233	14		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T215	4		T132	9		T153	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T24	11		T132	16		T140	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T23	1		T262	7		T313	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T271	12		T264	10		T262	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T245	6		T82	11		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T216	6		T312	7		T302	21

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T166	1		T195	1		T286	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T24	4		T165	12		T33	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T2	1		T6	1		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T24	11		T15	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	11		T16	4		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	7		T54	14		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	6		T128	9		T201	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	15		T136	14		T152	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	9		T127	1		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	2		T219	11		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	5		T54	5		T48	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	14		T151	11		T219	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T151	12		T38	18		T218	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T178	2		T218	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	1		T37	4		T128	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T15	6		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	1		T54	6		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T24	6		T15	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T129	7		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T5	1		T8	2		T10	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T127	15		T145	1		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T156	15		T246	6		T23	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T24	11		T33	9		T235	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T20	1		T266	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	8		T130	7		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	10		T130	3		T215	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T54	14		T172	8		T258	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	2		T128	8		T201	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T136	12		T152	16		T222	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T135	12		T136	2		T217	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T219	9		T201	11		T217	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T28	10		T54	2		T48	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T219	12		T133	9		T155	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	1		T218	7		T84	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T218	2		T140	2		T223	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T128	11		T257	2		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	1		T156	22		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T54	10		T141	22		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T24	1		T138	7		T152	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T132	22		T237	9		T22	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T8	23		T29	24		T45	30
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T132	16		T140	14		T141	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20