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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.19


Total test records in report: 919
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T76 /workspace/coverage/default/1.adc_ctrl_sec_cm.412312490 Jul 01 11:14:02 AM PDT 24 Jul 01 11:14:22 AM PDT 24 7562050063 ps
T793 /workspace/coverage/default/19.adc_ctrl_fsm_reset.4167309542 Jul 01 11:15:15 AM PDT 24 Jul 01 11:20:49 AM PDT 24 107630316089 ps
T284 /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1042080117 Jul 01 11:15:38 AM PDT 24 Jul 01 11:24:40 AM PDT 24 493637083997 ps
T794 /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1442618548 Jul 01 11:15:55 AM PDT 24 Jul 01 11:17:47 AM PDT 24 36520901233 ps
T58 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.782973073 Jul 01 10:38:58 AM PDT 24 Jul 01 10:39:00 AM PDT 24 552917784 ps
T795 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4215441631 Jul 01 10:39:41 AM PDT 24 Jul 01 10:39:46 AM PDT 24 479229099 ps
T796 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3719365831 Jul 01 10:39:29 AM PDT 24 Jul 01 10:39:31 AM PDT 24 403137807 ps
T121 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1853032156 Jul 01 10:40:03 AM PDT 24 Jul 01 10:40:10 AM PDT 24 2491287213 ps
T50 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.336789550 Jul 01 10:39:28 AM PDT 24 Jul 01 10:39:33 AM PDT 24 2159161654 ps
T59 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2612806443 Jul 01 10:39:28 AM PDT 24 Jul 01 10:39:32 AM PDT 24 721435447 ps
T60 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1905843962 Jul 01 10:39:05 AM PDT 24 Jul 01 10:39:09 AM PDT 24 538869703 ps
T122 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.834979731 Jul 01 10:39:05 AM PDT 24 Jul 01 10:39:08 AM PDT 24 508467842 ps
T66 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1634343168 Jul 01 10:39:11 AM PDT 24 Jul 01 10:39:15 AM PDT 24 567500680 ps
T53 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.890131306 Jul 01 10:39:59 AM PDT 24 Jul 01 10:40:03 AM PDT 24 548981393 ps
T87 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2483384332 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:39 AM PDT 24 523013200 ps
T64 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2487701736 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:09 AM PDT 24 377515506 ps
T108 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2290263499 Jul 01 10:39:10 AM PDT 24 Jul 01 10:39:17 AM PDT 24 1056968826 ps
T65 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.812958262 Jul 01 10:39:15 AM PDT 24 Jul 01 10:39:19 AM PDT 24 855930695 ps
T69 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1174297229 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:40 AM PDT 24 432781860 ps
T797 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1643898992 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:08 AM PDT 24 326017949 ps
T70 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1355315749 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:13 AM PDT 24 590640568 ps
T71 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.489506497 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:08 AM PDT 24 928772199 ps
T55 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.747825469 Jul 01 10:39:26 AM PDT 24 Jul 01 10:39:50 AM PDT 24 9028731931 ps
T51 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1089658619 Jul 01 10:39:01 AM PDT 24 Jul 01 10:39:04 AM PDT 24 2698652487 ps
T56 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2843932221 Jul 01 10:39:01 AM PDT 24 Jul 01 10:39:12 AM PDT 24 4001201864 ps
T798 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1281995840 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:39 AM PDT 24 292622594 ps
T799 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.790407579 Jul 01 10:39:29 AM PDT 24 Jul 01 10:39:32 AM PDT 24 370632494 ps
T109 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.325114960 Jul 01 10:39:20 AM PDT 24 Jul 01 10:39:22 AM PDT 24 632293238 ps
T110 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4016884672 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:32 AM PDT 24 1379735038 ps
T57 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.186946396 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:19 AM PDT 24 4624686282 ps
T800 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.926020791 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:08 AM PDT 24 552997284 ps
T801 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2418413902 Jul 01 10:40:04 AM PDT 24 Jul 01 10:40:12 AM PDT 24 525453975 ps
T802 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3930457701 Jul 01 10:39:25 AM PDT 24 Jul 01 10:39:29 AM PDT 24 648281817 ps
T333 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2139796800 Jul 01 10:39:44 AM PDT 24 Jul 01 10:40:09 AM PDT 24 8170013512 ps
T803 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4264394596 Jul 01 10:39:28 AM PDT 24 Jul 01 10:39:30 AM PDT 24 385387092 ps
T804 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1109599600 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 321394593 ps
T111 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2220384545 Jul 01 10:40:28 AM PDT 24 Jul 01 10:40:31 AM PDT 24 606455972 ps
T805 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2696274351 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 360894367 ps
T806 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4208862459 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:30 AM PDT 24 556845586 ps
T807 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1716059971 Jul 01 10:40:05 AM PDT 24 Jul 01 10:40:07 AM PDT 24 412749396 ps
T808 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.631844268 Jul 01 10:39:08 AM PDT 24 Jul 01 10:39:12 AM PDT 24 385844412 ps
T809 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4062008570 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 323913888 ps
T810 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4274836799 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:32 AM PDT 24 456251201 ps
T811 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3627283788 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:34 AM PDT 24 296896630 ps
T123 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.588241351 Jul 01 10:39:21 AM PDT 24 Jul 01 10:39:24 AM PDT 24 586134489 ps
T812 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.595146103 Jul 01 10:39:19 AM PDT 24 Jul 01 10:39:21 AM PDT 24 598784623 ps
T124 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.209629653 Jul 01 10:40:05 AM PDT 24 Jul 01 10:40:10 AM PDT 24 2072917811 ps
T813 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4261534740 Jul 01 10:40:05 AM PDT 24 Jul 01 10:40:07 AM PDT 24 444055399 ps
T52 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2903721183 Jul 01 10:38:53 AM PDT 24 Jul 01 10:39:20 AM PDT 24 26657468163 ps
T814 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3084522310 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:10 AM PDT 24 452156641 ps
T815 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3740048342 Jul 01 10:39:22 AM PDT 24 Jul 01 10:39:24 AM PDT 24 1410478692 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3801941509 Jul 01 10:39:05 AM PDT 24 Jul 01 10:39:18 AM PDT 24 4846844483 ps
T816 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2574416349 Jul 01 10:39:08 AM PDT 24 Jul 01 10:39:23 AM PDT 24 2906753740 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1378150951 Jul 01 10:40:21 AM PDT 24 Jul 01 10:40:26 AM PDT 24 378599391 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.816033470 Jul 01 10:39:44 AM PDT 24 Jul 01 10:39:54 AM PDT 24 4119540139 ps
T818 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.840790970 Jul 01 10:39:08 AM PDT 24 Jul 01 10:39:18 AM PDT 24 8249197322 ps
T819 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3514692289 Jul 01 10:39:21 AM PDT 24 Jul 01 10:39:23 AM PDT 24 476589704 ps
T820 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1825380429 Jul 01 10:40:25 AM PDT 24 Jul 01 10:40:28 AM PDT 24 307113591 ps
T821 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1554202030 Jul 01 10:39:05 AM PDT 24 Jul 01 10:39:10 AM PDT 24 312151578 ps
T822 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3391780640 Jul 01 10:39:00 AM PDT 24 Jul 01 10:39:03 AM PDT 24 405793531 ps
T823 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3265404592 Jul 01 10:39:03 AM PDT 24 Jul 01 10:40:17 AM PDT 24 52342508012 ps
T113 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1175472647 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:16 AM PDT 24 302314989 ps
T824 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3335853391 Jul 01 10:39:21 AM PDT 24 Jul 01 10:39:23 AM PDT 24 365467767 ps
T825 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.853642106 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:42 AM PDT 24 488270491 ps
T826 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2498257969 Jul 01 10:39:07 AM PDT 24 Jul 01 10:39:16 AM PDT 24 4241687337 ps
T827 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3428338569 Jul 01 10:39:59 AM PDT 24 Jul 01 10:40:01 AM PDT 24 483345040 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1751962913 Jul 01 10:39:18 AM PDT 24 Jul 01 10:39:22 AM PDT 24 436915604 ps
T115 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3366235481 Jul 01 10:39:05 AM PDT 24 Jul 01 10:39:09 AM PDT 24 313666796 ps
T828 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3880426094 Jul 01 10:39:42 AM PDT 24 Jul 01 10:39:51 AM PDT 24 452125548 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1162505290 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:47 AM PDT 24 554560480 ps
T830 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2119078646 Jul 01 10:39:33 AM PDT 24 Jul 01 10:39:37 AM PDT 24 573058311 ps
T116 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2850635979 Jul 01 10:39:15 AM PDT 24 Jul 01 10:39:18 AM PDT 24 401514198 ps
T831 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2319640876 Jul 01 10:39:14 AM PDT 24 Jul 01 10:39:18 AM PDT 24 560583699 ps
T120 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.626351494 Jul 01 10:39:26 AM PDT 24 Jul 01 10:39:28 AM PDT 24 467233653 ps
T832 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1252882767 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:47 AM PDT 24 336698176 ps
T833 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4090619681 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:40 AM PDT 24 341724520 ps
T834 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2790639986 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 435886375 ps
T835 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3109633385 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:03 AM PDT 24 4206006998 ps
T117 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4195992542 Jul 01 10:39:37 AM PDT 24 Jul 01 10:39:44 AM PDT 24 434912215 ps
T836 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2024699487 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:33 AM PDT 24 326177420 ps
T837 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1695229863 Jul 01 10:39:25 AM PDT 24 Jul 01 10:39:38 AM PDT 24 4176000362 ps
T838 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2870153035 Jul 01 10:39:08 AM PDT 24 Jul 01 10:39:13 AM PDT 24 808964465 ps
T839 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.115074663 Jul 01 10:39:18 AM PDT 24 Jul 01 10:39:22 AM PDT 24 981513786 ps
T840 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3959108542 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:05 AM PDT 24 425624170 ps
T841 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2324289458 Jul 01 10:39:25 AM PDT 24 Jul 01 10:39:27 AM PDT 24 544352320 ps
T842 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2246216663 Jul 01 10:39:14 AM PDT 24 Jul 01 10:39:16 AM PDT 24 482140517 ps
T843 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.869686634 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:44 AM PDT 24 508945375 ps
T844 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3949382413 Jul 01 10:38:58 AM PDT 24 Jul 01 10:39:01 AM PDT 24 2993177030 ps
T845 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.31712035 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:34 AM PDT 24 290009804 ps
T846 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.124302744 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:42 AM PDT 24 5009053963 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2218038715 Jul 01 10:39:21 AM PDT 24 Jul 01 10:39:32 AM PDT 24 4464254765 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1519711411 Jul 01 10:40:32 AM PDT 24 Jul 01 10:40:35 AM PDT 24 482427903 ps
T849 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2383606642 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:39 AM PDT 24 5407810645 ps
T850 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4022957849 Jul 01 10:39:12 AM PDT 24 Jul 01 10:39:15 AM PDT 24 518632616 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.76653374 Jul 01 10:39:26 AM PDT 24 Jul 01 10:39:29 AM PDT 24 1389092561 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4051162506 Jul 01 10:39:25 AM PDT 24 Jul 01 10:39:47 AM PDT 24 26341858055 ps
T852 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3929779467 Jul 01 10:38:56 AM PDT 24 Jul 01 10:38:58 AM PDT 24 366847727 ps
T853 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3091879406 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:41 AM PDT 24 508173984 ps
T72 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4253590778 Jul 01 10:39:00 AM PDT 24 Jul 01 10:39:04 AM PDT 24 4300286633 ps
T854 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3271109958 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:53 AM PDT 24 7839284690 ps
T855 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.969054269 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:36 AM PDT 24 4476859681 ps
T856 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.489917892 Jul 01 10:39:10 AM PDT 24 Jul 01 10:39:16 AM PDT 24 593832072 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1629397202 Jul 01 10:39:12 AM PDT 24 Jul 01 10:39:15 AM PDT 24 326880186 ps
T119 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1158297708 Jul 01 10:39:11 AM PDT 24 Jul 01 10:39:14 AM PDT 24 495125040 ps
T858 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.863773834 Jul 01 10:40:20 AM PDT 24 Jul 01 10:40:25 AM PDT 24 296996267 ps
T859 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1498224428 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:29 AM PDT 24 529506670 ps
T860 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2981868325 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:41 AM PDT 24 494514943 ps
T861 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1498064162 Jul 01 10:40:27 AM PDT 24 Jul 01 10:40:31 AM PDT 24 1394725479 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3010132691 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:07 AM PDT 24 2491353258 ps
T863 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.212249701 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:09 AM PDT 24 723641308 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.126617188 Jul 01 10:39:35 AM PDT 24 Jul 01 10:39:43 AM PDT 24 4727365454 ps
T865 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.393291890 Jul 01 10:39:19 AM PDT 24 Jul 01 10:39:23 AM PDT 24 529262531 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1794398229 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 291548890 ps
T867 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2893433526 Jul 01 10:39:56 AM PDT 24 Jul 01 10:40:05 AM PDT 24 4086825873 ps
T868 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1355013725 Jul 01 10:39:17 AM PDT 24 Jul 01 10:39:20 AM PDT 24 352177244 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3920949376 Jul 01 10:40:25 AM PDT 24 Jul 01 10:40:29 AM PDT 24 618337895 ps
T870 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4193853196 Jul 01 10:39:01 AM PDT 24 Jul 01 10:39:13 AM PDT 24 2843798468 ps
T871 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.857851040 Jul 01 10:39:02 AM PDT 24 Jul 01 10:39:06 AM PDT 24 4601421869 ps
T872 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1248032723 Jul 01 10:39:27 AM PDT 24 Jul 01 10:39:33 AM PDT 24 4510675973 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3976305165 Jul 01 10:39:12 AM PDT 24 Jul 01 10:39:15 AM PDT 24 458895410 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1402785930 Jul 01 10:39:18 AM PDT 24 Jul 01 10:39:20 AM PDT 24 448387658 ps
T875 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1213491058 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:33 AM PDT 24 405832927 ps
T876 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.518177819 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:44 AM PDT 24 4628958475 ps
T877 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2500156241 Jul 01 10:40:04 AM PDT 24 Jul 01 10:40:10 AM PDT 24 4703133377 ps
T878 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3141867096 Jul 01 10:38:58 AM PDT 24 Jul 01 10:39:00 AM PDT 24 375409593 ps
T879 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3406266301 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:33 AM PDT 24 307947080 ps
T880 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2196499668 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:42 AM PDT 24 430429064 ps
T881 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.588400611 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:35 AM PDT 24 533943846 ps
T882 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.895300871 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:35 AM PDT 24 493114094 ps
T883 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3901211466 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:43 AM PDT 24 4823797947 ps
T884 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1998871760 Jul 01 10:39:01 AM PDT 24 Jul 01 10:39:03 AM PDT 24 535271925 ps
T334 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1011357207 Jul 01 10:39:10 AM PDT 24 Jul 01 10:39:18 AM PDT 24 3992766527 ps
T885 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2520366897 Jul 01 10:39:19 AM PDT 24 Jul 01 10:39:22 AM PDT 24 623412685 ps
T886 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3823621630 Jul 01 10:39:24 AM PDT 24 Jul 01 10:39:36 AM PDT 24 2660159445 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3334709898 Jul 01 10:39:30 AM PDT 24 Jul 01 10:39:34 AM PDT 24 1562537143 ps
T888 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.862957836 Jul 01 10:39:31 AM PDT 24 Jul 01 10:39:34 AM PDT 24 313880411 ps
T73 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1509672421 Jul 01 10:40:27 AM PDT 24 Jul 01 10:40:36 AM PDT 24 8575822501 ps
T889 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1820179315 Jul 01 10:39:13 AM PDT 24 Jul 01 10:40:58 AM PDT 24 26380328278 ps
T890 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3887414023 Jul 01 10:39:36 AM PDT 24 Jul 01 10:39:40 AM PDT 24 480499900 ps
T891 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1633246049 Jul 01 10:40:15 AM PDT 24 Jul 01 10:40:18 AM PDT 24 310231887 ps
T892 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.806263815 Jul 01 10:39:13 AM PDT 24 Jul 01 10:39:16 AM PDT 24 2472657772 ps
T893 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.633983353 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:44 AM PDT 24 387220785 ps
T894 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.21963976 Jul 01 10:39:34 AM PDT 24 Jul 01 10:39:38 AM PDT 24 1131132636 ps
T895 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1367861331 Jul 01 10:39:29 AM PDT 24 Jul 01 10:39:39 AM PDT 24 2990968215 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.815643499 Jul 01 10:40:01 AM PDT 24 Jul 01 10:40:22 AM PDT 24 5097986694 ps
T897 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.596085852 Jul 01 10:40:33 AM PDT 24 Jul 01 10:40:36 AM PDT 24 365186267 ps
T898 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2860872619 Jul 01 10:39:26 AM PDT 24 Jul 01 10:39:29 AM PDT 24 368884322 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3155152562 Jul 01 10:38:59 AM PDT 24 Jul 01 10:39:02 AM PDT 24 391411202 ps
T900 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1464317335 Jul 01 10:39:39 AM PDT 24 Jul 01 10:39:45 AM PDT 24 632752367 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.369647227 Jul 01 10:39:16 AM PDT 24 Jul 01 10:39:18 AM PDT 24 551996498 ps
T902 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.872652571 Jul 01 10:39:16 AM PDT 24 Jul 01 10:39:18 AM PDT 24 590841451 ps
T903 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1577069993 Jul 01 10:40:28 AM PDT 24 Jul 01 10:40:31 AM PDT 24 380935173 ps
T904 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.553286177 Jul 01 10:39:15 AM PDT 24 Jul 01 10:39:17 AM PDT 24 672527043 ps
T905 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1403438558 Jul 01 10:39:38 AM PDT 24 Jul 01 10:39:43 AM PDT 24 513813741 ps
T906 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3945035029 Jul 01 10:39:17 AM PDT 24 Jul 01 10:39:20 AM PDT 24 661399642 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3278240196 Jul 01 10:39:16 AM PDT 24 Jul 01 10:39:19 AM PDT 24 465068560 ps
T908 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1385069435 Jul 01 10:39:03 AM PDT 24 Jul 01 10:39:09 AM PDT 24 816122281 ps
T909 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2603203432 Jul 01 10:39:19 AM PDT 24 Jul 01 10:39:22 AM PDT 24 399804774 ps
T910 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3076108861 Jul 01 10:40:25 AM PDT 24 Jul 01 10:40:30 AM PDT 24 414714650 ps
T911 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.484119776 Jul 01 10:39:04 AM PDT 24 Jul 01 10:39:08 AM PDT 24 408925243 ps
T74 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1953559823 Jul 01 10:40:30 AM PDT 24 Jul 01 10:40:39 AM PDT 24 8117763129 ps
T912 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3714161013 Jul 01 10:39:24 AM PDT 24 Jul 01 10:39:26 AM PDT 24 756312661 ps
T913 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.580508108 Jul 01 10:39:28 AM PDT 24 Jul 01 10:39:35 AM PDT 24 4334868329 ps
T914 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1239107547 Jul 01 10:39:44 AM PDT 24 Jul 01 10:39:48 AM PDT 24 443908423 ps
T915 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3738713679 Jul 01 10:39:00 AM PDT 24 Jul 01 10:39:10 AM PDT 24 4060467157 ps
T916 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3286651824 Jul 01 10:39:16 AM PDT 24 Jul 01 10:39:19 AM PDT 24 544934059 ps
T917 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1900676204 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:46 AM PDT 24 16704956386 ps
T918 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.670194947 Jul 01 10:39:32 AM PDT 24 Jul 01 10:39:36 AM PDT 24 636655975 ps
T919 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3560388550 Jul 01 10:39:06 AM PDT 24 Jul 01 10:39:10 AM PDT 24 427894339 ps

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1746396963
Short name T7
Test name
Test status
Simulation time 555122247042 ps
CPU time 452.77 seconds
Started Jul 01 11:15:42 AM PDT 24
Finished Jul 01 11:23:56 AM PDT 24
Peak memory 210436 kb
Host smart-279ad2ad-82f5-4219-ae68-942fec8d16dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746396963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1746396963
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4285398656
Short name T14
Test name
Test status
Simulation time 113284426206 ps
CPU time 149.93 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:16:55 AM PDT 24
Peak memory 217976 kb
Host smart-0226bfe9-7a96-47b7-a71a-c250105edaf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285398656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4285398656
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.241951105
Short name T16
Test name
Test status
Simulation time 390133860494 ps
CPU time 272.52 seconds
Started Jul 01 11:16:16 AM PDT 24
Finished Jul 01 11:22:26 AM PDT 24
Peak memory 210488 kb
Host smart-3de17355-9267-4fc7-aa7f-83862b6a805b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241951105 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.241951105
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3029229115
Short name T24
Test name
Test status
Simulation time 544602212656 ps
CPU time 1154.39 seconds
Started Jul 01 11:16:01 AM PDT 24
Finished Jul 01 11:36:34 AM PDT 24
Peak memory 201900 kb
Host smart-d7486e39-f9a8-4f9b-a079-cff906d43308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029229115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3029229115
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.741118927
Short name T136
Test name
Test status
Simulation time 532515848393 ps
CPU time 504.46 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:23:11 AM PDT 24
Peak memory 201824 kb
Host smart-2c5d3b6f-8341-4fde-ad6b-c2f603aeb9b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741118927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.741118927
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3558112072
Short name T155
Test name
Test status
Simulation time 564333960881 ps
CPU time 328.39 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:21:05 AM PDT 24
Peak memory 201944 kb
Host smart-9a57bb5f-f03d-4a4f-9280-e37978d76d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558112072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3558112072
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1373952544
Short name T10
Test name
Test status
Simulation time 99830678163 ps
CPU time 168.29 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:17:28 AM PDT 24
Peak memory 210520 kb
Host smart-3c6a37f4-ca2a-4f5b-acb3-692295345250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373952544 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1373952544
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4242429474
Short name T223
Test name
Test status
Simulation time 198166414809 ps
CPU time 106.57 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:16:18 AM PDT 24
Peak memory 218356 kb
Host smart-616cd3bc-7ac9-47c7-a9ec-a6896a41b62f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242429474 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4242429474
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1318684277
Short name T140
Test name
Test status
Simulation time 615130769120 ps
CPU time 242.18 seconds
Started Jul 01 11:15:46 AM PDT 24
Finished Jul 01 11:20:37 AM PDT 24
Peak memory 201888 kb
Host smart-db5bc13f-db64-48c3-be14-c55f03f9472e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318684277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1318684277
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1424018747
Short name T54
Test name
Test status
Simulation time 498132110962 ps
CPU time 1079.68 seconds
Started Jul 01 11:16:00 AM PDT 24
Finished Jul 01 11:35:20 AM PDT 24
Peak memory 201760 kb
Host smart-87da3280-15c5-460b-9011-9771569c1272
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424018747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1424018747
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.812958262
Short name T65
Test name
Test status
Simulation time 855930695 ps
CPU time 2.39 seconds
Started Jul 01 10:39:15 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 209884 kb
Host smart-75a551c4-c564-4f35-9aea-5b4b6059f798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812958262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.812958262
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2897952887
Short name T219
Test name
Test status
Simulation time 326507161053 ps
CPU time 789.25 seconds
Started Jul 01 11:17:59 AM PDT 24
Finished Jul 01 11:31:30 AM PDT 24
Peak memory 201940 kb
Host smart-f4731757-18fd-405d-b391-161429c122a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897952887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2897952887
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.501596926
Short name T221
Test name
Test status
Simulation time 72565846443 ps
CPU time 81.52 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:16:10 AM PDT 24
Peak memory 210168 kb
Host smart-9936f104-5145-47f6-9efe-55bd6fa4e6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501596926 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.501596926
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1428652081
Short name T153
Test name
Test status
Simulation time 522028660973 ps
CPU time 839.25 seconds
Started Jul 01 11:17:56 AM PDT 24
Finished Jul 01 11:32:19 AM PDT 24
Peak memory 201820 kb
Host smart-f733eb3d-4ae5-4c18-b720-a45bf776f64d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428652081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1428652081
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2048581178
Short name T147
Test name
Test status
Simulation time 545560110489 ps
CPU time 927.43 seconds
Started Jul 01 11:15:08 AM PDT 24
Finished Jul 01 11:30:37 AM PDT 24
Peak memory 201904 kb
Host smart-57a2fd1b-6427-43ee-9a5b-dcb325fc0f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048581178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2048581178
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.762034863
Short name T29
Test name
Test status
Simulation time 396491488868 ps
CPU time 784.2 seconds
Started Jul 01 11:15:26 AM PDT 24
Finished Jul 01 11:28:36 AM PDT 24
Peak memory 201848 kb
Host smart-cc69e596-f9ad-48e2-b335-b7123681854a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762034863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.762034863
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3957597208
Short name T67
Test name
Test status
Simulation time 346163566 ps
CPU time 0.73 seconds
Started Jul 01 11:14:49 AM PDT 24
Finished Jul 01 11:14:51 AM PDT 24
Peak memory 201512 kb
Host smart-cd50f097-e3cf-42ab-b470-a51b23612639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957597208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3957597208
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.890131306
Short name T53
Test name
Test status
Simulation time 548981393 ps
CPU time 2.09 seconds
Started Jul 01 10:39:59 AM PDT 24
Finished Jul 01 10:40:03 AM PDT 24
Peak memory 200060 kb
Host smart-796718f7-cf16-4cf3-856e-0abc2ebed4d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890131306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.890131306
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3394553950
Short name T201
Test name
Test status
Simulation time 562829217744 ps
CPU time 1505.64 seconds
Started Jul 01 11:17:58 AM PDT 24
Finished Jul 01 11:43:26 AM PDT 24
Peak memory 202072 kb
Host smart-c4ae39d8-29f2-4857-89d1-fe1d5991ef61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394553950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3394553950
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2097556580
Short name T75
Test name
Test status
Simulation time 3967818154 ps
CPU time 9.52 seconds
Started Jul 01 11:14:34 AM PDT 24
Finished Jul 01 11:14:44 AM PDT 24
Peak memory 217108 kb
Host smart-2b14104d-4ca7-4219-84f3-a8eec47f6ab4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097556580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2097556580
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3236477304
Short name T220
Test name
Test status
Simulation time 596739991023 ps
CPU time 213.92 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:18:29 AM PDT 24
Peak memory 201860 kb
Host smart-24821ea6-ae4d-42de-895a-8f0076a4ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236477304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3236477304
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1842801684
Short name T128
Test name
Test status
Simulation time 513770301983 ps
CPU time 764.73 seconds
Started Jul 01 11:15:46 AM PDT 24
Finished Jul 01 11:29:20 AM PDT 24
Peak memory 201936 kb
Host smart-5f75654e-9fdb-45d9-a17f-a84436399068
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842801684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1842801684
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2953503042
Short name T233
Test name
Test status
Simulation time 491795707036 ps
CPU time 549.5 seconds
Started Jul 01 11:15:27 AM PDT 24
Finished Jul 01 11:24:41 AM PDT 24
Peak memory 201860 kb
Host smart-694d75cf-b63c-4109-82e9-0420857b27e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953503042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2953503042
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.429592663
Short name T215
Test name
Test status
Simulation time 452228841753 ps
CPU time 981.89 seconds
Started Jul 01 11:14:13 AM PDT 24
Finished Jul 01 11:30:35 AM PDT 24
Peak memory 201932 kb
Host smart-ac921ff7-6876-454d-91aa-58963d2da30a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429592663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.429592663
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4078614689
Short name T82
Test name
Test status
Simulation time 496329419578 ps
CPU time 247.81 seconds
Started Jul 01 11:15:47 AM PDT 24
Finished Jul 01 11:20:49 AM PDT 24
Peak memory 201872 kb
Host smart-f76f9ef7-4967-4078-856f-a5400e506723
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078614689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4078614689
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4143807585
Short name T23
Test name
Test status
Simulation time 107226484907 ps
CPU time 265 seconds
Started Jul 01 11:14:49 AM PDT 24
Finished Jul 01 11:19:16 AM PDT 24
Peak memory 210484 kb
Host smart-08767a4f-0646-4576-af8f-2d0ffe33091d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143807585 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4143807585
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1657103383
Short name T22
Test name
Test status
Simulation time 75014093947 ps
CPU time 138.52 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:17:25 AM PDT 24
Peak memory 213068 kb
Host smart-4e760448-e01f-4149-9afd-a4e73126b857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657103383 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1657103383
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2410781166
Short name T135
Test name
Test status
Simulation time 359703160736 ps
CPU time 248.76 seconds
Started Jul 01 11:14:06 AM PDT 24
Finished Jul 01 11:18:15 AM PDT 24
Peak memory 201852 kb
Host smart-16951bdb-300e-4d49-8251-ce8ec052030a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410781166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2410781166
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.816033470
Short name T817
Test name
Test status
Simulation time 4119540139 ps
CPU time 5.91 seconds
Started Jul 01 10:39:44 AM PDT 24
Finished Jul 01 10:39:54 AM PDT 24
Peak memory 201724 kb
Host smart-1cc2d139-a918-4d35-9d6a-d5e351922cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816033470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.816033470
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1615595752
Short name T279
Test name
Test status
Simulation time 537353442096 ps
CPU time 1181.85 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:34:28 AM PDT 24
Peak memory 201888 kb
Host smart-74bef0ff-1627-49d4-b956-e08af55bfdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615595752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1615595752
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.66203865
Short name T246
Test name
Test status
Simulation time 330338905339 ps
CPU time 163.31 seconds
Started Jul 01 11:17:30 AM PDT 24
Finished Jul 01 11:20:59 AM PDT 24
Peak memory 201804 kb
Host smart-0b828478-0d82-49ac-913b-b820ad4ea0ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66203865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gatin
g.66203865
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3843161683
Short name T12
Test name
Test status
Simulation time 331585118470 ps
CPU time 606.09 seconds
Started Jul 01 11:16:25 AM PDT 24
Finished Jul 01 11:28:06 AM PDT 24
Peak memory 201880 kb
Host smart-c94e3d0d-c899-40d3-a23d-cf8148866053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843161683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3843161683
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3369296642
Short name T38
Test name
Test status
Simulation time 210608756391 ps
CPU time 172.65 seconds
Started Jul 01 11:17:44 AM PDT 24
Finished Jul 01 11:21:11 AM PDT 24
Peak memory 210404 kb
Host smart-09030ce0-ebbe-4429-89a3-c0da577fb6a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369296642 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3369296642
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.190313552
Short name T266
Test name
Test status
Simulation time 536013192022 ps
CPU time 1171.71 seconds
Started Jul 01 11:15:05 AM PDT 24
Finished Jul 01 11:34:38 AM PDT 24
Peak memory 201888 kb
Host smart-630d00eb-f6ff-4274-864c-595d433fd053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190313552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.190313552
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3874164017
Short name T276
Test name
Test status
Simulation time 227662870553 ps
CPU time 101.32 seconds
Started Jul 01 11:17:11 AM PDT 24
Finished Jul 01 11:19:54 AM PDT 24
Peak memory 201756 kb
Host smart-167a0054-fbbf-4d43-a594-ad9c5c24309f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874164017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3874164017
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.186891449
Short name T19
Test name
Test status
Simulation time 165390887567 ps
CPU time 106.61 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:15:48 AM PDT 24
Peak memory 210184 kb
Host smart-9404c5bc-fb14-4d0e-b4fe-86d9925fd7e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186891449 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.186891449
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3427813402
Short name T199
Test name
Test status
Simulation time 335120149997 ps
CPU time 139.39 seconds
Started Jul 01 11:14:35 AM PDT 24
Finished Jul 01 11:16:55 AM PDT 24
Peak memory 201840 kb
Host smart-39f4cdfd-f32f-4ebe-946b-9649063e18df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427813402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3427813402
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1042080117
Short name T284
Test name
Test status
Simulation time 493637083997 ps
CPU time 511.8 seconds
Started Jul 01 11:15:38 AM PDT 24
Finished Jul 01 11:24:40 AM PDT 24
Peak memory 201836 kb
Host smart-b16c999e-de77-4e75-872f-9ead0ac72377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042080117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1042080117
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2402369965
Short name T273
Test name
Test status
Simulation time 610129515818 ps
CPU time 1436.6 seconds
Started Jul 01 11:15:33 AM PDT 24
Finished Jul 01 11:39:49 AM PDT 24
Peak memory 201884 kb
Host smart-fcde465c-1e54-4fd7-989f-5d9096857e9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402369965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2402369965
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.680161283
Short name T299
Test name
Test status
Simulation time 164000263974 ps
CPU time 90.31 seconds
Started Jul 01 11:14:32 AM PDT 24
Finished Jul 01 11:16:03 AM PDT 24
Peak memory 201876 kb
Host smart-a281489d-caf2-4aef-95c0-560dbb049904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680161283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.680161283
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4025178437
Short name T15
Test name
Test status
Simulation time 91167628582 ps
CPU time 102.84 seconds
Started Jul 01 11:15:26 AM PDT 24
Finished Jul 01 11:17:15 AM PDT 24
Peak memory 210096 kb
Host smart-2e04686f-8b9d-45fc-8eae-a992fedf4f4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025178437 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4025178437
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3631102995
Short name T262
Test name
Test status
Simulation time 505490741669 ps
CPU time 1125.13 seconds
Started Jul 01 11:16:39 AM PDT 24
Finished Jul 01 11:36:42 AM PDT 24
Peak memory 201884 kb
Host smart-c8ad2844-fc4e-4102-9f34-1c41f26befeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631102995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3631102995
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1714956148
Short name T144
Test name
Test status
Simulation time 290282022974 ps
CPU time 681.28 seconds
Started Jul 01 11:15:53 AM PDT 24
Finished Jul 01 11:28:16 AM PDT 24
Peak memory 212636 kb
Host smart-975cc257-1ee0-46c2-8a3e-a94dc810fd1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714956148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1714956148
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.4025305791
Short name T293
Test name
Test status
Simulation time 568657830151 ps
CPU time 1268.8 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:35:34 AM PDT 24
Peak memory 201844 kb
Host smart-90be337a-71f6-4590-bf0e-b96fc45d16a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025305791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.4025305791
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2264611012
Short name T98
Test name
Test status
Simulation time 489932790189 ps
CPU time 172.25 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:17:39 AM PDT 24
Peak memory 210212 kb
Host smart-c96cca96-85b3-47d6-b09b-ac487a235cec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264611012 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2264611012
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1453403095
Short name T306
Test name
Test status
Simulation time 175712557544 ps
CPU time 188.84 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:17:34 AM PDT 24
Peak memory 201916 kb
Host smart-815099d2-6b28-40f9-ac0f-32e1411f788d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453403095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1453403095
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3839747652
Short name T309
Test name
Test status
Simulation time 344827296081 ps
CPU time 722.53 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:27:57 AM PDT 24
Peak memory 201732 kb
Host smart-41bce915-76cc-4a16-9509-77bcf39ed5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839747652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3839747652
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3538366781
Short name T244
Test name
Test status
Simulation time 489968939493 ps
CPU time 584.92 seconds
Started Jul 01 11:15:30 AM PDT 24
Finished Jul 01 11:25:25 AM PDT 24
Peak memory 201912 kb
Host smart-e7ec42bf-db55-44a5-8ddc-14403d990efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538366781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3538366781
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1015440253
Short name T260
Test name
Test status
Simulation time 375096799352 ps
CPU time 261.78 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:19:08 AM PDT 24
Peak memory 201932 kb
Host smart-08995480-dd08-4616-bda3-392c500f40c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015440253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1015440253
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1141148131
Short name T241
Test name
Test status
Simulation time 350901956675 ps
CPU time 772.09 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:27:44 AM PDT 24
Peak memory 202076 kb
Host smart-c7bd641f-054f-4050-a117-f75702cfc1e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141148131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1141148131
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.495967001
Short name T200
Test name
Test status
Simulation time 130583901553 ps
CPU time 463.89 seconds
Started Jul 01 11:15:40 AM PDT 24
Finished Jul 01 11:24:02 AM PDT 24
Peak memory 202112 kb
Host smart-aa2d8b96-0f4e-4ddd-ad45-5dc825734ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495967001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.495967001
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1057305009
Short name T291
Test name
Test status
Simulation time 494628889324 ps
CPU time 568.99 seconds
Started Jul 01 11:15:42 AM PDT 24
Finished Jul 01 11:25:52 AM PDT 24
Peak memory 201824 kb
Host smart-783f316d-0c39-446c-b068-47675f4ea27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057305009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1057305009
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2399915723
Short name T168
Test name
Test status
Simulation time 492058751909 ps
CPU time 79.88 seconds
Started Jul 01 11:17:55 AM PDT 24
Finished Jul 01 11:19:39 AM PDT 24
Peak memory 201888 kb
Host smart-e125f3e4-8be5-4ced-9751-5045aa0b22bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399915723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2399915723
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1985624229
Short name T145
Test name
Test status
Simulation time 158763723664 ps
CPU time 377.03 seconds
Started Jul 01 11:14:36 AM PDT 24
Finished Jul 01 11:20:53 AM PDT 24
Peak memory 201864 kb
Host smart-daff888d-4c5f-4be8-8e52-a5cc2b549fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985624229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1985624229
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2903721183
Short name T52
Test name
Test status
Simulation time 26657468163 ps
CPU time 26.08 seconds
Started Jul 01 10:38:53 AM PDT 24
Finished Jul 01 10:39:20 AM PDT 24
Peak memory 201728 kb
Host smart-70601ef7-3857-4bf7-80f1-fde59cdb4be9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903721183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2903721183
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2156620550
Short name T282
Test name
Test status
Simulation time 162033122807 ps
CPU time 373.2 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:20:56 AM PDT 24
Peak memory 201876 kb
Host smart-eee8a121-b07f-465d-9e84-d4e149cf9ba9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156620550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2156620550
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2484792440
Short name T208
Test name
Test status
Simulation time 82917952842 ps
CPU time 280.13 seconds
Started Jul 01 11:16:37 AM PDT 24
Finished Jul 01 11:22:48 AM PDT 24
Peak memory 202188 kb
Host smart-ca770487-18c3-4743-8ca2-f8a974b3102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484792440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2484792440
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.733324587
Short name T182
Test name
Test status
Simulation time 496299619975 ps
CPU time 184.34 seconds
Started Jul 01 11:16:50 AM PDT 24
Finished Jul 01 11:21:17 AM PDT 24
Peak memory 201760 kb
Host smart-8b566ae6-64f1-465b-9f3a-d994b1372c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733324587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.733324587
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.186946396
Short name T57
Test name
Test status
Simulation time 4624686282 ps
CPU time 12.7 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 201720 kb
Host smart-fe632569-a08d-44f9-9506-eb70b91d8dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186946396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.186946396
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2338320366
Short name T209
Test name
Test status
Simulation time 125584831592 ps
CPU time 671.17 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:25:43 AM PDT 24
Peak memory 202152 kb
Host smart-02e2fda5-9124-4931-b2a4-7f413d22db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338320366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2338320366
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3022909728
Short name T292
Test name
Test status
Simulation time 360704821882 ps
CPU time 107.36 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:16:28 AM PDT 24
Peak memory 201864 kb
Host smart-4fda63fc-61b4-4125-b5c7-50ebb0054e1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022909728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3022909728
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2939397941
Short name T286
Test name
Test status
Simulation time 490146630353 ps
CPU time 333.1 seconds
Started Jul 01 11:15:31 AM PDT 24
Finished Jul 01 11:21:16 AM PDT 24
Peak memory 201960 kb
Host smart-e2875924-ef70-4d84-b16f-ed4d435efcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939397941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2939397941
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.966611528
Short name T34
Test name
Test status
Simulation time 408613028362 ps
CPU time 214.81 seconds
Started Jul 01 11:14:27 AM PDT 24
Finished Jul 01 11:18:02 AM PDT 24
Peak memory 201804 kb
Host smart-5b846948-2156-4119-a888-7cced49c3311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966611528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.966611528
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.714285453
Short name T96
Test name
Test status
Simulation time 757230025323 ps
CPU time 254.96 seconds
Started Jul 01 11:17:58 AM PDT 24
Finished Jul 01 11:22:35 AM PDT 24
Peak memory 211544 kb
Host smart-d611ebc0-a0d4-413f-9a00-10e45c3bb8d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714285453 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.714285453
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2957786331
Short name T214
Test name
Test status
Simulation time 490933739135 ps
CPU time 411.79 seconds
Started Jul 01 11:18:04 AM PDT 24
Finished Jul 01 11:25:13 AM PDT 24
Peak memory 201792 kb
Host smart-04921f08-939a-4cee-abbb-28d88e125c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957786331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2957786331
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1953559823
Short name T74
Test name
Test status
Simulation time 8117763129 ps
CPU time 7.08 seconds
Started Jul 01 10:40:30 AM PDT 24
Finished Jul 01 10:40:39 AM PDT 24
Peak memory 201636 kb
Host smart-a1a547fb-6348-459d-a58e-3da38e7e5e86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953559823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1953559823
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3073343204
Short name T518
Test name
Test status
Simulation time 94264539584 ps
CPU time 317.95 seconds
Started Jul 01 11:13:58 AM PDT 24
Finished Jul 01 11:19:17 AM PDT 24
Peak memory 202164 kb
Host smart-e1f7c976-e36a-416b-a5b4-36d8394f768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073343204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3073343204
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.906079341
Short name T207
Test name
Test status
Simulation time 105993540247 ps
CPU time 372.81 seconds
Started Jul 01 11:14:26 AM PDT 24
Finished Jul 01 11:20:40 AM PDT 24
Peak memory 202248 kb
Host smart-66b07739-4ac8-4716-a09d-d31340f14a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906079341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.906079341
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3306759569
Short name T303
Test name
Test status
Simulation time 326995342021 ps
CPU time 74.5 seconds
Started Jul 01 11:14:47 AM PDT 24
Finished Jul 01 11:16:03 AM PDT 24
Peak memory 201772 kb
Host smart-f5124e28-44f6-4979-8944-89d5f63bbb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306759569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3306759569
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.4271856025
Short name T151
Test name
Test status
Simulation time 487224794311 ps
CPU time 301.22 seconds
Started Jul 01 11:14:37 AM PDT 24
Finished Jul 01 11:19:39 AM PDT 24
Peak memory 201932 kb
Host smart-f92f89ad-cf6a-4d0b-9048-8657d8b9246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271856025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4271856025
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.833739847
Short name T254
Test name
Test status
Simulation time 189799540968 ps
CPU time 70.98 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:15:55 AM PDT 24
Peak memory 201840 kb
Host smart-bcc8a8ff-297b-4a18-9dae-cbb7a44d45af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833739847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.833739847
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1110880368
Short name T105
Test name
Test status
Simulation time 343044766671 ps
CPU time 801.62 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:28:13 AM PDT 24
Peak memory 201888 kb
Host smart-00efd017-ddb8-41ee-a297-7a9858aee0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110880368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1110880368
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2157658765
Short name T271
Test name
Test status
Simulation time 180529893301 ps
CPU time 318.42 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:20:14 AM PDT 24
Peak memory 201784 kb
Host smart-369e4574-bd89-42e6-a52d-5438094f5217
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157658765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2157658765
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.4061030250
Short name T141
Test name
Test status
Simulation time 535691079867 ps
CPU time 147.72 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:17:20 AM PDT 24
Peak memory 201924 kb
Host smart-4946a44a-5f05-4ca6-902e-0c27756df870
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061030250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.4061030250
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1483671231
Short name T335
Test name
Test status
Simulation time 117537195191 ps
CPU time 584.84 seconds
Started Jul 01 11:15:05 AM PDT 24
Finished Jul 01 11:24:51 AM PDT 24
Peak memory 202264 kb
Host smart-b94969e0-caed-4415-a6c1-8f6de425792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483671231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1483671231
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.4228895065
Short name T324
Test name
Test status
Simulation time 353654529737 ps
CPU time 91.39 seconds
Started Jul 01 11:15:28 AM PDT 24
Finished Jul 01 11:17:08 AM PDT 24
Peak memory 201876 kb
Host smart-7c62b285-eb2c-439d-8781-c1892e1cfa1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228895065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.4228895065
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1685054727
Short name T274
Test name
Test status
Simulation time 170574948751 ps
CPU time 180.49 seconds
Started Jul 01 11:14:27 AM PDT 24
Finished Jul 01 11:17:28 AM PDT 24
Peak memory 201872 kb
Host smart-0c3c4f12-e055-44dd-8aad-15c4afef293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685054727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1685054727
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4028580643
Short name T340
Test name
Test status
Simulation time 93966140750 ps
CPU time 312.79 seconds
Started Jul 01 11:15:45 AM PDT 24
Finished Jul 01 11:21:47 AM PDT 24
Peak memory 202180 kb
Host smart-468a4ca6-ca46-48ee-872a-62f662de6b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028580643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4028580643
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.854512473
Short name T4
Test name
Test status
Simulation time 170117758019 ps
CPU time 110.9 seconds
Started Jul 01 11:18:26 AM PDT 24
Finished Jul 01 11:20:18 AM PDT 24
Peak memory 201940 kb
Host smart-f25fe660-bbec-4cc5-b70e-5633e3c9578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854512473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.854512473
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3581818916
Short name T264
Test name
Test status
Simulation time 354844860173 ps
CPU time 1312.97 seconds
Started Jul 01 11:17:21 AM PDT 24
Finished Jul 01 11:40:08 AM PDT 24
Peak memory 202164 kb
Host smart-84881234-78a3-4a84-9123-e895c3a2f93f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581818916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3581818916
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.300444877
Short name T210
Test name
Test status
Simulation time 143176267019 ps
CPU time 538.26 seconds
Started Jul 01 11:17:43 AM PDT 24
Finished Jul 01 11:27:16 AM PDT 24
Peak memory 202248 kb
Host smart-9fadb847-9533-41dd-bd2a-023ab0976ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300444877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.300444877
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3657241089
Short name T267
Test name
Test status
Simulation time 491342239321 ps
CPU time 329.93 seconds
Started Jul 01 11:14:25 AM PDT 24
Finished Jul 01 11:19:56 AM PDT 24
Peak memory 201804 kb
Host smart-c3fa287e-59f1-4b9f-9f06-9c8b5df5e4c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657241089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3657241089
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2290263499
Short name T108
Test name
Test status
Simulation time 1056968826 ps
CPU time 5.58 seconds
Started Jul 01 10:39:10 AM PDT 24
Finished Jul 01 10:39:17 AM PDT 24
Peak memory 201628 kb
Host smart-c1697bc8-6770-467c-b440-069a76120a26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290263499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2290263499
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1820179315
Short name T889
Test name
Test status
Simulation time 26380328278 ps
CPU time 103.17 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:40:58 AM PDT 24
Peak memory 201784 kb
Host smart-5e355dda-f163-4790-a32a-f53d696744a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820179315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1820179315
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.21963976
Short name T894
Test name
Test status
Simulation time 1131132636 ps
CPU time 1.39 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 201412 kb
Host smart-c2cab356-b14d-4325-b0af-6d50d3bcc796
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21963976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_res
et.21963976
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3929779467
Short name T852
Test name
Test status
Simulation time 366847727 ps
CPU time 1.25 seconds
Started Jul 01 10:38:56 AM PDT 24
Finished Jul 01 10:38:58 AM PDT 24
Peak memory 201460 kb
Host smart-77b41c34-0452-4bd7-80df-86eef25cd7db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929779467 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3929779467
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3366235481
Short name T115
Test name
Test status
Simulation time 313666796 ps
CPU time 1.43 seconds
Started Jul 01 10:39:05 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 201404 kb
Host smart-4566db70-f18b-4384-9fa3-c40177e9d4a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366235481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3366235481
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4022957849
Short name T850
Test name
Test status
Simulation time 518632616 ps
CPU time 0.75 seconds
Started Jul 01 10:39:12 AM PDT 24
Finished Jul 01 10:39:15 AM PDT 24
Peak memory 201348 kb
Host smart-fec81f12-27cc-4a3d-9f92-e57ec40f7fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022957849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4022957849
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3010132691
Short name T862
Test name
Test status
Simulation time 2491353258 ps
CPU time 2.69 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:07 AM PDT 24
Peak memory 201556 kb
Host smart-04119e12-feb6-4a93-bd95-9176a941aa49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010132691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3010132691
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3286651824
Short name T916
Test name
Test status
Simulation time 544934059 ps
CPU time 2.27 seconds
Started Jul 01 10:39:16 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 201656 kb
Host smart-6daa7e4f-e027-43a5-a861-9535c91771d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286651824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3286651824
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.840790970
Short name T818
Test name
Test status
Simulation time 8249197322 ps
CPU time 6.87 seconds
Started Jul 01 10:39:08 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 201720 kb
Host smart-57f13b07-7799-4403-85e7-36e7eb28e006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840790970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.840790970
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3334709898
Short name T887
Test name
Test status
Simulation time 1562537143 ps
CPU time 3 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 201628 kb
Host smart-481b5983-36e9-4feb-be93-08889c2c8354
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334709898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3334709898
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.553286177
Short name T904
Test name
Test status
Simulation time 672527043 ps
CPU time 1.4 seconds
Started Jul 01 10:39:15 AM PDT 24
Finished Jul 01 10:39:17 AM PDT 24
Peak memory 201380 kb
Host smart-3f28fb7d-3820-4eff-b6ec-308a7949e52e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553286177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.553286177
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.631844268
Short name T808
Test name
Test status
Simulation time 385844412 ps
CPU time 1.04 seconds
Started Jul 01 10:39:08 AM PDT 24
Finished Jul 01 10:39:12 AM PDT 24
Peak memory 201448 kb
Host smart-48cd1ca5-864d-4afa-b63b-ac9841e3d028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631844268 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.631844268
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1378150951
Short name T112
Test name
Test status
Simulation time 378599391 ps
CPU time 1.7 seconds
Started Jul 01 10:40:21 AM PDT 24
Finished Jul 01 10:40:26 AM PDT 24
Peak memory 201288 kb
Host smart-cad115cf-20cc-4fcc-b0ce-9257348603c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378150951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1378150951
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1998871760
Short name T884
Test name
Test status
Simulation time 535271925 ps
CPU time 0.97 seconds
Started Jul 01 10:39:01 AM PDT 24
Finished Jul 01 10:39:03 AM PDT 24
Peak memory 201360 kb
Host smart-505629c0-9a5e-4517-a54b-9fde38edb507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998871760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1998871760
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3801941509
Short name T125
Test name
Test status
Simulation time 4846844483 ps
CPU time 11.11 seconds
Started Jul 01 10:39:05 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 201720 kb
Host smart-f8ecee1a-3780-403e-83db-91bc7a5b908c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801941509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3801941509
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3391780640
Short name T822
Test name
Test status
Simulation time 405793531 ps
CPU time 2.09 seconds
Started Jul 01 10:39:00 AM PDT 24
Finished Jul 01 10:39:03 AM PDT 24
Peak memory 201680 kb
Host smart-1067937d-f075-4bdb-b11f-f53615f67e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391780640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3391780640
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1695229863
Short name T837
Test name
Test status
Simulation time 4176000362 ps
CPU time 11.15 seconds
Started Jul 01 10:39:25 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 201760 kb
Host smart-7c4aaf4a-f29d-4a64-8d51-833d898d20af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695229863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1695229863
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3714161013
Short name T912
Test name
Test status
Simulation time 756312661 ps
CPU time 1.21 seconds
Started Jul 01 10:39:24 AM PDT 24
Finished Jul 01 10:39:26 AM PDT 24
Peak memory 201768 kb
Host smart-63d1c468-aa4c-4b8d-8ed6-b2cea9f95249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714161013 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3714161013
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.596085852
Short name T897
Test name
Test status
Simulation time 365186267 ps
CPU time 1.6 seconds
Started Jul 01 10:40:33 AM PDT 24
Finished Jul 01 10:40:36 AM PDT 24
Peak memory 201324 kb
Host smart-a835cdcd-62b2-422a-8155-0cffcfeb98b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596085852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.596085852
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3278240196
Short name T907
Test name
Test status
Simulation time 465068560 ps
CPU time 1.59 seconds
Started Jul 01 10:39:16 AM PDT 24
Finished Jul 01 10:39:19 AM PDT 24
Peak memory 201344 kb
Host smart-bc0e05b0-a153-4920-b7b8-5c6509fa06de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278240196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3278240196
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2218038715
Short name T847
Test name
Test status
Simulation time 4464254765 ps
CPU time 9.93 seconds
Started Jul 01 10:39:21 AM PDT 24
Finished Jul 01 10:39:32 AM PDT 24
Peak memory 201740 kb
Host smart-a756998e-5652-47da-aee9-dc8c9a08bd08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218038715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2218038715
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.670194947
Short name T918
Test name
Test status
Simulation time 636655975 ps
CPU time 1.92 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:36 AM PDT 24
Peak memory 210912 kb
Host smart-0124ccfb-56f2-431f-a494-b1eb9a6ffa23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670194947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.670194947
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3560388550
Short name T919
Test name
Test status
Simulation time 427894339 ps
CPU time 1.93 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 201464 kb
Host smart-ac587166-1cf0-4331-bf3e-01a7801ed082
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560388550 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3560388550
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1577069993
Short name T903
Test name
Test status
Simulation time 380935173 ps
CPU time 1.1 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 201328 kb
Host smart-fc12fb22-717b-4c13-ba3b-a6f59cda9a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577069993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1577069993
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2324289458
Short name T841
Test name
Test status
Simulation time 544352320 ps
CPU time 0.79 seconds
Started Jul 01 10:39:25 AM PDT 24
Finished Jul 01 10:39:27 AM PDT 24
Peak memory 201360 kb
Host smart-78fa8518-920f-4fbb-a265-3a240b630dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324289458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2324289458
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1853032156
Short name T121
Test name
Test status
Simulation time 2491287213 ps
CPU time 6.11 seconds
Started Jul 01 10:40:03 AM PDT 24
Finished Jul 01 10:40:10 AM PDT 24
Peak memory 200668 kb
Host smart-6878dd5e-8d67-4841-a851-b1bf125d5169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853032156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1853032156
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.489506497
Short name T71
Test name
Test status
Simulation time 928772199 ps
CPU time 2.66 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 209876 kb
Host smart-452340f0-5b12-4b4e-bba8-f44f84730f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489506497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.489506497
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.580508108
Short name T913
Test name
Test status
Simulation time 4334868329 ps
CPU time 6.7 seconds
Started Jul 01 10:39:28 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 201740 kb
Host smart-48469a7a-8e8a-4816-b5fc-917ac1201c12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580508108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.580508108
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.782973073
Short name T58
Test name
Test status
Simulation time 552917784 ps
CPU time 1.09 seconds
Started Jul 01 10:38:58 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 201348 kb
Host smart-205c3122-7dc4-4fdd-845b-cc5f7597736e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782973073 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.782973073
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1519711411
Short name T848
Test name
Test status
Simulation time 482427903 ps
CPU time 1.81 seconds
Started Jul 01 10:40:32 AM PDT 24
Finished Jul 01 10:40:35 AM PDT 24
Peak memory 201328 kb
Host smart-ac6545d1-2233-47f7-b7c4-2283811f3dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519711411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1519711411
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3084522310
Short name T814
Test name
Test status
Simulation time 452156641 ps
CPU time 0.93 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 201332 kb
Host smart-aedc1f49-fbc9-4a3d-8a36-d248c0da0317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084522310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3084522310
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1089658619
Short name T51
Test name
Test status
Simulation time 2698652487 ps
CPU time 2.97 seconds
Started Jul 01 10:39:01 AM PDT 24
Finished Jul 01 10:39:04 AM PDT 24
Peak memory 201548 kb
Host smart-9cdcd527-c421-4626-8b2a-8a5b882a9eab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089658619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1089658619
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1498064162
Short name T861
Test name
Test status
Simulation time 1394725479 ps
CPU time 2.38 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 217988 kb
Host smart-7c384600-876d-4411-8b5c-d3f8462ef4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498064162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1498064162
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.747825469
Short name T55
Test name
Test status
Simulation time 9028731931 ps
CPU time 23.03 seconds
Started Jul 01 10:39:26 AM PDT 24
Finished Jul 01 10:39:50 AM PDT 24
Peak memory 201728 kb
Host smart-6dd6943f-ebd1-4b8d-a237-e502f7c87a12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747825469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.747825469
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2483384332
Short name T87
Test name
Test status
Simulation time 523013200 ps
CPU time 2.16 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 201472 kb
Host smart-9c7d16ed-5431-48f6-8a40-41e721cce447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483384332 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2483384332
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1402785930
Short name T874
Test name
Test status
Simulation time 448387658 ps
CPU time 1.32 seconds
Started Jul 01 10:39:18 AM PDT 24
Finished Jul 01 10:39:20 AM PDT 24
Peak memory 201432 kb
Host smart-b34f1cbe-59c7-4e25-97c8-d4aa1f072c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402785930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1402785930
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.790407579
Short name T799
Test name
Test status
Simulation time 370632494 ps
CPU time 1.47 seconds
Started Jul 01 10:39:29 AM PDT 24
Finished Jul 01 10:39:32 AM PDT 24
Peak memory 201344 kb
Host smart-450d15cb-d26a-4ed7-a2d3-84976e376f6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790407579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.790407579
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.209629653
Short name T124
Test name
Test status
Simulation time 2072917811 ps
CPU time 3.49 seconds
Started Jul 01 10:40:05 AM PDT 24
Finished Jul 01 10:40:10 AM PDT 24
Peak memory 201376 kb
Host smart-e2de09e0-ecb1-4c0d-9002-e4a52947d6bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209629653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.209629653
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3076108861
Short name T910
Test name
Test status
Simulation time 414714650 ps
CPU time 3.08 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 217580 kb
Host smart-7fe7554e-b114-4c15-a5d9-3299189c3c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076108861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3076108861
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3091879406
Short name T853
Test name
Test status
Simulation time 508173984 ps
CPU time 1.56 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 201472 kb
Host smart-4378ea6d-0c08-4fc7-89b4-398ed28fc93d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091879406 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3091879406
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1175472647
Short name T113
Test name
Test status
Simulation time 302314989 ps
CPU time 1.37 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 201420 kb
Host smart-ae1d6b04-b3e3-4895-a1ec-22f1fbdf29e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175472647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1175472647
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1629397202
Short name T857
Test name
Test status
Simulation time 326880186 ps
CPU time 1.4 seconds
Started Jul 01 10:39:12 AM PDT 24
Finished Jul 01 10:39:15 AM PDT 24
Peak memory 201344 kb
Host smart-06cb1969-d38e-425b-b457-73c0649b90f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629397202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1629397202
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2574416349
Short name T816
Test name
Test status
Simulation time 2906753740 ps
CPU time 11.49 seconds
Started Jul 01 10:39:08 AM PDT 24
Finished Jul 01 10:39:23 AM PDT 24
Peak memory 201536 kb
Host smart-5491d989-34f0-4b20-a88f-a232acac8dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574416349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2574416349
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2612806443
Short name T59
Test name
Test status
Simulation time 721435447 ps
CPU time 2.28 seconds
Started Jul 01 10:39:28 AM PDT 24
Finished Jul 01 10:39:32 AM PDT 24
Peak memory 210856 kb
Host smart-2e85792b-baa0-455a-99de-54400eaceb03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612806443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2612806443
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2696274351
Short name T805
Test name
Test status
Simulation time 360894367 ps
CPU time 1.22 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 201432 kb
Host smart-f91a6026-9e3c-4f1b-967e-a4522fdc7d0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696274351 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2696274351
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.872652571
Short name T902
Test name
Test status
Simulation time 590841451 ps
CPU time 1.01 seconds
Started Jul 01 10:39:16 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 201420 kb
Host smart-466712bd-8a28-4763-b42e-4a9e8b7f1d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872652571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.872652571
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1794398229
Short name T866
Test name
Test status
Simulation time 291548890 ps
CPU time 1.37 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 201316 kb
Host smart-179f8fc3-38d2-41c0-8fc5-a028f1dc4279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794398229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1794398229
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.336789550
Short name T50
Test name
Test status
Simulation time 2159161654 ps
CPU time 4.62 seconds
Started Jul 01 10:39:28 AM PDT 24
Finished Jul 01 10:39:33 AM PDT 24
Peak memory 201560 kb
Host smart-5003ee74-153f-45d8-8f44-4e1e899c8e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336789550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.336789550
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.489917892
Short name T856
Test name
Test status
Simulation time 593832072 ps
CPU time 3.69 seconds
Started Jul 01 10:39:10 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 201708 kb
Host smart-9ffc2fd7-f491-4037-81ce-7b2e3b14c249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489917892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.489917892
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2893433526
Short name T867
Test name
Test status
Simulation time 4086825873 ps
CPU time 8.5 seconds
Started Jul 01 10:39:56 AM PDT 24
Finished Jul 01 10:40:05 AM PDT 24
Peak memory 201748 kb
Host smart-ee813e5c-3aa0-4014-885b-2ed8883d3575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893433526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2893433526
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2520366897
Short name T885
Test name
Test status
Simulation time 623412685 ps
CPU time 1.36 seconds
Started Jul 01 10:39:19 AM PDT 24
Finished Jul 01 10:39:22 AM PDT 24
Peak memory 201496 kb
Host smart-51c1685e-ccde-431a-ae8d-929aa318b437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520366897 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2520366897
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.325114960
Short name T109
Test name
Test status
Simulation time 632293238 ps
CPU time 1.05 seconds
Started Jul 01 10:39:20 AM PDT 24
Finished Jul 01 10:39:22 AM PDT 24
Peak memory 201416 kb
Host smart-6682554c-74b5-4254-bd7b-dfb924adc868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325114960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.325114960
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2603203432
Short name T909
Test name
Test status
Simulation time 399804774 ps
CPU time 0.87 seconds
Started Jul 01 10:39:19 AM PDT 24
Finished Jul 01 10:39:22 AM PDT 24
Peak memory 201348 kb
Host smart-cf3c1c3c-2302-408a-a6d5-d9e8f3267d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603203432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2603203432
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.815643499
Short name T896
Test name
Test status
Simulation time 5097986694 ps
CPU time 20.44 seconds
Started Jul 01 10:40:01 AM PDT 24
Finished Jul 01 10:40:22 AM PDT 24
Peak memory 201760 kb
Host smart-4e8379ac-137e-4e85-bb97-ccbb57ceadd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815643499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.815643499
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3930457701
Short name T802
Test name
Test status
Simulation time 648281817 ps
CPU time 2.47 seconds
Started Jul 01 10:39:25 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 218008 kb
Host smart-0e79d04e-9e24-4a9d-8019-2976a98de78e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930457701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3930457701
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1248032723
Short name T872
Test name
Test status
Simulation time 4510675973 ps
CPU time 4.5 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:33 AM PDT 24
Peak memory 201796 kb
Host smart-26cd7512-d910-4651-bcbe-9d0f55cc897c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248032723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1248032723
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1464317335
Short name T900
Test name
Test status
Simulation time 632752367 ps
CPU time 1.19 seconds
Started Jul 01 10:39:39 AM PDT 24
Finished Jul 01 10:39:45 AM PDT 24
Peak memory 209852 kb
Host smart-f984f5dd-e6ae-4511-ac64-32b56db95950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464317335 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1464317335
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.588241351
Short name T123
Test name
Test status
Simulation time 586134489 ps
CPU time 1.58 seconds
Started Jul 01 10:39:21 AM PDT 24
Finished Jul 01 10:39:24 AM PDT 24
Peak memory 201396 kb
Host smart-19115e61-b868-49ed-ab62-8182e81ebd80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588241351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.588241351
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3887414023
Short name T890
Test name
Test status
Simulation time 480499900 ps
CPU time 0.86 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 201332 kb
Host smart-15502a93-e8db-4d04-bd95-470e9313a0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887414023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3887414023
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3901211466
Short name T883
Test name
Test status
Simulation time 4823797947 ps
CPU time 9.13 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 201744 kb
Host smart-a9ff4a48-6fdf-49fa-b720-7873510d83b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901211466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3901211466
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4208862459
Short name T806
Test name
Test status
Simulation time 556845586 ps
CPU time 1.93 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:30 AM PDT 24
Peak memory 201984 kb
Host smart-7bbb9b4b-dec2-440e-a99c-340ba4175743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208862459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.4208862459
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3271109958
Short name T854
Test name
Test status
Simulation time 7839284690 ps
CPU time 19.56 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:53 AM PDT 24
Peak memory 201752 kb
Host smart-0f9dd8dc-9c1f-4885-a66d-b75a26babd00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271109958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3271109958
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2119078646
Short name T830
Test name
Test status
Simulation time 573058311 ps
CPU time 1.74 seconds
Started Jul 01 10:39:33 AM PDT 24
Finished Jul 01 10:39:37 AM PDT 24
Peak memory 201452 kb
Host smart-fb30a3b7-3aa5-4eb2-808f-3c85f44d2dce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119078646 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2119078646
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4195992542
Short name T117
Test name
Test status
Simulation time 434912215 ps
CPU time 1.81 seconds
Started Jul 01 10:39:37 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 201436 kb
Host smart-f075166c-bc39-40d9-a957-c683e72d05ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195992542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4195992542
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.853642106
Short name T825
Test name
Test status
Simulation time 488270491 ps
CPU time 1.73 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 201492 kb
Host smart-45b541c5-606a-4fc0-bd3c-23c71d019283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853642106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.853642106
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3823621630
Short name T886
Test name
Test status
Simulation time 2660159445 ps
CPU time 10.63 seconds
Started Jul 01 10:39:24 AM PDT 24
Finished Jul 01 10:39:36 AM PDT 24
Peak memory 201560 kb
Host smart-0df7421f-ca5a-47e3-b600-12e648a2bdb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823621630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3823621630
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1174297229
Short name T69
Test name
Test status
Simulation time 432781860 ps
CPU time 2.03 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 201464 kb
Host smart-cc1a306b-ad86-4994-abc2-2cd2f54fef1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174297229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1174297229
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.124302744
Short name T846
Test name
Test status
Simulation time 5009053963 ps
CPU time 3.45 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 201764 kb
Host smart-2b5a850b-ec9e-4411-9ce1-9e10f1371ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124302744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.124302744
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1162505290
Short name T829
Test name
Test status
Simulation time 554560480 ps
CPU time 1.99 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 201456 kb
Host smart-ba938b03-2ae1-486a-bfff-554e452151ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162505290 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1162505290
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2850635979
Short name T116
Test name
Test status
Simulation time 401514198 ps
CPU time 1.01 seconds
Started Jul 01 10:39:15 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 201436 kb
Host smart-2bebcccc-7625-4c92-bcf6-bf59e3e0e5c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850635979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2850635979
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.588400611
Short name T881
Test name
Test status
Simulation time 533943846 ps
CPU time 0.94 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 201316 kb
Host smart-de01ffa7-96b8-4525-8625-f97fee67135b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588400611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.588400611
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2500156241
Short name T877
Test name
Test status
Simulation time 4703133377 ps
CPU time 4.77 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:40:10 AM PDT 24
Peak memory 201784 kb
Host smart-2f82d10c-1444-4cdd-9aee-2fc889d96c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500156241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2500156241
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.126617188
Short name T864
Test name
Test status
Simulation time 4727365454 ps
CPU time 4.46 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 201744 kb
Host smart-3ba3823c-3c17-47aa-82c5-f554535e70dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126617188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.126617188
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.212249701
Short name T863
Test name
Test status
Simulation time 723641308 ps
CPU time 3.04 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 201624 kb
Host smart-c9521c3f-dc28-4017-ade3-0be0dc038eb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212249701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.212249701
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3265404592
Short name T823
Test name
Test status
Simulation time 52342508012 ps
CPU time 71.31 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:40:17 AM PDT 24
Peak memory 201756 kb
Host smart-7044e647-4aa2-42ec-8971-2935340541b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265404592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3265404592
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3740048342
Short name T815
Test name
Test status
Simulation time 1410478692 ps
CPU time 1.58 seconds
Started Jul 01 10:39:22 AM PDT 24
Finished Jul 01 10:39:24 AM PDT 24
Peak memory 201368 kb
Host smart-a7887ca1-9fbd-4028-b0a8-9d1290cd8ecd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740048342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3740048342
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.369647227
Short name T901
Test name
Test status
Simulation time 551996498 ps
CPU time 1.07 seconds
Started Jul 01 10:39:16 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 201496 kb
Host smart-ab1db6db-e4ad-496d-a402-575e77b35d55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369647227 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.369647227
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2246216663
Short name T842
Test name
Test status
Simulation time 482140517 ps
CPU time 1.1 seconds
Started Jul 01 10:39:14 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 201480 kb
Host smart-9998689a-0e94-41d5-969e-c40892265a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246216663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2246216663
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3949382413
Short name T844
Test name
Test status
Simulation time 2993177030 ps
CPU time 3.17 seconds
Started Jul 01 10:38:58 AM PDT 24
Finished Jul 01 10:39:01 AM PDT 24
Peak memory 201772 kb
Host smart-72407415-2080-441b-9b14-eb11d943bdf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949382413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3949382413
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3945035029
Short name T906
Test name
Test status
Simulation time 661399642 ps
CPU time 1.88 seconds
Started Jul 01 10:39:17 AM PDT 24
Finished Jul 01 10:39:20 AM PDT 24
Peak memory 201688 kb
Host smart-95057c9d-c0cf-4b34-bfde-85c1fdc29847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945035029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3945035029
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3109633385
Short name T835
Test name
Test status
Simulation time 4206006998 ps
CPU time 3.46 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:03 AM PDT 24
Peak memory 201844 kb
Host smart-88cc49db-0ae6-4cd7-9d33-7e332ac795bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109633385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3109633385
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3514692289
Short name T819
Test name
Test status
Simulation time 476589704 ps
CPU time 1.14 seconds
Started Jul 01 10:39:21 AM PDT 24
Finished Jul 01 10:39:23 AM PDT 24
Peak memory 201328 kb
Host smart-d97d19b9-2f07-4539-9fcb-71f2e13db18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514692289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3514692289
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4261534740
Short name T813
Test name
Test status
Simulation time 444055399 ps
CPU time 0.87 seconds
Started Jul 01 10:40:05 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 201296 kb
Host smart-0a22d434-626d-4fa0-a64f-f9b3a69a3978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261534740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4261534740
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.869686634
Short name T843
Test name
Test status
Simulation time 508945375 ps
CPU time 0.91 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 201344 kb
Host smart-d05e3016-53a9-4350-9fe5-647eff0cedaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869686634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.869686634
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3428338569
Short name T827
Test name
Test status
Simulation time 483345040 ps
CPU time 1.76 seconds
Started Jul 01 10:39:59 AM PDT 24
Finished Jul 01 10:40:01 AM PDT 24
Peak memory 201360 kb
Host smart-12a123a8-544d-41fe-9890-f39a32dd1caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428338569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3428338569
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3880426094
Short name T828
Test name
Test status
Simulation time 452125548 ps
CPU time 0.93 seconds
Started Jul 01 10:39:42 AM PDT 24
Finished Jul 01 10:39:51 AM PDT 24
Peak memory 201344 kb
Host smart-652f957f-61b6-4be0-b76b-563f96880743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880426094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3880426094
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1633246049
Short name T891
Test name
Test status
Simulation time 310231887 ps
CPU time 0.81 seconds
Started Jul 01 10:40:15 AM PDT 24
Finished Jul 01 10:40:18 AM PDT 24
Peak memory 201364 kb
Host smart-ae90016d-d7b8-430d-b6be-8567446c99c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633246049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1633246049
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2196499668
Short name T880
Test name
Test status
Simulation time 430429064 ps
CPU time 1.56 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:42 AM PDT 24
Peak memory 201340 kb
Host smart-d3479689-2255-49ca-bb8b-5c498cb17f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196499668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2196499668
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3719365831
Short name T796
Test name
Test status
Simulation time 403137807 ps
CPU time 1.63 seconds
Started Jul 01 10:39:29 AM PDT 24
Finished Jul 01 10:39:31 AM PDT 24
Peak memory 201352 kb
Host smart-65ff2593-231a-4e86-afdc-4535e2c5aaa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719365831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3719365831
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2860872619
Short name T898
Test name
Test status
Simulation time 368884322 ps
CPU time 1.52 seconds
Started Jul 01 10:39:26 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 201360 kb
Host smart-2e21b8e3-3b80-4cd0-b5a6-fef412a5c20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860872619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2860872619
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4062008570
Short name T809
Test name
Test status
Simulation time 323913888 ps
CPU time 0.81 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 201360 kb
Host smart-ecb40342-f47b-43cc-8306-7306fc1395a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062008570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4062008570
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1751962913
Short name T114
Test name
Test status
Simulation time 436915604 ps
CPU time 1.89 seconds
Started Jul 01 10:39:18 AM PDT 24
Finished Jul 01 10:39:22 AM PDT 24
Peak memory 201592 kb
Host smart-10c49727-f9c7-4509-905a-b7088cbcc35b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751962913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1751962913
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1900676204
Short name T917
Test name
Test status
Simulation time 16704956386 ps
CPU time 37.29 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 201748 kb
Host smart-ad156393-245c-43c5-9c45-dd58665a78fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900676204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1900676204
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2870153035
Short name T838
Test name
Test status
Simulation time 808964465 ps
CPU time 2.41 seconds
Started Jul 01 10:39:08 AM PDT 24
Finished Jul 01 10:39:13 AM PDT 24
Peak memory 201360 kb
Host smart-4d6c34a3-780c-40e1-bb91-356033c2c5a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870153035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2870153035
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1355013725
Short name T868
Test name
Test status
Simulation time 352177244 ps
CPU time 1.71 seconds
Started Jul 01 10:39:17 AM PDT 24
Finished Jul 01 10:39:20 AM PDT 24
Peak memory 201496 kb
Host smart-e556b527-ace5-49cb-bf64-aab49dc0b801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355013725 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1355013725
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1158297708
Short name T119
Test name
Test status
Simulation time 495125040 ps
CPU time 1.11 seconds
Started Jul 01 10:39:11 AM PDT 24
Finished Jul 01 10:39:14 AM PDT 24
Peak memory 201404 kb
Host smart-e47e24dd-1996-4407-b6d2-5227eb101a4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158297708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1158297708
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3155152562
Short name T899
Test name
Test status
Simulation time 391411202 ps
CPU time 1.41 seconds
Started Jul 01 10:38:59 AM PDT 24
Finished Jul 01 10:39:02 AM PDT 24
Peak memory 201360 kb
Host smart-ffb90784-d798-44d7-b9da-a42a881e83a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155152562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3155152562
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.806263815
Short name T892
Test name
Test status
Simulation time 2472657772 ps
CPU time 1.63 seconds
Started Jul 01 10:39:13 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 201492 kb
Host smart-db7686e8-e9fd-4bda-bd11-d023331c840c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806263815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.806263815
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1385069435
Short name T908
Test name
Test status
Simulation time 816122281 ps
CPU time 2.75 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 217528 kb
Host smart-d5319e2e-f9f7-447c-b019-8a2d8fc2a19e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385069435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1385069435
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.969054269
Short name T855
Test name
Test status
Simulation time 4476859681 ps
CPU time 11.73 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:36 AM PDT 24
Peak memory 201624 kb
Host smart-9db2264e-5238-46e0-be1f-ee85700c8573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969054269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.969054269
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1716059971
Short name T807
Test name
Test status
Simulation time 412749396 ps
CPU time 1.11 seconds
Started Jul 01 10:40:05 AM PDT 24
Finished Jul 01 10:40:07 AM PDT 24
Peak memory 201304 kb
Host smart-0745afe8-7c2a-44c9-9810-3da9e37dd8d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716059971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1716059971
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.862957836
Short name T888
Test name
Test status
Simulation time 313880411 ps
CPU time 0.79 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 201364 kb
Host smart-c8157a5f-dbc2-4af3-86db-719ee0319fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862957836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.862957836
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3627283788
Short name T811
Test name
Test status
Simulation time 296896630 ps
CPU time 1.31 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 201328 kb
Host smart-8dd54b65-33bd-4c20-aafc-c833164fd912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627283788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3627283788
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1213491058
Short name T875
Test name
Test status
Simulation time 405832927 ps
CPU time 1.77 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:33 AM PDT 24
Peak memory 201336 kb
Host smart-4fc397d5-c66a-4507-be34-9b97aee12f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213491058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1213491058
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1403438558
Short name T905
Test name
Test status
Simulation time 513813741 ps
CPU time 1 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:43 AM PDT 24
Peak memory 201344 kb
Host smart-503fb3bc-831b-4782-8735-e6fe26296c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403438558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1403438558
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2024699487
Short name T836
Test name
Test status
Simulation time 326177420 ps
CPU time 0.96 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:33 AM PDT 24
Peak memory 201360 kb
Host smart-4aba9be7-9640-4d9b-b8cf-e44cbc21f511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024699487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2024699487
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4264394596
Short name T803
Test name
Test status
Simulation time 385387092 ps
CPU time 0.89 seconds
Started Jul 01 10:39:28 AM PDT 24
Finished Jul 01 10:39:30 AM PDT 24
Peak memory 201336 kb
Host smart-3fb8c41a-4a17-40d3-af61-a9a77d1bb44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264394596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4264394596
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3335853391
Short name T824
Test name
Test status
Simulation time 365467767 ps
CPU time 1.06 seconds
Started Jul 01 10:39:21 AM PDT 24
Finished Jul 01 10:39:23 AM PDT 24
Peak memory 201316 kb
Host smart-db62e6cf-3c99-4878-bbed-81112477d35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335853391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3335853391
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1109599600
Short name T804
Test name
Test status
Simulation time 321394593 ps
CPU time 0.82 seconds
Started Jul 01 10:39:32 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 201320 kb
Host smart-92016a1d-ea17-42fb-a159-a2468047ff76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109599600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1109599600
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2418413902
Short name T801
Test name
Test status
Simulation time 525453975 ps
CPU time 1.32 seconds
Started Jul 01 10:40:04 AM PDT 24
Finished Jul 01 10:40:12 AM PDT 24
Peak memory 201336 kb
Host smart-6e32bb22-ff8c-47f7-aa1d-6afe1a472b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418413902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2418413902
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4016884672
Short name T110
Test name
Test status
Simulation time 1379735038 ps
CPU time 3.64 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:32 AM PDT 24
Peak memory 201604 kb
Host smart-dde5c58d-5647-4b3a-90b2-0437ca8a90d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016884672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4016884672
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4051162506
Short name T851
Test name
Test status
Simulation time 26341858055 ps
CPU time 21.44 seconds
Started Jul 01 10:39:25 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 201736 kb
Host smart-b5f93986-1a9d-4e85-b66d-6998c147b0f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051162506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4051162506
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.76653374
Short name T118
Test name
Test status
Simulation time 1389092561 ps
CPU time 1.33 seconds
Started Jul 01 10:39:26 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 201436 kb
Host smart-f4184da6-753b-4183-b6cb-fe94b0610ee2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76653374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_res
et.76653374
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2319640876
Short name T831
Test name
Test status
Simulation time 560583699 ps
CPU time 2.18 seconds
Started Jul 01 10:39:14 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 201496 kb
Host smart-03b9a707-674c-4977-a342-62809d07fbe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319640876 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2319640876
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.626351494
Short name T120
Test name
Test status
Simulation time 467233653 ps
CPU time 1.87 seconds
Started Jul 01 10:39:26 AM PDT 24
Finished Jul 01 10:39:28 AM PDT 24
Peak memory 201420 kb
Host smart-d9fcdff2-82dc-4629-8fa3-1e5975a5f348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626351494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.626351494
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1643898992
Short name T797
Test name
Test status
Simulation time 326017949 ps
CPU time 1.29 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 201336 kb
Host smart-1999f18d-e5bc-4c80-813d-bcb0442e7657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643898992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1643898992
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3738713679
Short name T915
Test name
Test status
Simulation time 4060467157 ps
CPU time 9.69 seconds
Started Jul 01 10:39:00 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 201776 kb
Host smart-c707688c-b86d-46fe-810a-c01bbe66a88a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738713679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3738713679
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1355315749
Short name T70
Test name
Test status
Simulation time 590640568 ps
CPU time 3.58 seconds
Started Jul 01 10:39:06 AM PDT 24
Finished Jul 01 10:39:13 AM PDT 24
Peak memory 201724 kb
Host smart-39267408-9dcc-4e8d-ba34-7fba864122d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355315749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1355315749
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2843932221
Short name T56
Test name
Test status
Simulation time 4001201864 ps
CPU time 10.77 seconds
Started Jul 01 10:39:01 AM PDT 24
Finished Jul 01 10:39:12 AM PDT 24
Peak memory 201748 kb
Host smart-d54410c6-db7b-4f21-93b3-79826b5cdf5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843932221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2843932221
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1252882767
Short name T832
Test name
Test status
Simulation time 336698176 ps
CPU time 1.42 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:47 AM PDT 24
Peak memory 201356 kb
Host smart-8092cd47-4532-450f-be4b-d82e181dbadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252882767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1252882767
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1239107547
Short name T914
Test name
Test status
Simulation time 443908423 ps
CPU time 0.87 seconds
Started Jul 01 10:39:44 AM PDT 24
Finished Jul 01 10:39:48 AM PDT 24
Peak memory 201332 kb
Host smart-e9e7f0e7-b46e-4761-8f5a-869579e5cb2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239107547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1239107547
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1498224428
Short name T859
Test name
Test status
Simulation time 529506670 ps
CPU time 0.93 seconds
Started Jul 01 10:39:27 AM PDT 24
Finished Jul 01 10:39:29 AM PDT 24
Peak memory 201332 kb
Host smart-2a515c28-7a09-4327-8293-a9d0268da5fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498224428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1498224428
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.633983353
Short name T893
Test name
Test status
Simulation time 387220785 ps
CPU time 0.82 seconds
Started Jul 01 10:39:38 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 201348 kb
Host smart-d0233d40-185d-4413-93ed-af27a4671098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633983353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.633983353
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4215441631
Short name T795
Test name
Test status
Simulation time 479229099 ps
CPU time 0.96 seconds
Started Jul 01 10:39:41 AM PDT 24
Finished Jul 01 10:39:46 AM PDT 24
Peak memory 201336 kb
Host smart-5ba77a98-6ff4-418c-9251-08dbe2162bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215441631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4215441631
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2981868325
Short name T860
Test name
Test status
Simulation time 494514943 ps
CPU time 1.19 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:41 AM PDT 24
Peak memory 201356 kb
Host smart-7a66979e-49c6-4cd4-9f60-86472a283308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981868325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2981868325
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.863773834
Short name T858
Test name
Test status
Simulation time 296996267 ps
CPU time 1.26 seconds
Started Jul 01 10:40:20 AM PDT 24
Finished Jul 01 10:40:25 AM PDT 24
Peak memory 201336 kb
Host smart-1e2ec229-66b5-476b-9e38-a9ab2fc60eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863773834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.863773834
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3406266301
Short name T879
Test name
Test status
Simulation time 307947080 ps
CPU time 1.4 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:33 AM PDT 24
Peak memory 201292 kb
Host smart-15851be1-f9d8-433b-bc47-57dc41096865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406266301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3406266301
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1281995840
Short name T798
Test name
Test status
Simulation time 292622594 ps
CPU time 1.22 seconds
Started Jul 01 10:39:35 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 201292 kb
Host smart-165e8d50-9eab-40bb-8586-519217035f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281995840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1281995840
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.393291890
Short name T865
Test name
Test status
Simulation time 529262531 ps
CPU time 1.87 seconds
Started Jul 01 10:39:19 AM PDT 24
Finished Jul 01 10:39:23 AM PDT 24
Peak memory 201432 kb
Host smart-54c79923-2120-4091-a7ea-2ead8393e8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393291890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.393291890
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3920949376
Short name T869
Test name
Test status
Simulation time 618337895 ps
CPU time 1.1 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:29 AM PDT 24
Peak memory 201388 kb
Host smart-b0d2eb16-4c99-4b62-ba16-73cdbce93f76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920949376 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3920949376
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.484119776
Short name T911
Test name
Test status
Simulation time 408925243 ps
CPU time 1.15 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 201420 kb
Host smart-e70772bc-65ea-47f2-8c4d-afe7cc4b747b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484119776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.484119776
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2790639986
Short name T834
Test name
Test status
Simulation time 435886375 ps
CPU time 1.59 seconds
Started Jul 01 10:39:34 AM PDT 24
Finished Jul 01 10:39:38 AM PDT 24
Peak memory 201328 kb
Host smart-5d92f625-98bc-41ba-8a94-9dec38b85ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790639986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2790639986
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4193853196
Short name T870
Test name
Test status
Simulation time 2843798468 ps
CPU time 11.91 seconds
Started Jul 01 10:39:01 AM PDT 24
Finished Jul 01 10:39:13 AM PDT 24
Peak memory 201720 kb
Host smart-48d742ec-685b-492f-8e8a-840c9971af58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193853196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4193853196
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1634343168
Short name T66
Test name
Test status
Simulation time 567500680 ps
CPU time 2.08 seconds
Started Jul 01 10:39:11 AM PDT 24
Finished Jul 01 10:39:15 AM PDT 24
Peak memory 201708 kb
Host smart-87f7c3b3-b727-40b9-b6b0-304c4ee0a5b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634343168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1634343168
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4253590778
Short name T72
Test name
Test status
Simulation time 4300286633 ps
CPU time 3.84 seconds
Started Jul 01 10:39:00 AM PDT 24
Finished Jul 01 10:39:04 AM PDT 24
Peak memory 201792 kb
Host smart-b6389abc-a7fa-4735-a1f4-a9c4a6ecab88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253590778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4253590778
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.926020791
Short name T800
Test name
Test status
Simulation time 552997284 ps
CPU time 1.32 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 201452 kb
Host smart-2ca03a28-d9ce-47e8-90f0-ea8da909aec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926020791 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.926020791
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3141867096
Short name T878
Test name
Test status
Simulation time 375409593 ps
CPU time 1.18 seconds
Started Jul 01 10:38:58 AM PDT 24
Finished Jul 01 10:39:00 AM PDT 24
Peak memory 201420 kb
Host smart-792a1e1f-dab5-4a21-a9d6-41e5fa955321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141867096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3141867096
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4274836799
Short name T810
Test name
Test status
Simulation time 456251201 ps
CPU time 0.94 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:32 AM PDT 24
Peak memory 201336 kb
Host smart-a70ed78f-3095-4c25-92cd-7118073ad350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274836799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4274836799
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1367861331
Short name T895
Test name
Test status
Simulation time 2990968215 ps
CPU time 9.53 seconds
Started Jul 01 10:39:29 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 201560 kb
Host smart-57cf396b-d0b1-4e31-850f-d65e0c448988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367861331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1367861331
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1554202030
Short name T821
Test name
Test status
Simulation time 312151578 ps
CPU time 1.9 seconds
Started Jul 01 10:39:05 AM PDT 24
Finished Jul 01 10:39:10 AM PDT 24
Peak memory 201644 kb
Host smart-cbb40f49-d5df-4d18-b11e-668edd671913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554202030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1554202030
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1011357207
Short name T334
Test name
Test status
Simulation time 3992766527 ps
CPU time 6.53 seconds
Started Jul 01 10:39:10 AM PDT 24
Finished Jul 01 10:39:18 AM PDT 24
Peak memory 201672 kb
Host smart-a8cc0672-5e19-4ba0-a9e4-aa21fea89f79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011357207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1011357207
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3976305165
Short name T873
Test name
Test status
Simulation time 458895410 ps
CPU time 1.07 seconds
Started Jul 01 10:39:12 AM PDT 24
Finished Jul 01 10:39:15 AM PDT 24
Peak memory 201480 kb
Host smart-24ae223c-72b6-4901-af87-87c0d0720a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976305165 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3976305165
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.834979731
Short name T122
Test name
Test status
Simulation time 508467842 ps
CPU time 0.86 seconds
Started Jul 01 10:39:05 AM PDT 24
Finished Jul 01 10:39:08 AM PDT 24
Peak memory 201392 kb
Host smart-c9011670-2049-468b-9f2d-d4c05e27eeed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834979731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.834979731
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.31712035
Short name T845
Test name
Test status
Simulation time 290009804 ps
CPU time 0.97 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:34 AM PDT 24
Peak memory 201348 kb
Host smart-5a0f8dd4-a7e7-42d6-bb1f-7e43d7792966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31712035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.31712035
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.518177819
Short name T876
Test name
Test status
Simulation time 4628958475 ps
CPU time 4.99 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:44 AM PDT 24
Peak memory 201664 kb
Host smart-202b98f3-17cc-4aaf-b513-c161aa630fbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518177819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.518177819
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2487701736
Short name T64
Test name
Test status
Simulation time 377515506 ps
CPU time 2.76 seconds
Started Jul 01 10:39:04 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 210884 kb
Host smart-5ca96e20-5eb7-42a5-aaff-95bbd775ace0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487701736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2487701736
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2139796800
Short name T333
Test name
Test status
Simulation time 8170013512 ps
CPU time 21.76 seconds
Started Jul 01 10:39:44 AM PDT 24
Finished Jul 01 10:40:09 AM PDT 24
Peak memory 201748 kb
Host smart-33f8edf4-9735-4b16-811f-7ce27cd1b1b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139796800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2139796800
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.595146103
Short name T812
Test name
Test status
Simulation time 598784623 ps
CPU time 1.3 seconds
Started Jul 01 10:39:19 AM PDT 24
Finished Jul 01 10:39:21 AM PDT 24
Peak memory 201348 kb
Host smart-bc180f82-51b4-4197-a4bd-b8fcbb550ed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595146103 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.595146103
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2220384545
Short name T111
Test name
Test status
Simulation time 606455972 ps
CPU time 1.06 seconds
Started Jul 01 10:40:28 AM PDT 24
Finished Jul 01 10:40:31 AM PDT 24
Peak memory 201328 kb
Host smart-4c1451ab-6a85-46b9-8f5f-94c53ce7ea28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220384545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2220384545
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1825380429
Short name T820
Test name
Test status
Simulation time 307113591 ps
CPU time 0.77 seconds
Started Jul 01 10:40:25 AM PDT 24
Finished Jul 01 10:40:28 AM PDT 24
Peak memory 201240 kb
Host smart-0880730f-582c-43b3-8bcd-f37ee73360b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825380429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1825380429
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2383606642
Short name T849
Test name
Test status
Simulation time 5407810645 ps
CPU time 6.82 seconds
Started Jul 01 10:39:30 AM PDT 24
Finished Jul 01 10:39:39 AM PDT 24
Peak memory 201708 kb
Host smart-98d1d7a4-931c-489b-ade5-dba7a2920a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383606642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2383606642
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.895300871
Short name T882
Test name
Test status
Simulation time 493114094 ps
CPU time 1.58 seconds
Started Jul 01 10:39:31 AM PDT 24
Finished Jul 01 10:39:35 AM PDT 24
Peak memory 201640 kb
Host smart-d35c119b-3dc8-4601-90b6-4405859808bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895300871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.895300871
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1509672421
Short name T73
Test name
Test status
Simulation time 8575822501 ps
CPU time 6.74 seconds
Started Jul 01 10:40:27 AM PDT 24
Finished Jul 01 10:40:36 AM PDT 24
Peak memory 201632 kb
Host smart-e9b0547d-004d-4f82-9f34-c8341c528d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509672421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1509672421
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1905843962
Short name T60
Test name
Test status
Simulation time 538869703 ps
CPU time 1.75 seconds
Started Jul 01 10:39:05 AM PDT 24
Finished Jul 01 10:39:09 AM PDT 24
Peak memory 201496 kb
Host smart-932abde6-6bfb-4042-8f3b-dc604b1c2920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905843962 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1905843962
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3959108542
Short name T840
Test name
Test status
Simulation time 425624170 ps
CPU time 0.82 seconds
Started Jul 01 10:39:03 AM PDT 24
Finished Jul 01 10:39:05 AM PDT 24
Peak memory 201400 kb
Host smart-b4a765d8-ded0-4cc1-9fbc-a8865caa35c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959108542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3959108542
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4090619681
Short name T833
Test name
Test status
Simulation time 341724520 ps
CPU time 0.73 seconds
Started Jul 01 10:39:36 AM PDT 24
Finished Jul 01 10:39:40 AM PDT 24
Peak memory 201340 kb
Host smart-8868504a-709c-484a-8b7a-0766b23d54be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090619681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4090619681
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.857851040
Short name T871
Test name
Test status
Simulation time 4601421869 ps
CPU time 2.93 seconds
Started Jul 01 10:39:02 AM PDT 24
Finished Jul 01 10:39:06 AM PDT 24
Peak memory 201732 kb
Host smart-4d60cf97-fc11-4a38-8b70-fb91c99d6ab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857851040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.857851040
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.115074663
Short name T839
Test name
Test status
Simulation time 981513786 ps
CPU time 2.08 seconds
Started Jul 01 10:39:18 AM PDT 24
Finished Jul 01 10:39:22 AM PDT 24
Peak memory 217604 kb
Host smart-307165be-6557-449a-a215-fd59fbee6497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115074663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.115074663
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2498257969
Short name T826
Test name
Test status
Simulation time 4241687337 ps
CPU time 6.78 seconds
Started Jul 01 10:39:07 AM PDT 24
Finished Jul 01 10:39:16 AM PDT 24
Peak memory 201760 kb
Host smart-072e9e49-a7a8-4a50-859b-f0c9693e6e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498257969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2498257969
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3601322280
Short name T527
Test name
Test status
Simulation time 388197860 ps
CPU time 1.58 seconds
Started Jul 01 11:14:01 AM PDT 24
Finished Jul 01 11:14:04 AM PDT 24
Peak memory 201588 kb
Host smart-55f7942d-c748-4bbd-bdd1-a429f675d9d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601322280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3601322280
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2267196923
Short name T181
Test name
Test status
Simulation time 349037919899 ps
CPU time 192.07 seconds
Started Jul 01 11:14:01 AM PDT 24
Finished Jul 01 11:17:14 AM PDT 24
Peak memory 201828 kb
Host smart-5879734d-eeb1-4f6c-8b54-23ccc96f66cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267196923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2267196923
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1143920848
Short name T762
Test name
Test status
Simulation time 162672562458 ps
CPU time 80.7 seconds
Started Jul 01 11:14:28 AM PDT 24
Finished Jul 01 11:15:49 AM PDT 24
Peak memory 201884 kb
Host smart-915281dc-fc82-4d9d-9ba0-ec90c5387a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143920848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1143920848
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.900965176
Short name T193
Test name
Test status
Simulation time 486879188691 ps
CPU time 264.79 seconds
Started Jul 01 11:13:51 AM PDT 24
Finished Jul 01 11:18:17 AM PDT 24
Peak memory 201836 kb
Host smart-b49e31ed-f5da-4b9d-a40d-0a9641149fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900965176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.900965176
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2900495800
Short name T498
Test name
Test status
Simulation time 330563897065 ps
CPU time 785.78 seconds
Started Jul 01 11:14:26 AM PDT 24
Finished Jul 01 11:27:32 AM PDT 24
Peak memory 201844 kb
Host smart-0e47a7a3-58a0-4376-b6a8-bee459a90342
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900495800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2900495800
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.322127281
Short name T250
Test name
Test status
Simulation time 497787466427 ps
CPU time 365.11 seconds
Started Jul 01 11:14:23 AM PDT 24
Finished Jul 01 11:20:29 AM PDT 24
Peak memory 201952 kb
Host smart-7e1d9124-7a1f-489a-815c-46539d4b2dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322127281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.322127281
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2445200240
Short name T35
Test name
Test status
Simulation time 162601719594 ps
CPU time 92.98 seconds
Started Jul 01 11:13:50 AM PDT 24
Finished Jul 01 11:15:25 AM PDT 24
Peak memory 201908 kb
Host smart-a8914dcd-0e82-4093-bf94-a7c096a54228
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445200240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2445200240
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2238163833
Short name T636
Test name
Test status
Simulation time 180491074408 ps
CPU time 403.66 seconds
Started Jul 01 11:13:51 AM PDT 24
Finished Jul 01 11:20:36 AM PDT 24
Peak memory 201804 kb
Host smart-97235b4f-fd7a-4027-bdfc-9ac8bb27adca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238163833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2238163833
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2154565780
Short name T81
Test name
Test status
Simulation time 598672583518 ps
CPU time 1409.31 seconds
Started Jul 01 11:13:52 AM PDT 24
Finished Jul 01 11:37:23 AM PDT 24
Peak memory 201908 kb
Host smart-900b9aa3-08c7-48eb-8102-7c5e33c16662
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154565780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2154565780
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4052758054
Short name T471
Test name
Test status
Simulation time 98892085102 ps
CPU time 513.01 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:22:37 AM PDT 24
Peak memory 202236 kb
Host smart-da7f5bcd-b319-4a1f-a98c-ca7786b436f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052758054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4052758054
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1213851786
Short name T403
Test name
Test status
Simulation time 29827936010 ps
CPU time 7.11 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:14:11 AM PDT 24
Peak memory 201688 kb
Host smart-079f61a3-a897-4da1-ab50-2026f995f2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213851786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1213851786
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2099300460
Short name T137
Test name
Test status
Simulation time 4517923228 ps
CPU time 10.26 seconds
Started Jul 01 11:14:01 AM PDT 24
Finished Jul 01 11:14:13 AM PDT 24
Peak memory 201672 kb
Host smart-d8c222b5-2c5d-41cb-8004-7d154ef254df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099300460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2099300460
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.323221745
Short name T674
Test name
Test status
Simulation time 5934874567 ps
CPU time 4.68 seconds
Started Jul 01 11:13:49 AM PDT 24
Finished Jul 01 11:13:54 AM PDT 24
Peak memory 201632 kb
Host smart-dbec0c6f-bd8a-4e5e-a5a6-bb53f9c9d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323221745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.323221745
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.515718310
Short name T662
Test name
Test status
Simulation time 325238619233 ps
CPU time 699.85 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:25:42 AM PDT 24
Peak memory 201828 kb
Host smart-cb8343b7-878b-4bce-ba83-bc3810869d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515718310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.515718310
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2926884552
Short name T647
Test name
Test status
Simulation time 522740605 ps
CPU time 0.7 seconds
Started Jul 01 11:14:01 AM PDT 24
Finished Jul 01 11:14:03 AM PDT 24
Peak memory 201628 kb
Host smart-1519f575-858b-485b-88e7-5dca6a9fe3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926884552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2926884552
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1646637076
Short name T318
Test name
Test status
Simulation time 349197999269 ps
CPU time 330.58 seconds
Started Jul 01 11:13:59 AM PDT 24
Finished Jul 01 11:19:30 AM PDT 24
Peak memory 201928 kb
Host smart-b6ef5a72-6f64-47d9-9148-9f6c5a1f3af1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646637076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1646637076
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2063119870
Short name T544
Test name
Test status
Simulation time 491091878220 ps
CPU time 305.84 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:19:10 AM PDT 24
Peak memory 201888 kb
Host smart-c82e9018-b3c6-457f-ae66-57d5def93781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063119870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2063119870
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2074094133
Short name T584
Test name
Test status
Simulation time 326596199295 ps
CPU time 395.41 seconds
Started Jul 01 11:14:01 AM PDT 24
Finished Jul 01 11:20:38 AM PDT 24
Peak memory 201868 kb
Host smart-c3c90ede-7dab-4092-8043-1f4ea267f74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074094133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2074094133
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1516931747
Short name T706
Test name
Test status
Simulation time 496907829810 ps
CPU time 309.36 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:19:11 AM PDT 24
Peak memory 201828 kb
Host smart-fc6bed87-9b5c-4692-83bf-ba5ba5017fbb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516931747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1516931747
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3972215069
Short name T180
Test name
Test status
Simulation time 324049710450 ps
CPU time 123.47 seconds
Started Jul 01 11:13:59 AM PDT 24
Finished Jul 01 11:16:03 AM PDT 24
Peak memory 201932 kb
Host smart-6dd703b4-cfd0-47d9-8e89-7a818bcc28fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972215069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3972215069
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2738414565
Short name T27
Test name
Test status
Simulation time 490911617276 ps
CPU time 1076 seconds
Started Jul 01 11:13:58 AM PDT 24
Finished Jul 01 11:31:55 AM PDT 24
Peak memory 201856 kb
Host smart-2628b923-d7bd-4f2c-9f99-ba977b1faf05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738414565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2738414565
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2721015849
Short name T138
Test name
Test status
Simulation time 169778375861 ps
CPU time 38.9 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:15:04 AM PDT 24
Peak memory 201924 kb
Host smart-1a2b4733-009b-4273-8b1e-99aac30544fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721015849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2721015849
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.897185378
Short name T770
Test name
Test status
Simulation time 198538841233 ps
CPU time 118.65 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:16:32 AM PDT 24
Peak memory 201852 kb
Host smart-a464eeb1-e021-40e1-9232-c68863aadb1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897185378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.897185378
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.987991383
Short name T586
Test name
Test status
Simulation time 24580872608 ps
CPU time 13.93 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:14:15 AM PDT 24
Peak memory 201672 kb
Host smart-5d846a1f-bed5-4b69-a786-3a794c0a52b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987991383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.987991383
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3308989469
Short name T606
Test name
Test status
Simulation time 4299541007 ps
CPU time 9.49 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:14:35 AM PDT 24
Peak memory 201680 kb
Host smart-de2eaf83-305a-4963-8c27-0ea03013c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308989469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3308989469
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.412312490
Short name T76
Test name
Test status
Simulation time 7562050063 ps
CPU time 18.84 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:14:22 AM PDT 24
Peak memory 218084 kb
Host smart-d7fa2f1d-bed5-4d57-b51f-a2399d12f660
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412312490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.412312490
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.644059439
Short name T360
Test name
Test status
Simulation time 5846936070 ps
CPU time 15.48 seconds
Started Jul 01 11:14:03 AM PDT 24
Finished Jul 01 11:14:20 AM PDT 24
Peak memory 201636 kb
Host smart-ad7f19f5-1a4d-4f99-bcb0-559902f8d9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644059439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.644059439
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1673243250
Short name T11
Test name
Test status
Simulation time 297175272605 ps
CPU time 504.79 seconds
Started Jul 01 11:14:29 AM PDT 24
Finished Jul 01 11:22:54 AM PDT 24
Peak memory 212804 kb
Host smart-f398b884-71c4-44a1-99c2-3d381f685263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673243250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1673243250
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2532182911
Short name T327
Test name
Test status
Simulation time 138378171374 ps
CPU time 371.12 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:20:15 AM PDT 24
Peak memory 210496 kb
Host smart-4159707e-01ed-42ca-a36a-8f68af0cbe66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532182911 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2532182911
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1264090273
Short name T408
Test name
Test status
Simulation time 478716727 ps
CPU time 1.7 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:14:55 AM PDT 24
Peak memory 201644 kb
Host smart-52fd613b-dc2b-472a-a7e1-7bc7e3abbab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264090273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1264090273
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.387409031
Short name T315
Test name
Test status
Simulation time 390745760056 ps
CPU time 737.12 seconds
Started Jul 01 11:14:21 AM PDT 24
Finished Jul 01 11:26:38 AM PDT 24
Peak memory 201988 kb
Host smart-f850187a-237a-4cee-8a55-7108e442b550
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387409031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.387409031
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1114217254
Short name T310
Test name
Test status
Simulation time 497405029822 ps
CPU time 1179.57 seconds
Started Jul 01 11:14:23 AM PDT 24
Finished Jul 01 11:34:03 AM PDT 24
Peak memory 201864 kb
Host smart-88295b76-3a67-45d0-8035-3b0e043f385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114217254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1114217254
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1662058384
Short name T725
Test name
Test status
Simulation time 503651439732 ps
CPU time 567.36 seconds
Started Jul 01 11:14:20 AM PDT 24
Finished Jul 01 11:23:47 AM PDT 24
Peak memory 201896 kb
Host smart-9299011b-321c-41ff-b901-03d09a7f88c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662058384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1662058384
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1401339697
Short name T393
Test name
Test status
Simulation time 325732344605 ps
CPU time 689.64 seconds
Started Jul 01 11:14:23 AM PDT 24
Finished Jul 01 11:25:54 AM PDT 24
Peak memory 201828 kb
Host smart-186876f1-395b-4e31-a322-71e2dea025ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401339697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1401339697
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2936854764
Short name T265
Test name
Test status
Simulation time 326249533466 ps
CPU time 239.68 seconds
Started Jul 01 11:14:38 AM PDT 24
Finished Jul 01 11:18:39 AM PDT 24
Peak memory 201888 kb
Host smart-962b2239-4eb7-4be9-af94-68d80f50f1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936854764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2936854764
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3154880689
Short name T492
Test name
Test status
Simulation time 164962319826 ps
CPU time 368.82 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:20:31 AM PDT 24
Peak memory 201912 kb
Host smart-b926ad54-3633-4457-a194-a6dd78c91cb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154880689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3154880689
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3014475395
Short name T765
Test name
Test status
Simulation time 376668627496 ps
CPU time 223.59 seconds
Started Jul 01 11:14:35 AM PDT 24
Finished Jul 01 11:18:19 AM PDT 24
Peak memory 201860 kb
Host smart-be856810-223a-4137-8e85-7d7d4b4b50b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014475395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3014475395
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.4124039065
Short name T484
Test name
Test status
Simulation time 398303351381 ps
CPU time 958.3 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:30:42 AM PDT 24
Peak memory 201824 kb
Host smart-f8f548c2-f65f-4996-a76f-239c190638c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124039065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.4124039065
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2585976831
Short name T450
Test name
Test status
Simulation time 122010209112 ps
CPU time 688.22 seconds
Started Jul 01 11:14:21 AM PDT 24
Finished Jul 01 11:25:50 AM PDT 24
Peak memory 202084 kb
Host smart-e523c3cb-9f0d-4d45-8faf-aa798e6c246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585976831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2585976831
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.847218073
Short name T150
Test name
Test status
Simulation time 26039911250 ps
CPU time 53.82 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:15:38 AM PDT 24
Peak memory 201612 kb
Host smart-9d4c5af9-3df4-450f-ae6b-833fbd3fe22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847218073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.847218073
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.573095883
Short name T681
Test name
Test status
Simulation time 2805337139 ps
CPU time 3.85 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:14:56 AM PDT 24
Peak memory 201712 kb
Host smart-e3b3007d-6baa-4052-9a65-3604d0cf0697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573095883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.573095883
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.4187137631
Short name T728
Test name
Test status
Simulation time 5727305350 ps
CPU time 4.33 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:14:29 AM PDT 24
Peak memory 201676 kb
Host smart-32678c08-a634-4942-abdf-73114f0458fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187137631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.4187137631
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1831810029
Short name T614
Test name
Test status
Simulation time 214289327642 ps
CPU time 93 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:15:56 AM PDT 24
Peak memory 201768 kb
Host smart-a5c965d6-f8f8-4691-adb7-1e3bb033267e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831810029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1831810029
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1251777425
Short name T669
Test name
Test status
Simulation time 175838978959 ps
CPU time 188.52 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:18:02 AM PDT 24
Peak memory 217784 kb
Host smart-2223a388-614f-473d-9ca0-b73dca8d4433
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251777425 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1251777425
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2210041955
Short name T79
Test name
Test status
Simulation time 444341922 ps
CPU time 1 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:14:49 AM PDT 24
Peak memory 201600 kb
Host smart-de1042cd-525b-4d99-a042-7695546db40a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210041955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2210041955
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2263478422
Short name T232
Test name
Test status
Simulation time 352934630623 ps
CPU time 410.97 seconds
Started Jul 01 11:14:48 AM PDT 24
Finished Jul 01 11:21:41 AM PDT 24
Peak memory 201804 kb
Host smart-01c16421-92c0-47cb-b7e7-6b77e90bc614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263478422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2263478422
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3638550919
Short name T608
Test name
Test status
Simulation time 167042895668 ps
CPU time 369.32 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:20:53 AM PDT 24
Peak memory 201888 kb
Host smart-3b54d45d-304c-4113-92ee-20442e5bca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638550919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3638550919
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.725765187
Short name T456
Test name
Test status
Simulation time 324211996304 ps
CPU time 387.08 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:21:10 AM PDT 24
Peak memory 201852 kb
Host smart-572b8d5a-46f5-407f-9aee-810983470fda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=725765187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.725765187
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1373527324
Short name T703
Test name
Test status
Simulation time 328835375548 ps
CPU time 786.27 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:27:31 AM PDT 24
Peak memory 201896 kb
Host smart-2b043dea-18e9-4515-a6d7-53435ae2f64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373527324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1373527324
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2163576124
Short name T5
Test name
Test status
Simulation time 164540010547 ps
CPU time 93.37 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:16:14 AM PDT 24
Peak memory 201788 kb
Host smart-7e603649-6fd3-49e9-8d96-af1ead602ff3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163576124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2163576124
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1046935089
Short name T130
Test name
Test status
Simulation time 377810144016 ps
CPU time 272.39 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:18:57 AM PDT 24
Peak memory 201836 kb
Host smart-911d2c71-7731-496c-9d60-7d99408c133b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046935089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1046935089
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.365482083
Short name T100
Test name
Test status
Simulation time 590382176220 ps
CPU time 1278.41 seconds
Started Jul 01 11:14:36 AM PDT 24
Finished Jul 01 11:35:55 AM PDT 24
Peak memory 201844 kb
Host smart-53dc5565-723e-4d20-9c9c-8ae29053285e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365482083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.365482083
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1478714826
Short name T148
Test name
Test status
Simulation time 116874775760 ps
CPU time 419.8 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:21:43 AM PDT 24
Peak memory 202200 kb
Host smart-57d47d9d-615c-4fb5-8f1b-479b01e0f68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478714826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1478714826
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3404578837
Short name T358
Test name
Test status
Simulation time 46477747462 ps
CPU time 105.02 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:16:26 AM PDT 24
Peak memory 201692 kb
Host smart-89a997ba-06fa-4d6d-9e1f-1230c3be9415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404578837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3404578837
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2651686253
Short name T738
Test name
Test status
Simulation time 5296305939 ps
CPU time 3.73 seconds
Started Jul 01 11:14:47 AM PDT 24
Finished Jul 01 11:14:52 AM PDT 24
Peak memory 201664 kb
Host smart-fa4ca4b0-648c-4d3b-8b42-7a63dae830db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651686253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2651686253
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3981311956
Short name T441
Test name
Test status
Simulation time 6074654706 ps
CPU time 13.47 seconds
Started Jul 01 11:14:36 AM PDT 24
Finished Jul 01 11:14:50 AM PDT 24
Peak memory 201664 kb
Host smart-43096f91-85be-4d6f-ae4e-74561c5c6f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981311956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3981311956
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3376901691
Short name T263
Test name
Test status
Simulation time 838295405666 ps
CPU time 1024.11 seconds
Started Jul 01 11:14:47 AM PDT 24
Finished Jul 01 11:31:53 AM PDT 24
Peak memory 201820 kb
Host smart-6cd4a09e-b39b-4c45-a7e4-fd0df6897a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376901691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3376901691
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.185713427
Short name T21
Test name
Test status
Simulation time 19583990208 ps
CPU time 42.51 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:15:08 AM PDT 24
Peak memory 210384 kb
Host smart-b95a5511-3395-4959-ba51-c5fcc975fceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185713427 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.185713427
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2794272302
Short name T473
Test name
Test status
Simulation time 516736606 ps
CPU time 1.55 seconds
Started Jul 01 11:14:25 AM PDT 24
Finished Jul 01 11:14:27 AM PDT 24
Peak memory 201620 kb
Host smart-3ef2225e-74c1-4b29-b3de-29733eefe31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794272302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2794272302
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2053545841
Short name T629
Test name
Test status
Simulation time 180915801837 ps
CPU time 124.84 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:16:45 AM PDT 24
Peak memory 201852 kb
Host smart-953c58c8-5983-44f9-b612-c3bdd2e1de6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053545841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2053545841
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1768526680
Short name T174
Test name
Test status
Simulation time 556035581195 ps
CPU time 276.83 seconds
Started Jul 01 11:14:25 AM PDT 24
Finished Jul 01 11:19:02 AM PDT 24
Peak memory 201908 kb
Host smart-0eaeca19-4d52-4c70-b439-5a87f2d76f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768526680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1768526680
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.307492705
Short name T197
Test name
Test status
Simulation time 331593686957 ps
CPU time 62.02 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:15:27 AM PDT 24
Peak memory 201884 kb
Host smart-dbfaad85-7415-4efb-a954-5ce84364aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307492705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.307492705
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2701625034
Short name T543
Test name
Test status
Simulation time 320673559419 ps
CPU time 412.64 seconds
Started Jul 01 11:14:25 AM PDT 24
Finished Jul 01 11:21:19 AM PDT 24
Peak memory 201832 kb
Host smart-8eb6c4a4-85a0-46e8-984a-096e6c4de1a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701625034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2701625034
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.372800889
Short name T131
Test name
Test status
Simulation time 169875856653 ps
CPU time 414.1 seconds
Started Jul 01 11:14:25 AM PDT 24
Finished Jul 01 11:21:20 AM PDT 24
Peak memory 201928 kb
Host smart-ef13d692-e2cd-4015-a601-07d4e81fc3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372800889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.372800889
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.932449017
Short name T726
Test name
Test status
Simulation time 326774722452 ps
CPU time 789.33 seconds
Started Jul 01 11:14:43 AM PDT 24
Finished Jul 01 11:27:59 AM PDT 24
Peak memory 201768 kb
Host smart-e0b79ae9-455b-41a8-965f-2f359f5d790c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=932449017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.932449017
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1512223658
Short name T281
Test name
Test status
Simulation time 522470774225 ps
CPU time 148.49 seconds
Started Jul 01 11:14:26 AM PDT 24
Finished Jul 01 11:16:55 AM PDT 24
Peak memory 201836 kb
Host smart-9b9a015f-7da1-4527-b82b-efd837afdd1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512223658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1512223658
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.409083068
Short name T189
Test name
Test status
Simulation time 609697215789 ps
CPU time 288.46 seconds
Started Jul 01 11:14:26 AM PDT 24
Finished Jul 01 11:19:16 AM PDT 24
Peak memory 201860 kb
Host smart-17b3a09d-4fa7-4d46-8118-131bd52a01c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409083068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.409083068
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3450116170
Short name T639
Test name
Test status
Simulation time 28963260144 ps
CPU time 12.85 seconds
Started Jul 01 11:14:37 AM PDT 24
Finished Jul 01 11:14:51 AM PDT 24
Peak memory 201628 kb
Host smart-2b3664e3-720e-4e31-841e-684e6cdbc035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450116170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3450116170
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3429058760
Short name T398
Test name
Test status
Simulation time 5102915197 ps
CPU time 5.59 seconds
Started Jul 01 11:14:26 AM PDT 24
Finished Jul 01 11:14:32 AM PDT 24
Peak memory 201660 kb
Host smart-feac91c3-85b7-435d-8590-7981a1d83717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429058760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3429058760
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.133495925
Short name T507
Test name
Test status
Simulation time 5732972062 ps
CPU time 6.49 seconds
Started Jul 01 11:14:43 AM PDT 24
Finished Jul 01 11:14:52 AM PDT 24
Peak memory 201704 kb
Host smart-0536bd48-de52-4b9f-8943-b147f9241a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133495925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.133495925
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.98488807
Short name T540
Test name
Test status
Simulation time 39467759576 ps
CPU time 87.05 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:16:09 AM PDT 24
Peak memory 201640 kb
Host smart-3d6b348c-66bc-4a31-a921-d2e6389c173d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98488807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.98488807
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3009530516
Short name T17
Test name
Test status
Simulation time 517518011763 ps
CPU time 75.11 seconds
Started Jul 01 11:14:27 AM PDT 24
Finished Jul 01 11:15:42 AM PDT 24
Peak memory 210252 kb
Host smart-da1c28e7-c0c0-422d-b848-5a8ab4ca667d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009530516 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3009530516
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2887735828
Short name T457
Test name
Test status
Simulation time 360917946 ps
CPU time 1.02 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:14:44 AM PDT 24
Peak memory 201580 kb
Host smart-b5b6542b-bec9-4033-81ed-d4a3e8eeb088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887735828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2887735828
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3916722712
Short name T539
Test name
Test status
Simulation time 163611656664 ps
CPU time 187.42 seconds
Started Jul 01 11:14:49 AM PDT 24
Finished Jul 01 11:17:57 AM PDT 24
Peak memory 201852 kb
Host smart-486e8aa1-a851-4344-8ff3-567b5c05cad6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916722712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3916722712
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4170100704
Short name T319
Test name
Test status
Simulation time 497525021137 ps
CPU time 587.11 seconds
Started Jul 01 11:14:30 AM PDT 24
Finished Jul 01 11:24:17 AM PDT 24
Peak memory 201876 kb
Host smart-9bf99052-acaf-4527-913a-f069b522c7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170100704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4170100704
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2100335874
Short name T179
Test name
Test status
Simulation time 327162797396 ps
CPU time 194.79 seconds
Started Jul 01 11:14:28 AM PDT 24
Finished Jul 01 11:17:43 AM PDT 24
Peak memory 201880 kb
Host smart-1aff3f32-0ba9-4b5e-8711-c3ad35d16b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100335874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2100335874
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.320881082
Short name T430
Test name
Test status
Simulation time 496295391653 ps
CPU time 159.31 seconds
Started Jul 01 11:14:43 AM PDT 24
Finished Jul 01 11:17:24 AM PDT 24
Peak memory 201872 kb
Host smart-20f8d97e-0c9e-4771-bccd-7f450db5fab0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=320881082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.320881082
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1829650619
Short name T656
Test name
Test status
Simulation time 168637087934 ps
CPU time 100.36 seconds
Started Jul 01 11:14:25 AM PDT 24
Finished Jul 01 11:16:06 AM PDT 24
Peak memory 201928 kb
Host smart-50302816-f124-49ea-bf07-87820fe1c7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829650619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1829650619
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3230110589
Short name T183
Test name
Test status
Simulation time 488755230460 ps
CPU time 253.02 seconds
Started Jul 01 11:14:49 AM PDT 24
Finished Jul 01 11:19:03 AM PDT 24
Peak memory 201896 kb
Host smart-bf3e7a71-0e8b-40bd-ab97-6536e5821629
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230110589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3230110589
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3661299803
Short name T175
Test name
Test status
Simulation time 371333095008 ps
CPU time 230.6 seconds
Started Jul 01 11:14:29 AM PDT 24
Finished Jul 01 11:18:20 AM PDT 24
Peak memory 201852 kb
Host smart-54d0d463-3ceb-4333-80ea-75a17606a4de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661299803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3661299803
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3554907134
Short name T767
Test name
Test status
Simulation time 588722111728 ps
CPU time 139.98 seconds
Started Jul 01 11:14:30 AM PDT 24
Finished Jul 01 11:16:50 AM PDT 24
Peak memory 201884 kb
Host smart-451f4403-2b81-4b3d-8b24-d0a2802855a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554907134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3554907134
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3251210410
Short name T377
Test name
Test status
Simulation time 32525306379 ps
CPU time 38.93 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:15:26 AM PDT 24
Peak memory 201684 kb
Host smart-5e650a2a-05c7-4b11-a682-dd61437e5014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251210410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3251210410
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3670870233
Short name T559
Test name
Test status
Simulation time 5196624232 ps
CPU time 4.09 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:14:47 AM PDT 24
Peak memory 201664 kb
Host smart-0ce2d508-68b2-404b-b8fe-d9d0c3f1a242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670870233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3670870233
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1819790831
Short name T412
Test name
Test status
Simulation time 5782302438 ps
CPU time 7.75 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:14:51 AM PDT 24
Peak memory 201676 kb
Host smart-327e924d-1d4d-4a52-954e-add9825cae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819790831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1819790831
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1930103914
Short name T198
Test name
Test status
Simulation time 485156564773 ps
CPU time 1110.81 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:33:12 AM PDT 24
Peak memory 201772 kb
Host smart-9142a416-d0d9-4a9f-89e9-93f1ecfd16f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930103914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1930103914
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4129573573
Short name T191
Test name
Test status
Simulation time 369599329066 ps
CPU time 756.57 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:27:08 AM PDT 24
Peak memory 210412 kb
Host smart-6a102cd5-d1b5-4a31-b6b3-9e681b7394c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129573573 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4129573573
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2146372057
Short name T596
Test name
Test status
Simulation time 166756054514 ps
CPU time 184.23 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:17:47 AM PDT 24
Peak memory 201844 kb
Host smart-b3b03597-5268-4606-ba57-bb8d5290dc23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146372057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2146372057
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4143211277
Short name T759
Test name
Test status
Simulation time 164574018228 ps
CPU time 95.09 seconds
Started Jul 01 11:14:30 AM PDT 24
Finished Jul 01 11:16:06 AM PDT 24
Peak memory 201852 kb
Host smart-dd05650a-8106-4547-8678-548c0830299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143211277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.4143211277
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2482955080
Short name T470
Test name
Test status
Simulation time 331869011330 ps
CPU time 369.42 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:20:57 AM PDT 24
Peak memory 201788 kb
Host smart-021a5585-1386-42c1-bcea-c80ef5f16123
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482955080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2482955080
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3205307377
Short name T526
Test name
Test status
Simulation time 486127144774 ps
CPU time 442.68 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:21:54 AM PDT 24
Peak memory 201888 kb
Host smart-cd0b91ce-62ed-4eb6-bb29-77a510b20b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205307377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3205307377
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.673209300
Short name T755
Test name
Test status
Simulation time 167148254294 ps
CPU time 105.51 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:16:30 AM PDT 24
Peak memory 201920 kb
Host smart-7c096e17-60ec-4a35-abd5-91c842a57947
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=673209300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.673209300
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2087742613
Short name T715
Test name
Test status
Simulation time 177280027910 ps
CPU time 229.69 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:18:33 AM PDT 24
Peak memory 201868 kb
Host smart-d594a223-f9e8-49cb-8db9-3f5260fbd08f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087742613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2087742613
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2233792212
Short name T732
Test name
Test status
Simulation time 206852269752 ps
CPU time 110.04 seconds
Started Jul 01 11:14:32 AM PDT 24
Finished Jul 01 11:16:22 AM PDT 24
Peak memory 201856 kb
Host smart-3966583a-d1fa-4360-aaab-d3a44d96e93e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233792212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2233792212
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2413616939
Short name T437
Test name
Test status
Simulation time 75291350159 ps
CPU time 375.43 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:20:47 AM PDT 24
Peak memory 202152 kb
Host smart-84e562a4-e1f7-4671-93ee-ffa5848a369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413616939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2413616939
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1379596887
Short name T405
Test name
Test status
Simulation time 46528497593 ps
CPU time 55.34 seconds
Started Jul 01 11:14:43 AM PDT 24
Finished Jul 01 11:15:40 AM PDT 24
Peak memory 201680 kb
Host smart-4d502df4-cf51-4035-9072-337c60d51d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379596887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1379596887
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.420929101
Short name T541
Test name
Test status
Simulation time 4425382471 ps
CPU time 2.35 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:14:34 AM PDT 24
Peak memory 201684 kb
Host smart-5f4edae5-a972-4ff5-8fcb-c73599ca51ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420929101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.420929101
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.684945740
Short name T25
Test name
Test status
Simulation time 5735199770 ps
CPU time 2.65 seconds
Started Jul 01 11:14:28 AM PDT 24
Finished Jul 01 11:14:31 AM PDT 24
Peak memory 201692 kb
Host smart-b6d43751-24e9-4003-9384-deea2bae3014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684945740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.684945740
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.561569009
Short name T749
Test name
Test status
Simulation time 397520266857 ps
CPU time 224.44 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:18:35 AM PDT 24
Peak memory 201844 kb
Host smart-cfe89617-7a7b-4148-baea-3d1053fbe741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561569009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
561569009
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.269071094
Short name T589
Test name
Test status
Simulation time 448966838 ps
CPU time 1.69 seconds
Started Jul 01 11:14:36 AM PDT 24
Finished Jul 01 11:14:38 AM PDT 24
Peak memory 201628 kb
Host smart-69a75ae3-2f6d-4eda-830e-ba68233ec3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269071094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.269071094
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.893113611
Short name T243
Test name
Test status
Simulation time 520112383342 ps
CPU time 678.98 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:26:07 AM PDT 24
Peak memory 201852 kb
Host smart-7b7ba49f-ff27-4bff-ad65-1856d825bb4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893113611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.893113611
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.478550456
Short name T777
Test name
Test status
Simulation time 491604500852 ps
CPU time 214.97 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:18:32 AM PDT 24
Peak memory 201496 kb
Host smart-f6a88412-c74f-43bd-8d9f-4d18494c4a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478550456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.478550456
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.920928238
Short name T469
Test name
Test status
Simulation time 326848841638 ps
CPU time 707.94 seconds
Started Jul 01 11:14:36 AM PDT 24
Finished Jul 01 11:26:25 AM PDT 24
Peak memory 201828 kb
Host smart-bce2c10a-1067-4dd8-bc29-595a7c29a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920928238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.920928238
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.752036593
Short name T394
Test name
Test status
Simulation time 161359577808 ps
CPU time 340.04 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:20:23 AM PDT 24
Peak memory 201888 kb
Host smart-f9f43133-2295-4137-8c43-b7c266b73a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752036593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.752036593
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2439378617
Short name T529
Test name
Test status
Simulation time 327420741205 ps
CPU time 719.07 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:26:45 AM PDT 24
Peak memory 201836 kb
Host smart-e5deab57-2d73-485d-9c2e-dbaf983d6a4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439378617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2439378617
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.50344456
Short name T257
Test name
Test status
Simulation time 204476176309 ps
CPU time 445.44 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:22:08 AM PDT 24
Peak memory 201888 kb
Host smart-3bb878f4-ea9c-4af0-b5f8-573503ec0228
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50344456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_w
akeup.50344456
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2260476132
Short name T399
Test name
Test status
Simulation time 207084956573 ps
CPU time 491.02 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:22:57 AM PDT 24
Peak memory 202124 kb
Host smart-d5a702fa-fcf3-42f0-809e-cf46a965dfb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260476132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2260476132
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2893692305
Short name T212
Test name
Test status
Simulation time 91841870609 ps
CPU time 409.21 seconds
Started Jul 01 11:14:36 AM PDT 24
Finished Jul 01 11:21:25 AM PDT 24
Peak memory 202228 kb
Host smart-42532e51-14e3-477d-8121-46c4468d3e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893692305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2893692305
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1387345808
Short name T517
Test name
Test status
Simulation time 26403415726 ps
CPU time 59.07 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:15:33 AM PDT 24
Peak memory 201668 kb
Host smart-49c933f9-8154-420f-9cfe-e6f7d029f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387345808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1387345808
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1677816947
Short name T569
Test name
Test status
Simulation time 3116975441 ps
CPU time 2.39 seconds
Started Jul 01 11:14:34 AM PDT 24
Finished Jul 01 11:14:37 AM PDT 24
Peak memory 201576 kb
Host smart-e0d61844-8553-40bc-8ea0-002350c0ac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677816947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1677816947
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1796425463
Short name T487
Test name
Test status
Simulation time 5856077229 ps
CPU time 13.1 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:14:47 AM PDT 24
Peak memory 201608 kb
Host smart-8d2bf4e1-52b1-41cb-8362-d8fd9d4deeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796425463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1796425463
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1596121760
Short name T332
Test name
Test status
Simulation time 521471542964 ps
CPU time 1526.81 seconds
Started Jul 01 11:14:32 AM PDT 24
Finished Jul 01 11:40:00 AM PDT 24
Peak memory 210344 kb
Host smart-b715d2dc-c40b-4c1c-bbdb-16167b693b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596121760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1596121760
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2356532155
Short name T463
Test name
Test status
Simulation time 367814433 ps
CPU time 0.72 seconds
Started Jul 01 11:14:35 AM PDT 24
Finished Jul 01 11:14:36 AM PDT 24
Peak memory 201624 kb
Host smart-ded4370c-879d-40a0-8e3d-b2f0fee321f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356532155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2356532155
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4100059550
Short name T308
Test name
Test status
Simulation time 485492630997 ps
CPU time 263.58 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:18:58 AM PDT 24
Peak memory 201756 kb
Host smart-616be042-14a7-48f2-915b-150396bb11c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100059550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4100059550
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.225596054
Short name T701
Test name
Test status
Simulation time 168847522459 ps
CPU time 108.26 seconds
Started Jul 01 11:14:35 AM PDT 24
Finished Jul 01 11:16:23 AM PDT 24
Peak memory 201844 kb
Host smart-a6f70192-78d6-420b-81bb-e1336a353440
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=225596054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.225596054
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2810582480
Short name T610
Test name
Test status
Simulation time 336682888959 ps
CPU time 121.48 seconds
Started Jul 01 11:14:48 AM PDT 24
Finished Jul 01 11:16:51 AM PDT 24
Peak memory 201776 kb
Host smart-cc5a5bf4-d3e7-4bc2-885d-40e833e39f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810582480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2810582480
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4188997510
Short name T423
Test name
Test status
Simulation time 164461441047 ps
CPU time 90.26 seconds
Started Jul 01 11:14:35 AM PDT 24
Finished Jul 01 11:16:06 AM PDT 24
Peak memory 201840 kb
Host smart-5375de08-01d6-48da-8529-1f341cc32cd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188997510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4188997510
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2048155976
Short name T585
Test name
Test status
Simulation time 393581334404 ps
CPU time 420.06 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:21:47 AM PDT 24
Peak memory 201892 kb
Host smart-1bdf2cb6-3b0a-4c43-bf49-d5e1294108e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048155976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2048155976
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3379856361
Short name T705
Test name
Test status
Simulation time 125428455838 ps
CPU time 637.02 seconds
Started Jul 01 11:14:43 AM PDT 24
Finished Jul 01 11:25:21 AM PDT 24
Peak memory 202128 kb
Host smart-d8abf5fa-2dc8-44cf-8516-f7e2b77214ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379856361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3379856361
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2694226130
Short name T717
Test name
Test status
Simulation time 41433227439 ps
CPU time 68.67 seconds
Started Jul 01 11:14:34 AM PDT 24
Finished Jul 01 11:15:43 AM PDT 24
Peak memory 201652 kb
Host smart-40ce8c73-07eb-43af-9a2b-2aa043365863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694226130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2694226130
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.594787637
Short name T655
Test name
Test status
Simulation time 4387319984 ps
CPU time 3.55 seconds
Started Jul 01 11:14:47 AM PDT 24
Finished Jul 01 11:14:58 AM PDT 24
Peak memory 201676 kb
Host smart-dd957885-b14a-49e4-ae99-573b73bdd069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594787637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.594787637
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3013152568
Short name T575
Test name
Test status
Simulation time 6155126843 ps
CPU time 1.57 seconds
Started Jul 01 11:14:37 AM PDT 24
Finished Jul 01 11:14:39 AM PDT 24
Peak memory 201664 kb
Host smart-2eda32dd-ae6d-4d08-ae58-2c42071f2d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013152568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3013152568
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.491145449
Short name T634
Test name
Test status
Simulation time 336202370723 ps
CPU time 128 seconds
Started Jul 01 11:14:49 AM PDT 24
Finished Jul 01 11:16:58 AM PDT 24
Peak memory 201744 kb
Host smart-d9857a45-b306-41b6-aa8d-6f5120c3dabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491145449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
491145449
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.731961073
Short name T44
Test name
Test status
Simulation time 55434462532 ps
CPU time 29.2 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:15:09 AM PDT 24
Peak memory 210268 kb
Host smart-268a9a18-aa72-4061-8cce-9b863c72988e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731961073 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.731961073
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3157828597
Short name T410
Test name
Test status
Simulation time 492701681 ps
CPU time 1.66 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:14:44 AM PDT 24
Peak memory 201624 kb
Host smart-a5ea51f6-ff11-42f2-bf57-93e9308ac029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157828597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3157828597
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.4194490903
Short name T236
Test name
Test status
Simulation time 331815599326 ps
CPU time 297.67 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:19:45 AM PDT 24
Peak memory 201868 kb
Host smart-cf4a22b8-ea64-45cb-b11d-991980458651
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194490903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.4194490903
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2369543538
Short name T490
Test name
Test status
Simulation time 201311454796 ps
CPU time 125.15 seconds
Started Jul 01 11:14:58 AM PDT 24
Finished Jul 01 11:17:04 AM PDT 24
Peak memory 201868 kb
Host smart-2906d4bc-a878-4837-a9d4-9840c433049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369543538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2369543538
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1880282940
Short name T753
Test name
Test status
Simulation time 163340291035 ps
CPU time 391.9 seconds
Started Jul 01 11:14:36 AM PDT 24
Finished Jul 01 11:21:09 AM PDT 24
Peak memory 201836 kb
Host smart-1961a7d7-d9a4-4e61-b7c2-58548704fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880282940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1880282940
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1576376109
Short name T400
Test name
Test status
Simulation time 162846046185 ps
CPU time 86.38 seconds
Started Jul 01 11:14:49 AM PDT 24
Finished Jul 01 11:16:16 AM PDT 24
Peak memory 201736 kb
Host smart-a3af2b5c-fd15-4ad9-bde7-0db014a44845
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576376109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1576376109
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1869430501
Short name T654
Test name
Test status
Simulation time 327748133988 ps
CPU time 783.11 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:27:47 AM PDT 24
Peak memory 201840 kb
Host smart-c3e4a5ad-a3ff-4c0d-944f-250bc498b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869430501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1869430501
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.316671799
Short name T576
Test name
Test status
Simulation time 161902703037 ps
CPU time 383.48 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:21:10 AM PDT 24
Peak memory 201756 kb
Host smart-3e42969e-5387-4e5c-8b66-a9a43dd5b28d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=316671799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.316671799
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2311412927
Short name T392
Test name
Test status
Simulation time 200486344064 ps
CPU time 483.11 seconds
Started Jul 01 11:15:13 AM PDT 24
Finished Jul 01 11:23:18 AM PDT 24
Peak memory 201924 kb
Host smart-f0813687-e797-435a-9c4a-62bedeba281c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311412927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2311412927
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4013422409
Short name T556
Test name
Test status
Simulation time 128883213604 ps
CPU time 633.91 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:25:18 AM PDT 24
Peak memory 202196 kb
Host smart-6071581b-8d87-40e1-9e60-72703ab2be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013422409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4013422409
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.850444557
Short name T366
Test name
Test status
Simulation time 40851001498 ps
CPU time 93.07 seconds
Started Jul 01 11:15:03 AM PDT 24
Finished Jul 01 11:16:37 AM PDT 24
Peak memory 201684 kb
Host smart-48dcf29a-9008-4f63-a44c-7ba45e3273e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850444557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.850444557
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1589843186
Short name T171
Test name
Test status
Simulation time 2875953884 ps
CPU time 6.97 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:14:48 AM PDT 24
Peak memory 201636 kb
Host smart-065e8ca1-3e45-4167-8b5e-300b642b7d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589843186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1589843186
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3644549009
Short name T741
Test name
Test status
Simulation time 5679079100 ps
CPU time 7.97 seconds
Started Jul 01 11:14:37 AM PDT 24
Finished Jul 01 11:14:46 AM PDT 24
Peak memory 201632 kb
Host smart-b6048d31-e13f-4212-aa30-84fca80cde48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644549009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3644549009
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2468064740
Short name T404
Test name
Test status
Simulation time 164722469062 ps
CPU time 174.86 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:17:41 AM PDT 24
Peak memory 201820 kb
Host smart-401a2a8e-5487-44f7-8cc3-49efc4c349a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468064740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2468064740
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2860021015
Short name T359
Test name
Test status
Simulation time 316079224 ps
CPU time 0.76 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:14:49 AM PDT 24
Peak memory 201568 kb
Host smart-8d728afd-2f85-41b1-a650-e3a22c232b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860021015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2860021015
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.233738693
Short name T127
Test name
Test status
Simulation time 493224641444 ps
CPU time 1130.44 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:33:32 AM PDT 24
Peak memory 201916 kb
Host smart-4a7640e5-0224-4eb6-b11b-3211ca34ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233738693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.233738693
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2136850943
Short name T631
Test name
Test status
Simulation time 160345950492 ps
CPU time 292.59 seconds
Started Jul 01 11:14:38 AM PDT 24
Finished Jul 01 11:19:32 AM PDT 24
Peak memory 201884 kb
Host smart-2a82bd52-54c8-4ad1-89b7-8259d7676578
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136850943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2136850943
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1282109581
Short name T504
Test name
Test status
Simulation time 165273606100 ps
CPU time 386.02 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:21:13 AM PDT 24
Peak memory 201892 kb
Host smart-a1dcd982-63f9-419d-abfd-73e9c3f6a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282109581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1282109581
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2652549698
Short name T479
Test name
Test status
Simulation time 331405014446 ps
CPU time 807.58 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:28:15 AM PDT 24
Peak memory 201928 kb
Host smart-5d85c97f-514f-4b5a-8a63-4ee0344567c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652549698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2652549698
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2775103554
Short name T468
Test name
Test status
Simulation time 382814486778 ps
CPU time 222.12 seconds
Started Jul 01 11:15:07 AM PDT 24
Finished Jul 01 11:18:50 AM PDT 24
Peak memory 201848 kb
Host smart-9cafe85f-dc4c-47c2-bdbe-ffc2e27ed342
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775103554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2775103554
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1040778425
Short name T644
Test name
Test status
Simulation time 102677105568 ps
CPU time 332.02 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:20:19 AM PDT 24
Peak memory 202284 kb
Host smart-1753e83b-634d-4b51-8c30-fa17ccae2f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040778425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1040778425
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3031818847
Short name T609
Test name
Test status
Simulation time 27299829226 ps
CPU time 25.46 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:15:06 AM PDT 24
Peak memory 201648 kb
Host smart-1e34f7f0-4671-4cba-aae4-15ac2387140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031818847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3031818847
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2255140872
Short name T355
Test name
Test status
Simulation time 5424624444 ps
CPU time 6.75 seconds
Started Jul 01 11:15:02 AM PDT 24
Finished Jul 01 11:15:09 AM PDT 24
Peak memory 201660 kb
Host smart-08ef36e7-b6ad-4ea7-8c57-537bac24b628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255140872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2255140872
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.134674608
Short name T42
Test name
Test status
Simulation time 5833450342 ps
CPU time 13.39 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:14:57 AM PDT 24
Peak memory 201704 kb
Host smart-4fe8e289-b4bd-4fad-9157-411191bf27e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134674608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.134674608
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1346366025
Short name T623
Test name
Test status
Simulation time 201860712915 ps
CPU time 121.72 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:16:47 AM PDT 24
Peak memory 201800 kb
Host smart-fd2de5aa-66a0-4c4c-bb68-79e40e53694b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346366025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1346366025
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1812721809
Short name T43
Test name
Test status
Simulation time 94439697423 ps
CPU time 173.19 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:17:34 AM PDT 24
Peak memory 210160 kb
Host smart-e96dba6f-cb25-4d5b-a718-6cc108971da3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812721809 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1812721809
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3681274672
Short name T665
Test name
Test status
Simulation time 532715814 ps
CPU time 0.94 seconds
Started Jul 01 11:14:58 AM PDT 24
Finished Jul 01 11:15:00 AM PDT 24
Peak memory 201644 kb
Host smart-11dbc5bb-bd8a-4cc8-bca1-ed89f07b2852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681274672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3681274672
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2867076512
Short name T646
Test name
Test status
Simulation time 492905794618 ps
CPU time 198.15 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:18:04 AM PDT 24
Peak memory 201856 kb
Host smart-732b9ccc-6a87-4a2e-9bfc-5e98bb369787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867076512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2867076512
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2393790210
Short name T77
Test name
Test status
Simulation time 161369789756 ps
CPU time 37.4 seconds
Started Jul 01 11:14:48 AM PDT 24
Finished Jul 01 11:15:27 AM PDT 24
Peak memory 201848 kb
Host smart-6e0bc9ab-3686-4130-9ae5-1d18932c91e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393790210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2393790210
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1371079672
Short name T311
Test name
Test status
Simulation time 163338389465 ps
CPU time 383.97 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:21:10 AM PDT 24
Peak memory 201868 kb
Host smart-ecd05eab-7bb0-4445-b397-1ef8e45eb665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371079672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1371079672
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2834118642
Short name T384
Test name
Test status
Simulation time 320767108113 ps
CPU time 371.78 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:20:58 AM PDT 24
Peak memory 201852 kb
Host smart-824e9ea1-fbd7-474b-bf7c-cefe970a29f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834118642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2834118642
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3552764338
Short name T217
Test name
Test status
Simulation time 392272522233 ps
CPU time 478.15 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:23:05 AM PDT 24
Peak memory 201876 kb
Host smart-4ac74c28-0733-4a8f-a140-311c87f0fbf7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552764338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3552764338
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.924032313
Short name T368
Test name
Test status
Simulation time 601930671681 ps
CPU time 377.25 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:21:05 AM PDT 24
Peak memory 201828 kb
Host smart-d72b8f76-aaba-4a30-89e6-605f256b3086
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924032313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.924032313
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4167309542
Short name T793
Test name
Test status
Simulation time 107630316089 ps
CPU time 329.95 seconds
Started Jul 01 11:15:15 AM PDT 24
Finished Jul 01 11:20:49 AM PDT 24
Peak memory 202188 kb
Host smart-39483304-590f-4fd5-bde2-be7ad9aa008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167309542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4167309542
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.121658669
Short name T613
Test name
Test status
Simulation time 25676251099 ps
CPU time 16.6 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:15:03 AM PDT 24
Peak memory 201692 kb
Host smart-bdae844c-1acd-4404-a496-ace3009fe8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121658669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.121658669
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3850794051
Short name T547
Test name
Test status
Simulation time 5131003358 ps
CPU time 6.56 seconds
Started Jul 01 11:14:43 AM PDT 24
Finished Jul 01 11:14:51 AM PDT 24
Peak memory 201648 kb
Host smart-9a99f06f-abd2-4b33-ae90-f014ea41078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850794051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3850794051
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4021034867
Short name T693
Test name
Test status
Simulation time 5737448756 ps
CPU time 7.79 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:14:56 AM PDT 24
Peak memory 201660 kb
Host smart-ad717e8a-9577-42a2-905d-994dc34d632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021034867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4021034867
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.661873525
Short name T751
Test name
Test status
Simulation time 536724751021 ps
CPU time 916.11 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:30:03 AM PDT 24
Peak memory 210356 kb
Host smart-865d5414-4869-4d41-bf0a-7d18c659906e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661873525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
661873525
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3450818094
Short name T766
Test name
Test status
Simulation time 412901147270 ps
CPU time 456.38 seconds
Started Jul 01 11:15:04 AM PDT 24
Finished Jul 01 11:22:42 AM PDT 24
Peak memory 210504 kb
Host smart-dc57534e-2717-4596-b62e-5a43bace5f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450818094 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3450818094
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1611653042
Short name T364
Test name
Test status
Simulation time 375788484 ps
CPU time 0.79 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:14:04 AM PDT 24
Peak memory 201532 kb
Host smart-15e5aca3-f4be-451b-8d58-dd85a018a6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611653042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1611653042
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1064680452
Short name T594
Test name
Test status
Simulation time 161116001653 ps
CPU time 170.6 seconds
Started Jul 01 11:14:27 AM PDT 24
Finished Jul 01 11:17:18 AM PDT 24
Peak memory 201876 kb
Host smart-3c5889e3-e2c2-468d-a0d8-3c98650fbe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064680452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1064680452
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3402776437
Short name T671
Test name
Test status
Simulation time 161734479428 ps
CPU time 102.37 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:15:43 AM PDT 24
Peak memory 201848 kb
Host smart-64d7afe7-5333-4724-b4d3-6895493a6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402776437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3402776437
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3224025713
Short name T499
Test name
Test status
Simulation time 166058279118 ps
CPU time 47.5 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:14:49 AM PDT 24
Peak memory 201824 kb
Host smart-913d1ccf-65c4-44ca-8370-76a21579272e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224025713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3224025713
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1461104847
Short name T685
Test name
Test status
Simulation time 164416505312 ps
CPU time 384.79 seconds
Started Jul 01 11:14:04 AM PDT 24
Finished Jul 01 11:20:30 AM PDT 24
Peak memory 201808 kb
Host smart-aed73070-475e-42f8-9c9d-6a7ff19c86bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461104847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1461104847
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.824483579
Short name T772
Test name
Test status
Simulation time 320743671300 ps
CPU time 136.58 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:16:18 AM PDT 24
Peak memory 201760 kb
Host smart-428e9dcd-5078-438f-a4b5-c671a91455f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=824483579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.824483579
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2406049107
Short name T132
Test name
Test status
Simulation time 612480571955 ps
CPU time 344.16 seconds
Started Jul 01 11:14:26 AM PDT 24
Finished Jul 01 11:20:11 AM PDT 24
Peak memory 201812 kb
Host smart-1aa4f6b1-0aa5-47b4-8a68-a202ca5688c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406049107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2406049107
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2874197586
Short name T389
Test name
Test status
Simulation time 213361458947 ps
CPU time 423.5 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:21:07 AM PDT 24
Peak memory 201868 kb
Host smart-d8859e8c-308a-4c56-9abb-3677931d0c33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874197586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2874197586
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.872495235
Short name T598
Test name
Test status
Simulation time 67174629962 ps
CPU time 228.11 seconds
Started Jul 01 11:14:01 AM PDT 24
Finished Jul 01 11:17:50 AM PDT 24
Peak memory 202232 kb
Host smart-38c14679-3cb6-402d-bd2a-585e50d3cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872495235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.872495235
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2089402089
Short name T91
Test name
Test status
Simulation time 34383641342 ps
CPU time 67.4 seconds
Started Jul 01 11:14:03 AM PDT 24
Finished Jul 01 11:15:12 AM PDT 24
Peak memory 201696 kb
Host smart-8f822059-ecf1-4c74-a320-b6c319af2f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089402089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2089402089
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.457425302
Short name T566
Test name
Test status
Simulation time 3339716389 ps
CPU time 7.48 seconds
Started Jul 01 11:14:01 AM PDT 24
Finished Jul 01 11:14:10 AM PDT 24
Peak memory 201688 kb
Host smart-a6b7eb75-9837-4b1a-b6d2-90a38bfde712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457425302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.457425302
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1557338678
Short name T62
Test name
Test status
Simulation time 4004617428 ps
CPU time 4.76 seconds
Started Jul 01 11:14:03 AM PDT 24
Finished Jul 01 11:14:09 AM PDT 24
Peak memory 217136 kb
Host smart-f59534f3-0b3b-4530-bd8e-38dafe4621b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557338678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1557338678
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2597098594
Short name T687
Test name
Test status
Simulation time 6040561289 ps
CPU time 3.01 seconds
Started Jul 01 11:14:13 AM PDT 24
Finished Jul 01 11:14:16 AM PDT 24
Peak memory 201616 kb
Host smart-1eee6853-4e75-44a8-b3f0-a76f4c7e4503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597098594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2597098594
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4128939393
Short name T752
Test name
Test status
Simulation time 230647459245 ps
CPU time 347.99 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:19:51 AM PDT 24
Peak memory 201832 kb
Host smart-05232d0b-b3fd-4608-9491-c8a3315655f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128939393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4128939393
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.752092699
Short name T391
Test name
Test status
Simulation time 359566924 ps
CPU time 1.34 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:14:53 AM PDT 24
Peak memory 201608 kb
Host smart-631dc158-5ab4-444e-b626-2f7266d99bef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752092699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.752092699
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3484184623
Short name T601
Test name
Test status
Simulation time 166380830495 ps
CPU time 59.76 seconds
Started Jul 01 11:15:03 AM PDT 24
Finished Jul 01 11:16:04 AM PDT 24
Peak memory 201788 kb
Host smart-e47c360f-09a1-4065-afe5-078ccac5fe78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484184623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3484184623
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.488202275
Short name T774
Test name
Test status
Simulation time 561113443394 ps
CPU time 281.5 seconds
Started Jul 01 11:14:44 AM PDT 24
Finished Jul 01 11:19:28 AM PDT 24
Peak memory 201896 kb
Host smart-2b9625a6-757f-49d5-9fe3-1e0ffccbefcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488202275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.488202275
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3644803850
Short name T225
Test name
Test status
Simulation time 167589754109 ps
CPU time 107.74 seconds
Started Jul 01 11:15:14 AM PDT 24
Finished Jul 01 11:17:04 AM PDT 24
Peak memory 201772 kb
Host smart-2c1843a8-0617-4b48-ba0f-f8fafc5761e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644803850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3644803850
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3565746398
Short name T660
Test name
Test status
Simulation time 486572489500 ps
CPU time 534.75 seconds
Started Jul 01 11:14:54 AM PDT 24
Finished Jul 01 11:23:51 AM PDT 24
Peak memory 201868 kb
Host smart-8f2db66e-10ce-45b2-9439-6e4c7cfd134f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565746398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3565746398
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1482000471
Short name T83
Test name
Test status
Simulation time 490527159850 ps
CPU time 591.74 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:24:44 AM PDT 24
Peak memory 201904 kb
Host smart-0c4d9dfc-b529-4cca-8fda-caf3d8eb7d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482000471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1482000471
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3331909641
Short name T488
Test name
Test status
Simulation time 329956460989 ps
CPU time 154.45 seconds
Started Jul 01 11:14:47 AM PDT 24
Finished Jul 01 11:17:23 AM PDT 24
Peak memory 201864 kb
Host smart-20dccab4-196d-4352-8e11-8ea5bc898922
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331909641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3331909641
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2865845352
Short name T699
Test name
Test status
Simulation time 199208609801 ps
CPU time 223.1 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:18:35 AM PDT 24
Peak memory 201856 kb
Host smart-2e603ef6-6d62-4b1f-b27e-a7f049ebbf6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865845352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2865845352
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3922644071
Short name T458
Test name
Test status
Simulation time 139759709355 ps
CPU time 490.3 seconds
Started Jul 01 11:14:51 AM PDT 24
Finished Jul 01 11:23:04 AM PDT 24
Peak memory 202164 kb
Host smart-7c3fd0f0-002f-47c3-bdb2-24e73a9171cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922644071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3922644071
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1068855282
Short name T587
Test name
Test status
Simulation time 34994875850 ps
CPU time 42.95 seconds
Started Jul 01 11:15:09 AM PDT 24
Finished Jul 01 11:15:54 AM PDT 24
Peak memory 201880 kb
Host smart-3f286566-f55b-4586-a9ab-430b46bd92a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068855282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1068855282
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2675258559
Short name T683
Test name
Test status
Simulation time 4778102919 ps
CPU time 11.71 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:14:58 AM PDT 24
Peak memory 201680 kb
Host smart-6fd9c707-c655-4b11-8ac9-f158be678e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675258559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2675258559
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3478562069
Short name T162
Test name
Test status
Simulation time 5910930560 ps
CPU time 4.55 seconds
Started Jul 01 11:14:51 AM PDT 24
Finished Jul 01 11:14:58 AM PDT 24
Peak memory 201684 kb
Host smart-541ff943-9f04-4c82-9e7b-f59eeaf3d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478562069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3478562069
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2237101678
Short name T554
Test name
Test status
Simulation time 137738474979 ps
CPU time 448.95 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:22:17 AM PDT 24
Peak memory 210364 kb
Host smart-372c2791-343d-49db-9404-254329adc3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237101678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2237101678
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4003068975
Short name T39
Test name
Test status
Simulation time 81285122898 ps
CPU time 96.28 seconds
Started Jul 01 11:15:17 AM PDT 24
Finished Jul 01 11:16:58 AM PDT 24
Peak memory 210568 kb
Host smart-4e692fbc-6586-4e08-9d16-b10555321e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003068975 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4003068975
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2227919023
Short name T783
Test name
Test status
Simulation time 334797189 ps
CPU time 0.74 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:14:54 AM PDT 24
Peak memory 201640 kb
Host smart-cd90e276-05f8-46f3-923d-204161f0a551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227919023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2227919023
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.510293641
Short name T290
Test name
Test status
Simulation time 683183963175 ps
CPU time 428.49 seconds
Started Jul 01 11:14:52 AM PDT 24
Finished Jul 01 11:22:05 AM PDT 24
Peak memory 201752 kb
Host smart-2bec9bf2-705f-429c-9bb0-d1e8dc33462b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510293641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.510293641
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2685545674
Short name T95
Test name
Test status
Simulation time 488730637746 ps
CPU time 1071.65 seconds
Started Jul 01 11:14:51 AM PDT 24
Finished Jul 01 11:32:45 AM PDT 24
Peak memory 201876 kb
Host smart-c236378b-5169-4b86-83c7-c489155acada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685545674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2685545674
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3258864004
Short name T664
Test name
Test status
Simulation time 330452381824 ps
CPU time 52.24 seconds
Started Jul 01 11:14:57 AM PDT 24
Finished Jul 01 11:15:50 AM PDT 24
Peak memory 201752 kb
Host smart-be8137d8-c622-415a-a140-8ebc1f742d6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258864004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3258864004
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2550248902
Short name T323
Test name
Test status
Simulation time 507373360589 ps
CPU time 1163.93 seconds
Started Jul 01 11:15:14 AM PDT 24
Finished Jul 01 11:34:41 AM PDT 24
Peak memory 201944 kb
Host smart-4e262e75-2ab1-4550-90b6-fdec0c864129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550248902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2550248902
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1633551063
Short name T480
Test name
Test status
Simulation time 162514925796 ps
CPU time 372 seconds
Started Jul 01 11:14:52 AM PDT 24
Finished Jul 01 11:21:06 AM PDT 24
Peak memory 201832 kb
Host smart-b1405836-813f-433f-a800-bd448fac9bb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633551063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1633551063
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4033877496
Short name T357
Test name
Test status
Simulation time 401671180725 ps
CPU time 243.32 seconds
Started Jul 01 11:14:53 AM PDT 24
Finished Jul 01 11:18:59 AM PDT 24
Peak memory 201856 kb
Host smart-eb5c7255-b452-4e2d-8a02-db842a36f0c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033877496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4033877496
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1823168323
Short name T573
Test name
Test status
Simulation time 61999694569 ps
CPU time 334.09 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:20:26 AM PDT 24
Peak memory 202176 kb
Host smart-1f62d68a-90b5-4587-b226-c32bc8401b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823168323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1823168323
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1538246383
Short name T363
Test name
Test status
Simulation time 21274733227 ps
CPU time 3.31 seconds
Started Jul 01 11:14:53 AM PDT 24
Finished Jul 01 11:14:59 AM PDT 24
Peak memory 201680 kb
Host smart-fc1d8d67-212f-41ae-97f7-598bed2b5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538246383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1538246383
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.441962836
Short name T698
Test name
Test status
Simulation time 3034772278 ps
CPU time 2.33 seconds
Started Jul 01 11:15:15 AM PDT 24
Finished Jul 01 11:15:21 AM PDT 24
Peak memory 201616 kb
Host smart-74bc9f7e-218e-4bc1-8585-f7fc7ada09ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441962836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.441962836
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.30739219
Short name T348
Test name
Test status
Simulation time 5923438126 ps
CPU time 15.21 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:15:06 AM PDT 24
Peak memory 201676 kb
Host smart-7e830953-c1eb-425b-bf6c-692cd30ef974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30739219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.30739219
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.182907594
Short name T68
Test name
Test status
Simulation time 552604476 ps
CPU time 0.87 seconds
Started Jul 01 11:14:55 AM PDT 24
Finished Jul 01 11:14:58 AM PDT 24
Peak memory 201620 kb
Host smart-20d3d9ac-cbe2-43df-b9e5-2f9b90aa91f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182907594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.182907594
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.341628633
Short name T240
Test name
Test status
Simulation time 178513445922 ps
CPU time 44.1 seconds
Started Jul 01 11:14:57 AM PDT 24
Finished Jul 01 11:15:43 AM PDT 24
Peak memory 201944 kb
Host smart-58ac18c6-0268-4973-a864-5ec2a2b782a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341628633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.341628633
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4073018140
Short name T686
Test name
Test status
Simulation time 264054710650 ps
CPU time 156.64 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:17:44 AM PDT 24
Peak memory 201892 kb
Host smart-904f59fb-f9a8-4576-bcaa-180b18ffdda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073018140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4073018140
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4209697807
Short name T307
Test name
Test status
Simulation time 165331172154 ps
CPU time 376.13 seconds
Started Jul 01 11:14:56 AM PDT 24
Finished Jul 01 11:21:13 AM PDT 24
Peak memory 201876 kb
Host smart-cfbab3ee-3908-4989-a070-c2bb7f6c85fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209697807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4209697807
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2405683616
Short name T747
Test name
Test status
Simulation time 330195476451 ps
CPU time 155.49 seconds
Started Jul 01 11:15:01 AM PDT 24
Finished Jul 01 11:17:38 AM PDT 24
Peak memory 201872 kb
Host smart-95c1b0c8-93f9-4494-99c4-58acae07132e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405683616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2405683616
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2273821120
Short name T612
Test name
Test status
Simulation time 164279671869 ps
CPU time 360.22 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:20:53 AM PDT 24
Peak memory 201944 kb
Host smart-3736c793-1376-4772-99a8-a9db8138f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273821120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2273821120
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2231691286
Short name T605
Test name
Test status
Simulation time 329983892064 ps
CPU time 708.05 seconds
Started Jul 01 11:14:51 AM PDT 24
Finished Jul 01 11:26:42 AM PDT 24
Peak memory 201748 kb
Host smart-607fb08a-1fde-4f15-8198-51d140aa6056
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231691286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2231691286
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2367941146
Short name T320
Test name
Test status
Simulation time 368406495018 ps
CPU time 423.1 seconds
Started Jul 01 11:14:53 AM PDT 24
Finished Jul 01 11:21:58 AM PDT 24
Peak memory 201920 kb
Host smart-02b5f9cf-e390-45a9-a512-6378e3ba943f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367941146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2367941146
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1810723537
Short name T407
Test name
Test status
Simulation time 397883530800 ps
CPU time 224.22 seconds
Started Jul 01 11:14:50 AM PDT 24
Finished Jul 01 11:18:35 AM PDT 24
Peak memory 201856 kb
Host smart-b2f64060-138c-4956-8075-e82732114af5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810723537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1810723537
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2870869954
Short name T775
Test name
Test status
Simulation time 84323543424 ps
CPU time 317.72 seconds
Started Jul 01 11:14:52 AM PDT 24
Finished Jul 01 11:20:12 AM PDT 24
Peak memory 202208 kb
Host smart-ddb5ebdc-cd03-4a6b-a68a-b9210bc85c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870869954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2870869954
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.412954150
Short name T572
Test name
Test status
Simulation time 44395998967 ps
CPU time 103.5 seconds
Started Jul 01 11:14:52 AM PDT 24
Finished Jul 01 11:16:38 AM PDT 24
Peak memory 201680 kb
Host smart-67424c2e-9617-4534-9085-7fae46074f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412954150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.412954150
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1794587400
Short name T788
Test name
Test status
Simulation time 4375196624 ps
CPU time 8.7 seconds
Started Jul 01 11:14:53 AM PDT 24
Finished Jul 01 11:15:04 AM PDT 24
Peak memory 201676 kb
Host smart-40a91c00-2b5e-4168-884e-8911c663d65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794587400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1794587400
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1046615466
Short name T369
Test name
Test status
Simulation time 5798135055 ps
CPU time 13.41 seconds
Started Jul 01 11:15:09 AM PDT 24
Finished Jul 01 11:15:24 AM PDT 24
Peak memory 201636 kb
Host smart-193ae796-374e-4bbd-9ef3-6d2288f9c2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046615466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1046615466
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1631412117
Short name T33
Test name
Test status
Simulation time 273892366680 ps
CPU time 934.82 seconds
Started Jul 01 11:14:52 AM PDT 24
Finished Jul 01 11:30:29 AM PDT 24
Peak memory 210424 kb
Host smart-fbd414e0-33a7-494e-a886-d8c116e208ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631412117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1631412117
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3839495889
Short name T317
Test name
Test status
Simulation time 17527240781 ps
CPU time 36.36 seconds
Started Jul 01 11:14:51 AM PDT 24
Finished Jul 01 11:15:30 AM PDT 24
Peak memory 201972 kb
Host smart-2e30b9c9-afa2-4592-ba27-6fb282a011ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839495889 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3839495889
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.229362961
Short name T13
Test name
Test status
Simulation time 556488736 ps
CPU time 0.79 seconds
Started Jul 01 11:14:57 AM PDT 24
Finished Jul 01 11:14:58 AM PDT 24
Peak memory 201624 kb
Host smart-8de3727d-1c36-4b5c-b8f5-dd16c069b19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229362961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.229362961
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3211625089
Short name T196
Test name
Test status
Simulation time 507679170108 ps
CPU time 741.05 seconds
Started Jul 01 11:14:55 AM PDT 24
Finished Jul 01 11:27:18 AM PDT 24
Peak memory 201924 kb
Host smart-e2f5c316-36e5-410c-92c6-401500aec273
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211625089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3211625089
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.319141554
Short name T650
Test name
Test status
Simulation time 506582392766 ps
CPU time 324.76 seconds
Started Jul 01 11:14:56 AM PDT 24
Finished Jul 01 11:20:22 AM PDT 24
Peak memory 201968 kb
Host smart-bfff5c54-6414-4084-b678-269bc2201efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319141554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.319141554
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.742681563
Short name T165
Test name
Test status
Simulation time 319392324870 ps
CPU time 758.09 seconds
Started Jul 01 11:15:15 AM PDT 24
Finished Jul 01 11:27:56 AM PDT 24
Peak memory 201892 kb
Host smart-91e4b803-dfba-4048-b2a6-28923975b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742681563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.742681563
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1848522287
Short name T734
Test name
Test status
Simulation time 328692983698 ps
CPU time 784.36 seconds
Started Jul 01 11:14:55 AM PDT 24
Finished Jul 01 11:28:01 AM PDT 24
Peak memory 201828 kb
Host smart-30c835ac-51fc-4fa6-8ff0-15a32b563fa0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848522287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1848522287
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1462221212
Short name T552
Test name
Test status
Simulation time 164604593005 ps
CPU time 398.74 seconds
Started Jul 01 11:14:54 AM PDT 24
Finished Jul 01 11:21:35 AM PDT 24
Peak memory 201904 kb
Host smart-810b7b74-c5aa-4981-8321-78b4a8313871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462221212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1462221212
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1299019736
Short name T443
Test name
Test status
Simulation time 486178488816 ps
CPU time 526.36 seconds
Started Jul 01 11:14:54 AM PDT 24
Finished Jul 01 11:23:42 AM PDT 24
Peak memory 201876 kb
Host smart-4a6f21a9-431a-4ed7-a042-20e055b570d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299019736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1299019736
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3866412442
Short name T288
Test name
Test status
Simulation time 562095438031 ps
CPU time 1204.97 seconds
Started Jul 01 11:14:57 AM PDT 24
Finished Jul 01 11:35:03 AM PDT 24
Peak memory 201872 kb
Host smart-9b4026a4-bbb2-4dd4-91fd-f2a2f29f9920
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866412442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3866412442
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2859229734
Short name T704
Test name
Test status
Simulation time 619242355029 ps
CPU time 363.72 seconds
Started Jul 01 11:15:05 AM PDT 24
Finished Jul 01 11:21:10 AM PDT 24
Peak memory 201852 kb
Host smart-693c9fb8-7c9f-49d9-b9e4-53418333bf46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859229734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2859229734
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.336677116
Short name T47
Test name
Test status
Simulation time 95520951384 ps
CPU time 443.76 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:22:31 AM PDT 24
Peak memory 202272 kb
Host smart-ab9dfd19-31c9-4e1a-b3c9-3fe0c9a1f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336677116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.336677116
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3121359662
Short name T30
Test name
Test status
Simulation time 21809474571 ps
CPU time 11.87 seconds
Started Jul 01 11:15:10 AM PDT 24
Finished Jul 01 11:15:23 AM PDT 24
Peak memory 201688 kb
Host smart-645e2a12-c992-4924-8cd2-7a84c8221753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121359662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3121359662
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3679899407
Short name T451
Test name
Test status
Simulation time 3302738201 ps
CPU time 7.96 seconds
Started Jul 01 11:15:15 AM PDT 24
Finished Jul 01 11:15:26 AM PDT 24
Peak memory 201596 kb
Host smart-de10f5df-df3a-4886-8e68-edf6cb1ad8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679899407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3679899407
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3539569614
Short name T376
Test name
Test status
Simulation time 5677653895 ps
CPU time 13.41 seconds
Started Jul 01 11:14:53 AM PDT 24
Finished Jul 01 11:15:09 AM PDT 24
Peak memory 201676 kb
Host smart-9afd0ec3-30d7-460e-95d8-3839757ec658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539569614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3539569614
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2104531378
Short name T322
Test name
Test status
Simulation time 322579818385 ps
CPU time 718.56 seconds
Started Jul 01 11:15:12 AM PDT 24
Finished Jul 01 11:27:12 AM PDT 24
Peak memory 201788 kb
Host smart-38683f55-c93c-4e78-a760-1c0cc57a8193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104531378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2104531378
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1397615256
Short name T268
Test name
Test status
Simulation time 179045625998 ps
CPU time 308.18 seconds
Started Jul 01 11:15:03 AM PDT 24
Finished Jul 01 11:20:12 AM PDT 24
Peak memory 210432 kb
Host smart-18cfad22-7c07-4937-a19c-f99a30e3eacd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397615256 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1397615256
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2180181487
Short name T743
Test name
Test status
Simulation time 454337678 ps
CPU time 0.83 seconds
Started Jul 01 11:15:23 AM PDT 24
Finished Jul 01 11:15:28 AM PDT 24
Peak memory 201624 kb
Host smart-56e2ca19-97a9-4dd0-9388-111f0824814a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180181487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2180181487
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2366317491
Short name T224
Test name
Test status
Simulation time 162018030333 ps
CPU time 3.97 seconds
Started Jul 01 11:15:18 AM PDT 24
Finished Jul 01 11:15:26 AM PDT 24
Peak memory 201784 kb
Host smart-7d2c880d-9d22-4708-8c43-181523768dc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366317491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2366317491
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3488592989
Short name T272
Test name
Test status
Simulation time 534171235073 ps
CPU time 1138.77 seconds
Started Jul 01 11:14:59 AM PDT 24
Finished Jul 01 11:33:59 AM PDT 24
Peak memory 201848 kb
Host smart-41eebf00-4c5e-43fb-a7b6-457f6a57a0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488592989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3488592989
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2089004028
Short name T519
Test name
Test status
Simulation time 165963449180 ps
CPU time 191.62 seconds
Started Jul 01 11:15:18 AM PDT 24
Finished Jul 01 11:18:34 AM PDT 24
Peak memory 201884 kb
Host smart-79b51406-5274-4c94-ad1c-09b91694ab4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089004028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2089004028
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1134407761
Short name T675
Test name
Test status
Simulation time 328886151707 ps
CPU time 761.19 seconds
Started Jul 01 11:15:15 AM PDT 24
Finished Jul 01 11:27:59 AM PDT 24
Peak memory 201768 kb
Host smart-ce906acc-810b-4d44-a050-695914802674
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134407761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1134407761
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1674765258
Short name T719
Test name
Test status
Simulation time 495177063219 ps
CPU time 690.99 seconds
Started Jul 01 11:15:13 AM PDT 24
Finished Jul 01 11:26:46 AM PDT 24
Peak memory 201828 kb
Host smart-18d66640-79b7-48a6-9f7e-ca3ce419b9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674765258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1674765258
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.849159606
Short name T561
Test name
Test status
Simulation time 493153321996 ps
CPU time 528.12 seconds
Started Jul 01 11:15:11 AM PDT 24
Finished Jul 01 11:24:00 AM PDT 24
Peak memory 201860 kb
Host smart-160df77f-b837-4962-9680-abb8db7995b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=849159606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.849159606
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2232649086
Short name T255
Test name
Test status
Simulation time 188489768877 ps
CPU time 110.09 seconds
Started Jul 01 11:15:00 AM PDT 24
Finished Jul 01 11:16:51 AM PDT 24
Peak memory 201836 kb
Host smart-a99e7fce-c78b-49ec-b86f-71216dea99fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232649086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2232649086
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2700714724
Short name T560
Test name
Test status
Simulation time 385287862616 ps
CPU time 227.07 seconds
Started Jul 01 11:15:19 AM PDT 24
Finished Jul 01 11:19:11 AM PDT 24
Peak memory 201840 kb
Host smart-b5213515-d6fa-4cd3-8bdd-5b05da0d0a58
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700714724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2700714724
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3378262024
Short name T721
Test name
Test status
Simulation time 101667695601 ps
CPU time 470.31 seconds
Started Jul 01 11:15:22 AM PDT 24
Finished Jul 01 11:23:17 AM PDT 24
Peak memory 202188 kb
Host smart-8d5c9e29-0baa-4687-87a2-1c3ae56ca092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378262024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3378262024
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3723985223
Short name T428
Test name
Test status
Simulation time 29037285690 ps
CPU time 15.8 seconds
Started Jul 01 11:15:12 AM PDT 24
Finished Jul 01 11:15:30 AM PDT 24
Peak memory 201688 kb
Host smart-f71aa5ad-4075-4edb-a53c-b68c7d52ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723985223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3723985223
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2421846187
Short name T438
Test name
Test status
Simulation time 3742403781 ps
CPU time 2.69 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:15:10 AM PDT 24
Peak memory 201600 kb
Host smart-186e4f18-5184-4271-93a1-c6ed18092a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421846187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2421846187
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1052240515
Short name T475
Test name
Test status
Simulation time 5726945920 ps
CPU time 2.91 seconds
Started Jul 01 11:15:12 AM PDT 24
Finished Jul 01 11:15:16 AM PDT 24
Peak memory 201600 kb
Host smart-16b1cf8a-a325-4105-b6e2-56c9edb02cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052240515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1052240515
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3394088033
Short name T677
Test name
Test status
Simulation time 201474354658 ps
CPU time 114.42 seconds
Started Jul 01 11:15:02 AM PDT 24
Finished Jul 01 11:16:58 AM PDT 24
Peak memory 201864 kb
Host smart-02bc8bf7-f01d-44e0-a22c-12fd8b06d2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394088033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3394088033
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1609553674
Short name T597
Test name
Test status
Simulation time 148060605073 ps
CPU time 364.62 seconds
Started Jul 01 11:15:00 AM PDT 24
Finished Jul 01 11:21:05 AM PDT 24
Peak memory 218580 kb
Host smart-89709892-8c19-4d3f-b5a8-49af03979494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609553674 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1609553674
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3558635940
Short name T542
Test name
Test status
Simulation time 477190874 ps
CPU time 1.19 seconds
Started Jul 01 11:15:27 AM PDT 24
Finished Jul 01 11:15:35 AM PDT 24
Peak memory 201640 kb
Host smart-5efe9c09-f9f6-4497-8eeb-dd44f2fa8baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558635940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3558635940
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.912639334
Short name T277
Test name
Test status
Simulation time 365961642224 ps
CPU time 791.65 seconds
Started Jul 01 11:15:05 AM PDT 24
Finished Jul 01 11:28:18 AM PDT 24
Peak memory 201924 kb
Host smart-bf4d7b27-e3fb-4264-8963-bcaa47091fc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912639334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.912639334
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.339420941
Short name T604
Test name
Test status
Simulation time 486574732475 ps
CPU time 1044.54 seconds
Started Jul 01 11:14:59 AM PDT 24
Finished Jul 01 11:32:24 AM PDT 24
Peak memory 201884 kb
Host smart-3a2166b6-2b77-4082-bc67-fa866d947d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339420941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.339420941
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4066539522
Short name T553
Test name
Test status
Simulation time 484546302886 ps
CPU time 226.59 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:18:54 AM PDT 24
Peak memory 201764 kb
Host smart-462c2624-7e6a-4f8a-8144-4dbdb7856665
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066539522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4066539522
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3142996251
Short name T192
Test name
Test status
Simulation time 500837765523 ps
CPU time 264.72 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:19:32 AM PDT 24
Peak memory 201856 kb
Host smart-da8b7382-0b03-4aad-81de-ba5e4520541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142996251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3142996251
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3120096052
Short name T347
Test name
Test status
Simulation time 504653240065 ps
CPU time 1087.48 seconds
Started Jul 01 11:15:01 AM PDT 24
Finished Jul 01 11:33:10 AM PDT 24
Peak memory 201896 kb
Host smart-12b01456-ccd4-4fe8-918e-8e3c04d4bcf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120096052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3120096052
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1599663502
Short name T326
Test name
Test status
Simulation time 592910448522 ps
CPU time 291.69 seconds
Started Jul 01 11:15:06 AM PDT 24
Finished Jul 01 11:19:59 AM PDT 24
Peak memory 201924 kb
Host smart-dcd6c844-fd5a-434e-8a16-89ad1cbb5c68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599663502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1599663502
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.628487205
Short name T476
Test name
Test status
Simulation time 379591761796 ps
CPU time 454.22 seconds
Started Jul 01 11:15:27 AM PDT 24
Finished Jul 01 11:23:08 AM PDT 24
Peak memory 201936 kb
Host smart-518783c3-36e2-415e-a24c-70b2cb541089
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628487205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.628487205
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.159887120
Short name T432
Test name
Test status
Simulation time 23058939623 ps
CPU time 56.03 seconds
Started Jul 01 11:15:07 AM PDT 24
Finished Jul 01 11:16:04 AM PDT 24
Peak memory 201636 kb
Host smart-889eb77d-819b-42ba-adcb-e4f556f73d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159887120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.159887120
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2364551852
Short name T760
Test name
Test status
Simulation time 3494960672 ps
CPU time 2.82 seconds
Started Jul 01 11:15:16 AM PDT 24
Finished Jul 01 11:15:23 AM PDT 24
Peak memory 201664 kb
Host smart-4861587d-8f64-4412-8e59-faf3086cb826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364551852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2364551852
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2369072749
Short name T431
Test name
Test status
Simulation time 5566977388 ps
CPU time 4.06 seconds
Started Jul 01 11:15:18 AM PDT 24
Finished Jul 01 11:15:27 AM PDT 24
Peak memory 201652 kb
Host smart-3ff5f1d9-5fcb-41b5-b753-0583f50f6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369072749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2369072749
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.541492168
Short name T422
Test name
Test status
Simulation time 44747570416 ps
CPU time 5.99 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:16:04 AM PDT 24
Peak memory 201612 kb
Host smart-829de135-13fc-4a8a-bf73-bfa0c66c8e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541492168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
541492168
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.609949328
Short name T379
Test name
Test status
Simulation time 402027385 ps
CPU time 1.52 seconds
Started Jul 01 11:15:12 AM PDT 24
Finished Jul 01 11:15:15 AM PDT 24
Peak memory 201620 kb
Host smart-0984ee8c-edfc-4255-8e29-d6ea14eaeca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609949328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.609949328
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4233473001
Short name T313
Test name
Test status
Simulation time 327056804697 ps
CPU time 552.33 seconds
Started Jul 01 11:15:12 AM PDT 24
Finished Jul 01 11:24:26 AM PDT 24
Peak memory 201920 kb
Host smart-ae7cc884-d323-4ff0-899c-6d2b0e637845
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233473001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4233473001
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4217982458
Short name T300
Test name
Test status
Simulation time 205054903302 ps
CPU time 473.85 seconds
Started Jul 01 11:15:12 AM PDT 24
Finished Jul 01 11:23:08 AM PDT 24
Peak memory 201864 kb
Host smart-f0dcdded-f3fd-4ae7-92c7-c98c79dddeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217982458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4217982458
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3538641851
Short name T78
Test name
Test status
Simulation time 491775113898 ps
CPU time 1113.91 seconds
Started Jul 01 11:15:11 AM PDT 24
Finished Jul 01 11:33:46 AM PDT 24
Peak memory 201856 kb
Host smart-fc9448bb-9ac8-48f7-9f11-ec5fe050c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538641851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3538641851
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.473345046
Short name T477
Test name
Test status
Simulation time 328363825301 ps
CPU time 323.11 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:21:00 AM PDT 24
Peak memory 201860 kb
Host smart-a51a322c-2c75-4379-bfef-9a6ee1a58975
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=473345046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.473345046
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3967858809
Short name T736
Test name
Test status
Simulation time 492982867644 ps
CPU time 554.37 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:25:09 AM PDT 24
Peak memory 201808 kb
Host smart-148bba43-08d2-48a3-a293-c25ca245c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967858809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3967858809
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2800089752
Short name T617
Test name
Test status
Simulation time 331967163975 ps
CPU time 90.62 seconds
Started Jul 01 11:15:31 AM PDT 24
Finished Jul 01 11:17:14 AM PDT 24
Peak memory 201800 kb
Host smart-37080321-dce7-4528-b4ac-fe6ff14ee868
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800089752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2800089752
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4191676859
Short name T253
Test name
Test status
Simulation time 201472723063 ps
CPU time 415.98 seconds
Started Jul 01 11:15:11 AM PDT 24
Finished Jul 01 11:22:09 AM PDT 24
Peak memory 201844 kb
Host smart-c2d3e9e8-2ebe-47af-94a3-a6eba5a9e7a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191676859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4191676859
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3959354413
Short name T784
Test name
Test status
Simulation time 615111903800 ps
CPU time 375.63 seconds
Started Jul 01 11:15:25 AM PDT 24
Finished Jul 01 11:21:45 AM PDT 24
Peak memory 202064 kb
Host smart-2086ec21-165e-444f-ab6b-c5fc3c73a168
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959354413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3959354413
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1358567261
Short name T336
Test name
Test status
Simulation time 85515935064 ps
CPU time 300.15 seconds
Started Jul 01 11:15:31 AM PDT 24
Finished Jul 01 11:20:43 AM PDT 24
Peak memory 202192 kb
Host smart-65ca859f-b67e-4413-a394-bcfd3bbcc2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358567261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1358567261
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.720508453
Short name T637
Test name
Test status
Simulation time 26831157884 ps
CPU time 56.42 seconds
Started Jul 01 11:15:12 AM PDT 24
Finished Jul 01 11:16:10 AM PDT 24
Peak memory 201692 kb
Host smart-a6b5eb35-4854-40ec-a140-4953f0e6b365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720508453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.720508453
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3615565228
Short name T682
Test name
Test status
Simulation time 4223510295 ps
CPU time 10.74 seconds
Started Jul 01 11:15:25 AM PDT 24
Finished Jul 01 11:15:41 AM PDT 24
Peak memory 201692 kb
Host smart-41cff83f-bc24-4c5b-a834-25ec315e405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615565228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3615565228
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4005617059
Short name T672
Test name
Test status
Simulation time 5964845288 ps
CPU time 3.41 seconds
Started Jul 01 11:15:05 AM PDT 24
Finished Jul 01 11:15:09 AM PDT 24
Peak memory 201672 kb
Host smart-a355d25d-71fc-4d38-9f71-42446ba30cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005617059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4005617059
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.220358870
Short name T729
Test name
Test status
Simulation time 265253018435 ps
CPU time 450.36 seconds
Started Jul 01 11:15:24 AM PDT 24
Finished Jul 01 11:22:58 AM PDT 24
Peak memory 202080 kb
Host smart-aaf0534b-fc70-4ccb-9ddf-f3856eac1606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220358870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
220358870
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1609922596
Short name T709
Test name
Test status
Simulation time 425740046 ps
CPU time 0.95 seconds
Started Jul 01 11:15:21 AM PDT 24
Finished Jul 01 11:15:27 AM PDT 24
Peak memory 201628 kb
Host smart-51b001f5-9d77-4fc4-ad93-538514cc6e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609922596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1609922596
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1592152981
Short name T640
Test name
Test status
Simulation time 164628721425 ps
CPU time 97.67 seconds
Started Jul 01 11:15:17 AM PDT 24
Finished Jul 01 11:17:00 AM PDT 24
Peak memory 201864 kb
Host smart-0b2ac447-053c-4d25-a621-c63dd5a8d944
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592152981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1592152981
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.43959631
Short name T227
Test name
Test status
Simulation time 487423626961 ps
CPU time 1133.2 seconds
Started Jul 01 11:15:16 AM PDT 24
Finished Jul 01 11:34:14 AM PDT 24
Peak memory 201888 kb
Host smart-16826d38-8381-48e3-a6dd-bf23ea92a9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43959631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.43959631
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.780993800
Short name T435
Test name
Test status
Simulation time 158209869498 ps
CPU time 95.4 seconds
Started Jul 01 11:15:25 AM PDT 24
Finished Jul 01 11:17:05 AM PDT 24
Peak memory 201820 kb
Host smart-58d961ca-110e-4ed8-a47d-e1c13adc3df7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=780993800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.780993800
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4144130664
Short name T615
Test name
Test status
Simulation time 327975630006 ps
CPU time 800.39 seconds
Started Jul 01 11:15:27 AM PDT 24
Finished Jul 01 11:28:54 AM PDT 24
Peak memory 201856 kb
Host smart-11d0b91f-d6b1-4da8-9f7d-a60380217eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144130664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4144130664
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2767567054
Short name T602
Test name
Test status
Simulation time 167108754283 ps
CPU time 400.79 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:22:36 AM PDT 24
Peak memory 201896 kb
Host smart-f7537266-c3a1-4380-9965-3b7e2e56a555
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767567054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2767567054
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.16937975
Short name T630
Test name
Test status
Simulation time 545325370485 ps
CPU time 330.1 seconds
Started Jul 01 11:15:17 AM PDT 24
Finished Jul 01 11:20:52 AM PDT 24
Peak memory 201904 kb
Host smart-98875aba-9051-47b1-976f-e4653d76330e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16937975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_w
akeup.16937975
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3369295797
Short name T532
Test name
Test status
Simulation time 396119836906 ps
CPU time 209.22 seconds
Started Jul 01 11:15:18 AM PDT 24
Finished Jul 01 11:18:52 AM PDT 24
Peak memory 201908 kb
Host smart-d980948b-abcb-4ed0-ae42-92a9f20a12b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369295797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3369295797
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2641785254
Short name T635
Test name
Test status
Simulation time 132630254786 ps
CPU time 549.18 seconds
Started Jul 01 11:15:17 AM PDT 24
Finished Jul 01 11:24:31 AM PDT 24
Peak memory 202432 kb
Host smart-38db3de5-cf4f-4fd9-a516-d550cbd2b4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641785254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2641785254
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1699019803
Short name T396
Test name
Test status
Simulation time 28158800450 ps
CPU time 16.42 seconds
Started Jul 01 11:15:18 AM PDT 24
Finished Jul 01 11:15:39 AM PDT 24
Peak memory 201668 kb
Host smart-729ff5a4-4cd8-4e99-81d6-15dcde76c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699019803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1699019803
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3118993360
Short name T618
Test name
Test status
Simulation time 2989037400 ps
CPU time 2.28 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:15:57 AM PDT 24
Peak memory 201616 kb
Host smart-95efb26f-ef7b-4302-a6d5-962b6f259525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118993360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3118993360
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3037085375
Short name T452
Test name
Test status
Simulation time 5460674959 ps
CPU time 14.08 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:15:51 AM PDT 24
Peak memory 201648 kb
Host smart-05b4e790-4cbe-40c9-8947-5c8fb607ab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037085375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3037085375
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.4077215526
Short name T249
Test name
Test status
Simulation time 345696739223 ps
CPU time 700.92 seconds
Started Jul 01 11:15:28 AM PDT 24
Finished Jul 01 11:27:17 AM PDT 24
Peak memory 201892 kb
Host smart-260de0d4-95ee-4dff-a87e-15b3307aa2bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077215526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.4077215526
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.712449890
Short name T37
Test name
Test status
Simulation time 174899383684 ps
CPU time 98.5 seconds
Started Jul 01 11:15:28 AM PDT 24
Finished Jul 01 11:17:13 AM PDT 24
Peak memory 210500 kb
Host smart-33117669-ba82-4b9a-aeb0-08ffeed2842f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712449890 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.712449890
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.749770399
Short name T416
Test name
Test status
Simulation time 330654932 ps
CPU time 0.9 seconds
Started Jul 01 11:15:38 AM PDT 24
Finished Jul 01 11:16:10 AM PDT 24
Peak memory 201624 kb
Host smart-9a3af232-b63e-4edb-b76f-93a04a1c88ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749770399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.749770399
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3389814001
Short name T242
Test name
Test status
Simulation time 454697232306 ps
CPU time 1035.75 seconds
Started Jul 01 11:15:28 AM PDT 24
Finished Jul 01 11:32:51 AM PDT 24
Peak memory 201836 kb
Host smart-6017aa67-021c-48b4-b26d-57eaa5691639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389814001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3389814001
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1710558214
Short name T129
Test name
Test status
Simulation time 327616626809 ps
CPU time 209.74 seconds
Started Jul 01 11:15:19 AM PDT 24
Finished Jul 01 11:18:54 AM PDT 24
Peak memory 201884 kb
Host smart-c2881d2d-2cf4-4d19-a0e9-8ed70e630b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710558214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1710558214
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.4290524055
Short name T756
Test name
Test status
Simulation time 167033428852 ps
CPU time 180.83 seconds
Started Jul 01 11:15:24 AM PDT 24
Finished Jul 01 11:18:29 AM PDT 24
Peak memory 201852 kb
Host smart-1a42bc7a-06c5-40e8-a363-c500b092d02a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290524055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.4290524055
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1972627919
Short name T305
Test name
Test status
Simulation time 482598214405 ps
CPU time 994.66 seconds
Started Jul 01 11:15:38 AM PDT 24
Finished Jul 01 11:32:43 AM PDT 24
Peak memory 201896 kb
Host smart-76ceef41-88d8-4148-bd53-7d13dfbf7b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972627919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1972627919
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1689196481
Short name T663
Test name
Test status
Simulation time 166289625448 ps
CPU time 353.7 seconds
Started Jul 01 11:15:18 AM PDT 24
Finished Jul 01 11:21:16 AM PDT 24
Peak memory 201848 kb
Host smart-d34f2e47-dd58-4275-b53c-864a11a0dec1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689196481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1689196481
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2475983312
Short name T216
Test name
Test status
Simulation time 363454561203 ps
CPU time 844.93 seconds
Started Jul 01 11:15:24 AM PDT 24
Finished Jul 01 11:29:34 AM PDT 24
Peak memory 201880 kb
Host smart-50174bdc-6ef8-4393-80c0-6deb79512e98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475983312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2475983312
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.460973512
Short name T361
Test name
Test status
Simulation time 81754171885 ps
CPU time 316.21 seconds
Started Jul 01 11:15:36 AM PDT 24
Finished Jul 01 11:21:18 AM PDT 24
Peak memory 202272 kb
Host smart-0e0b166e-42aa-4c08-a77b-c17826ffa309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460973512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.460973512
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3224165051
Short name T346
Test name
Test status
Simulation time 30289111483 ps
CPU time 17.36 seconds
Started Jul 01 11:15:27 AM PDT 24
Finished Jul 01 11:15:51 AM PDT 24
Peak memory 201616 kb
Host smart-fc071a8c-2187-4d70-a961-2fd149550717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224165051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3224165051
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3076302552
Short name T342
Test name
Test status
Simulation time 3917625643 ps
CPU time 9.47 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:16:08 AM PDT 24
Peak memory 201664 kb
Host smart-2215602a-9b72-4f17-82a7-1bcfc97a751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076302552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3076302552
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3372527058
Short name T758
Test name
Test status
Simulation time 5884673060 ps
CPU time 5.11 seconds
Started Jul 01 11:15:19 AM PDT 24
Finished Jul 01 11:15:29 AM PDT 24
Peak memory 201676 kb
Host smart-dd49e56a-ff00-4c91-a983-3cc975b8cceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372527058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3372527058
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.803505809
Short name T6
Test name
Test status
Simulation time 539138883217 ps
CPU time 493.87 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:23:52 AM PDT 24
Peak memory 202068 kb
Host smart-fb677a0a-fe30-4522-89cb-bd021365c540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803505809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
803505809
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2197046944
Short name T40
Test name
Test status
Simulation time 101209297412 ps
CPU time 147.24 seconds
Started Jul 01 11:15:27 AM PDT 24
Finished Jul 01 11:18:00 AM PDT 24
Peak memory 210464 kb
Host smart-58ef038d-811e-47da-a8d4-34c9339a6115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197046944 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2197046944
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2395692055
Short name T425
Test name
Test status
Simulation time 448048445 ps
CPU time 1.48 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:15:59 AM PDT 24
Peak memory 201620 kb
Host smart-d7797afb-6360-4b48-a948-fa8c51167a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395692055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2395692055
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2819940513
Short name T782
Test name
Test status
Simulation time 324353287419 ps
CPU time 376.98 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:21:55 AM PDT 24
Peak memory 201892 kb
Host smart-3befd225-e08e-4b4a-b274-768bc44fe1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819940513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2819940513
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2627960664
Short name T314
Test name
Test status
Simulation time 495200176377 ps
CPU time 1049.93 seconds
Started Jul 01 11:15:32 AM PDT 24
Finished Jul 01 11:33:17 AM PDT 24
Peak memory 201832 kb
Host smart-cec9ab93-82fe-4811-b73b-a1f17fff186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627960664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2627960664
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1984316260
Short name T434
Test name
Test status
Simulation time 330618832118 ps
CPU time 189.41 seconds
Started Jul 01 11:15:32 AM PDT 24
Finished Jul 01 11:18:57 AM PDT 24
Peak memory 201836 kb
Host smart-0771cc2c-e706-41f4-af6a-cd4469a79d9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984316260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1984316260
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3478962997
Short name T684
Test name
Test status
Simulation time 496145021416 ps
CPU time 241.52 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:19:38 AM PDT 24
Peak memory 201848 kb
Host smart-3ffc9240-693d-4ec2-b6c0-8f3f11218d82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478962997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3478962997
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.970506377
Short name T172
Test name
Test status
Simulation time 189671226644 ps
CPU time 108.53 seconds
Started Jul 01 11:15:32 AM PDT 24
Finished Jul 01 11:17:36 AM PDT 24
Peak memory 201896 kb
Host smart-4c6a2946-bfe7-4f77-8dc7-2cee85630d97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970506377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.970506377
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1206437440
Short name T378
Test name
Test status
Simulation time 400807009863 ps
CPU time 490.76 seconds
Started Jul 01 11:15:26 AM PDT 24
Finished Jul 01 11:23:43 AM PDT 24
Peak memory 201904 kb
Host smart-77fe85b0-4e38-41ea-b6d0-14ab96b1a8b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206437440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1206437440
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3466364820
Short name T211
Test name
Test status
Simulation time 76278963081 ps
CPU time 294.57 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:20:32 AM PDT 24
Peak memory 202224 kb
Host smart-3a65ce00-54c6-4613-bac5-485bc1d58be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466364820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3466364820
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3793432583
Short name T549
Test name
Test status
Simulation time 30793407038 ps
CPU time 39.64 seconds
Started Jul 01 11:15:28 AM PDT 24
Finished Jul 01 11:16:15 AM PDT 24
Peak memory 201656 kb
Host smart-908da97d-164e-4cc4-9900-838f08f7d637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793432583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3793432583
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.4222337152
Short name T565
Test name
Test status
Simulation time 3558718216 ps
CPU time 2.23 seconds
Started Jul 01 11:15:29 AM PDT 24
Finished Jul 01 11:15:40 AM PDT 24
Peak memory 201652 kb
Host smart-1cb6651d-9556-4d29-93f0-505e0eb34992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222337152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4222337152
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1411648775
Short name T723
Test name
Test status
Simulation time 5857841937 ps
CPU time 6.96 seconds
Started Jul 01 11:15:27 AM PDT 24
Finished Jul 01 11:15:39 AM PDT 24
Peak memory 201656 kb
Host smart-9d90d549-dedd-49e3-9849-6b186e72220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411648775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1411648775
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1152678606
Short name T778
Test name
Test status
Simulation time 346249647114 ps
CPU time 207.17 seconds
Started Jul 01 11:15:36 AM PDT 24
Finished Jul 01 11:19:29 AM PDT 24
Peak memory 201864 kb
Host smart-13bbb066-e827-4021-8c0c-1a6e0dcb3e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152678606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1152678606
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2793553104
Short name T551
Test name
Test status
Simulation time 57997588540 ps
CPU time 119 seconds
Started Jul 01 11:15:31 AM PDT 24
Finished Jul 01 11:17:44 AM PDT 24
Peak memory 218124 kb
Host smart-b40c1279-965e-4384-abe7-640d56ded83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793553104 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2793553104
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.483253190
Short name T485
Test name
Test status
Simulation time 288207493 ps
CPU time 1.03 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:14:26 AM PDT 24
Peak memory 201640 kb
Host smart-43001647-ead3-47da-a8bc-7bd3514737c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483253190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.483253190
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3844042062
Short name T237
Test name
Test status
Simulation time 165525233575 ps
CPU time 108.17 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:16:08 AM PDT 24
Peak memory 201892 kb
Host smart-4ed5bbf5-c139-4794-a47c-b05046eed1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844042062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3844042062
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1559796477
Short name T414
Test name
Test status
Simulation time 165177226916 ps
CPU time 91.28 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:15:54 AM PDT 24
Peak memory 201836 kb
Host smart-b72dc45e-9cef-49f9-b277-7129d075354e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559796477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1559796477
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2401560782
Short name T157
Test name
Test status
Simulation time 332225143458 ps
CPU time 203.16 seconds
Started Jul 01 11:14:04 AM PDT 24
Finished Jul 01 11:17:28 AM PDT 24
Peak memory 201948 kb
Host smart-d34b1a41-4e9a-4e32-9ac1-25f2c383cbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401560782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2401560782
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4230408170
Short name T353
Test name
Test status
Simulation time 488405988438 ps
CPU time 301.21 seconds
Started Jul 01 11:14:02 AM PDT 24
Finished Jul 01 11:19:05 AM PDT 24
Peak memory 201852 kb
Host smart-547c39c9-e606-48a2-988d-bfb72b50e44e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230408170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4230408170
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1075982461
Short name T156
Test name
Test status
Simulation time 578518131617 ps
CPU time 363.96 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:20:19 AM PDT 24
Peak memory 201876 kb
Host smart-5bd9c3d0-33f3-421a-8b69-f8f60f0eba83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075982461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1075982461
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.641539263
Short name T373
Test name
Test status
Simulation time 204187340749 ps
CPU time 139.06 seconds
Started Jul 01 11:14:15 AM PDT 24
Finished Jul 01 11:16:35 AM PDT 24
Peak memory 201852 kb
Host smart-36744613-dc7e-43b8-b17a-9a1f9fb4a828
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641539263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.641539263
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.372709380
Short name T36
Test name
Test status
Simulation time 74905622862 ps
CPU time 265.89 seconds
Started Jul 01 11:14:07 AM PDT 24
Finished Jul 01 11:18:33 AM PDT 24
Peak memory 202220 kb
Host smart-1c60492e-5eb5-4473-8ab3-9abc8bf3af6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372709380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.372709380
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2134708232
Short name T508
Test name
Test status
Simulation time 44920235250 ps
CPU time 28.82 seconds
Started Jul 01 11:14:03 AM PDT 24
Finished Jul 01 11:14:33 AM PDT 24
Peak memory 201696 kb
Host smart-8460480d-8f2d-4147-9e20-bc0c83268d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134708232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2134708232
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2837350032
Short name T163
Test name
Test status
Simulation time 5233082092 ps
CPU time 12.42 seconds
Started Jul 01 11:14:04 AM PDT 24
Finished Jul 01 11:14:17 AM PDT 24
Peak memory 201704 kb
Host smart-aaeed850-e367-482a-a38b-f22242d27a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837350032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2837350032
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.4261967109
Short name T63
Test name
Test status
Simulation time 4115661600 ps
CPU time 9.35 seconds
Started Jul 01 11:14:18 AM PDT 24
Finished Jul 01 11:14:27 AM PDT 24
Peak memory 217312 kb
Host smart-d1db25f4-d959-4308-acfc-4091a455c095
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261967109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.4261967109
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2905178615
Short name T417
Test name
Test status
Simulation time 5730830431 ps
CPU time 3.7 seconds
Started Jul 01 11:14:03 AM PDT 24
Finished Jul 01 11:14:08 AM PDT 24
Peak memory 201704 kb
Host smart-5b1e8535-59f4-4fad-b38c-e85b272b4481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905178615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2905178615
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3841536853
Short name T167
Test name
Test status
Simulation time 162680669733 ps
CPU time 388.82 seconds
Started Jul 01 11:14:07 AM PDT 24
Finished Jul 01 11:20:36 AM PDT 24
Peak memory 210512 kb
Host smart-302db36e-c25e-48dc-9888-8578fe1610fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841536853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3841536853
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.849391425
Short name T94
Test name
Test status
Simulation time 395441254 ps
CPU time 1.03 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:15:56 AM PDT 24
Peak memory 201624 kb
Host smart-e95e4256-a96d-4140-9a42-10b5878b3558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849391425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.849391425
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.4286349289
Short name T678
Test name
Test status
Simulation time 169596310963 ps
CPU time 187.76 seconds
Started Jul 01 11:15:38 AM PDT 24
Finished Jul 01 11:19:16 AM PDT 24
Peak memory 201908 kb
Host smart-d1433138-0209-46ca-9891-7069839974df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286349289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.4286349289
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1424635577
Short name T786
Test name
Test status
Simulation time 484736647343 ps
CPU time 515.51 seconds
Started Jul 01 11:15:39 AM PDT 24
Finished Jul 01 11:24:49 AM PDT 24
Peak memory 201772 kb
Host smart-935714f6-ecb4-497e-9fad-7dd8a02cea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424635577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1424635577
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1260611333
Short name T160
Test name
Test status
Simulation time 489741503997 ps
CPU time 545.91 seconds
Started Jul 01 11:15:31 AM PDT 24
Finished Jul 01 11:24:49 AM PDT 24
Peak memory 201852 kb
Host smart-cc642f27-8bb4-4d28-96d5-baf2fee7232b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260611333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1260611333
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3264994609
Short name T372
Test name
Test status
Simulation time 500312342037 ps
CPU time 453.16 seconds
Started Jul 01 11:15:30 AM PDT 24
Finished Jul 01 11:23:15 AM PDT 24
Peak memory 201828 kb
Host smart-0b8145bc-b99b-4d9c-aaee-7d5b1e65a390
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264994609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3264994609
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1757323152
Short name T331
Test name
Test status
Simulation time 351901161009 ps
CPU time 199.81 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:19:15 AM PDT 24
Peak memory 201804 kb
Host smart-425df584-798e-4b1d-bcca-4d3a5cef2628
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757323152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1757323152
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.319905718
Short name T600
Test name
Test status
Simulation time 406758855358 ps
CPU time 270.96 seconds
Started Jul 01 11:15:32 AM PDT 24
Finished Jul 01 11:20:18 AM PDT 24
Peak memory 201872 kb
Host smart-5e815cf5-47bb-4632-9cf8-7c2b3eb91eb9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319905718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.319905718
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1131101465
Short name T202
Test name
Test status
Simulation time 117320164442 ps
CPU time 424.02 seconds
Started Jul 01 11:15:31 AM PDT 24
Finished Jul 01 11:22:47 AM PDT 24
Peak memory 202260 kb
Host smart-852eb9fa-453a-4eb6-8f33-c5b49e7cf415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131101465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1131101465
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2320230373
Short name T402
Test name
Test status
Simulation time 32303346333 ps
CPU time 21.92 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:16:17 AM PDT 24
Peak memory 201696 kb
Host smart-90ae1237-b5bf-43d2-bf5a-ec08d7898d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320230373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2320230373
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1818037450
Short name T161
Test name
Test status
Simulation time 3131018199 ps
CPU time 4 seconds
Started Jul 01 11:15:33 AM PDT 24
Finished Jul 01 11:15:54 AM PDT 24
Peak memory 201680 kb
Host smart-7d33a6fa-9dd5-485b-b377-0fab627d3e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818037450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1818037450
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2894343302
Short name T352
Test name
Test status
Simulation time 5928188246 ps
CPU time 3.44 seconds
Started Jul 01 11:15:36 AM PDT 24
Finished Jul 01 11:16:07 AM PDT 24
Peak memory 201696 kb
Host smart-fbc997bc-af27-4785-8dd5-fb7f288688be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894343302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2894343302
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2841453929
Short name T592
Test name
Test status
Simulation time 163563283162 ps
CPU time 368.99 seconds
Started Jul 01 11:15:36 AM PDT 24
Finished Jul 01 11:22:11 AM PDT 24
Peak memory 201904 kb
Host smart-d4f11c2d-1c64-4b66-98d2-a54ffce3b7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841453929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2841453929
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1694941663
Short name T251
Test name
Test status
Simulation time 44033755415 ps
CPU time 145.7 seconds
Started Jul 01 11:15:39 AM PDT 24
Finished Jul 01 11:18:39 AM PDT 24
Peak memory 217840 kb
Host smart-3570ba21-0fd1-4dd2-a095-abf2217b405e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694941663 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1694941663
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2532264596
Short name T99
Test name
Test status
Simulation time 478482594 ps
CPU time 0.72 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:15:56 AM PDT 24
Peak memory 201612 kb
Host smart-4a417b45-e60a-4c65-801b-1cc2eb4b06ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532264596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2532264596
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.193050671
Short name T133
Test name
Test status
Simulation time 184025014188 ps
CPU time 99.99 seconds
Started Jul 01 11:15:36 AM PDT 24
Finished Jul 01 11:17:42 AM PDT 24
Peak memory 201884 kb
Host smart-6d4f05b9-2827-4e90-908b-ab874a9adcc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193050671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.193050671
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1976522855
Short name T626
Test name
Test status
Simulation time 528185263240 ps
CPU time 573.02 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:25:28 AM PDT 24
Peak memory 201888 kb
Host smart-6c222602-cc79-4101-b355-0043a31e11ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976522855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1976522855
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2940638670
Short name T454
Test name
Test status
Simulation time 161402962181 ps
CPU time 160.31 seconds
Started Jul 01 11:15:33 AM PDT 24
Finished Jul 01 11:18:32 AM PDT 24
Peak memory 201888 kb
Host smart-81e742c1-a428-426d-a930-afda3428df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940638670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2940638670
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4140945955
Short name T149
Test name
Test status
Simulation time 342218763898 ps
CPU time 239.37 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:19:54 AM PDT 24
Peak memory 201788 kb
Host smart-bf0ca220-702d-4ecd-805d-b26a660e7927
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140945955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4140945955
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1666057633
Short name T143
Test name
Test status
Simulation time 327375188062 ps
CPU time 366.84 seconds
Started Jul 01 11:15:32 AM PDT 24
Finished Jul 01 11:21:54 AM PDT 24
Peak memory 201904 kb
Host smart-abbc7546-2b8d-4a04-a5dd-a3d6443c37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666057633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1666057633
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.297156685
Short name T740
Test name
Test status
Simulation time 321073636736 ps
CPU time 774.71 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:28:53 AM PDT 24
Peak memory 201852 kb
Host smart-9f29245b-1ff4-457a-9b4e-ddfb39054686
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=297156685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.297156685
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2083973244
Short name T712
Test name
Test status
Simulation time 541393780182 ps
CPU time 341.68 seconds
Started Jul 01 11:15:38 AM PDT 24
Finished Jul 01 11:21:50 AM PDT 24
Peak memory 201864 kb
Host smart-524d3529-7e94-48cb-94c7-1c658fcfe933
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083973244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2083973244
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1168239821
Short name T689
Test name
Test status
Simulation time 589873757051 ps
CPU time 258.18 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:20:20 AM PDT 24
Peak memory 201860 kb
Host smart-92691941-c9b0-4ea5-a450-39df2140d305
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168239821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1168239821
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3336199542
Short name T371
Test name
Test status
Simulation time 125698671319 ps
CPU time 679.1 seconds
Started Jul 01 11:15:39 AM PDT 24
Finished Jul 01 11:27:28 AM PDT 24
Peak memory 202136 kb
Host smart-85b4c1d8-ab6f-4ce6-a185-a9c0df0a6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336199542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3336199542
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1151831055
Short name T707
Test name
Test status
Simulation time 34759380998 ps
CPU time 73.23 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:17:08 AM PDT 24
Peak memory 201696 kb
Host smart-eb1e82ba-0ebb-46e0-88db-b21442b71b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151831055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1151831055
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4079074810
Short name T568
Test name
Test status
Simulation time 3118962597 ps
CPU time 1.59 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:16:00 AM PDT 24
Peak memory 201672 kb
Host smart-f72810f6-0c71-40f5-8a0a-62d02222aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079074810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4079074810
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.66233190
Short name T88
Test name
Test status
Simulation time 5620291678 ps
CPU time 4.02 seconds
Started Jul 01 11:15:37 AM PDT 24
Finished Jul 01 11:16:09 AM PDT 24
Peak memory 201600 kb
Host smart-182def29-cfe2-46cf-85e5-d8d8e186b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66233190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.66233190
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2061360188
Short name T750
Test name
Test status
Simulation time 530794506886 ps
CPU time 388.07 seconds
Started Jul 01 11:15:43 AM PDT 24
Finished Jul 01 11:22:52 AM PDT 24
Peak memory 201800 kb
Host smart-62af2d5d-06cf-464a-96e7-62af2aabf071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061360188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2061360188
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.770442571
Short name T436
Test name
Test status
Simulation time 414905348157 ps
CPU time 509.28 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:24:27 AM PDT 24
Peak memory 210572 kb
Host smart-9832a693-49dc-4dfb-9f3a-80360853c2a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770442571 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.770442571
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2883812161
Short name T483
Test name
Test status
Simulation time 532448031 ps
CPU time 0.8 seconds
Started Jul 01 11:15:40 AM PDT 24
Finished Jul 01 11:16:15 AM PDT 24
Peak memory 201624 kb
Host smart-cc2e3b08-8c60-4fa2-9e5a-0c452e3bde99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883812161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2883812161
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3596854085
Short name T312
Test name
Test status
Simulation time 161688124071 ps
CPU time 368.09 seconds
Started Jul 01 11:15:44 AM PDT 24
Finished Jul 01 11:22:37 AM PDT 24
Peak memory 201888 kb
Host smart-e01086f9-0fb4-4a12-926f-dffda5ff622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596854085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3596854085
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.737427565
Short name T159
Test name
Test status
Simulation time 330071559475 ps
CPU time 409.04 seconds
Started Jul 01 11:15:41 AM PDT 24
Finished Jul 01 11:23:08 AM PDT 24
Peak memory 201848 kb
Host smart-8e24e46b-b16a-4a52-9324-ea5b9ed83f96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=737427565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.737427565
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3703276860
Short name T283
Test name
Test status
Simulation time 169982020614 ps
CPU time 198.02 seconds
Started Jul 01 11:15:34 AM PDT 24
Finished Jul 01 11:19:13 AM PDT 24
Peak memory 201916 kb
Host smart-d86444f0-4899-4473-9782-30695d38fc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703276860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3703276860
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1515293004
Short name T691
Test name
Test status
Simulation time 332601569719 ps
CPU time 196.83 seconds
Started Jul 01 11:15:39 AM PDT 24
Finished Jul 01 11:19:31 AM PDT 24
Peak memory 201848 kb
Host smart-8f145ca7-b0d4-4835-a49c-df97f8e2de7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515293004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1515293004
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4285787204
Short name T387
Test name
Test status
Simulation time 590438406133 ps
CPU time 604.84 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:26:03 AM PDT 24
Peak memory 201872 kb
Host smart-63cfce20-910a-427b-b9d6-b852b1d5b453
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285787204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4285787204
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1977903548
Short name T638
Test name
Test status
Simulation time 41766991572 ps
CPU time 18.64 seconds
Started Jul 01 11:15:41 AM PDT 24
Finished Jul 01 11:16:37 AM PDT 24
Peak memory 201620 kb
Host smart-b46415cc-a050-4784-a1ff-9f8d3f0e6ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977903548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1977903548
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.545558301
Short name T356
Test name
Test status
Simulation time 4065961309 ps
CPU time 9.25 seconds
Started Jul 01 11:15:40 AM PDT 24
Finished Jul 01 11:16:23 AM PDT 24
Peak memory 201692 kb
Host smart-8a691d99-cc60-4b17-a86b-85f238f56d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545558301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.545558301
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.408973138
Short name T580
Test name
Test status
Simulation time 6144735780 ps
CPU time 3.66 seconds
Started Jul 01 11:15:35 AM PDT 24
Finished Jul 01 11:15:59 AM PDT 24
Peak memory 201704 kb
Host smart-fc2c943d-a728-4aa7-8f37-75b8b70914bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408973138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.408973138
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2555488565
Short name T666
Test name
Test status
Simulation time 61569353339 ps
CPU time 36.65 seconds
Started Jul 01 11:15:45 AM PDT 24
Finished Jul 01 11:17:11 AM PDT 24
Peak memory 210192 kb
Host smart-e721aa94-7ac4-4c3e-9f12-ce874910c965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555488565 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2555488565
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3579997838
Short name T591
Test name
Test status
Simulation time 510035972 ps
CPU time 0.89 seconds
Started Jul 01 11:15:45 AM PDT 24
Finished Jul 01 11:16:35 AM PDT 24
Peak memory 201616 kb
Host smart-c350072c-1042-435d-a50c-863b41be3593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579997838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3579997838
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2727687708
Short name T222
Test name
Test status
Simulation time 509935349745 ps
CPU time 1200.14 seconds
Started Jul 01 11:15:48 AM PDT 24
Finished Jul 01 11:36:42 AM PDT 24
Peak memory 201944 kb
Host smart-3153a8b5-faf3-4457-8054-01286cd9dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727687708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2727687708
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2388998451
Short name T164
Test name
Test status
Simulation time 326579307746 ps
CPU time 188.78 seconds
Started Jul 01 11:15:42 AM PDT 24
Finished Jul 01 11:19:32 AM PDT 24
Peak memory 201868 kb
Host smart-04389f6f-cd72-4683-bbd8-e8fea5f7c0fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388998451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2388998451
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.62254547
Short name T278
Test name
Test status
Simulation time 333713734280 ps
CPU time 391.42 seconds
Started Jul 01 11:15:40 AM PDT 24
Finished Jul 01 11:22:45 AM PDT 24
Peak memory 201932 kb
Host smart-84d83cbf-722b-46cb-aeb6-1e84e700e5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62254547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.62254547
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4197719612
Short name T433
Test name
Test status
Simulation time 492766290135 ps
CPU time 753.84 seconds
Started Jul 01 11:15:42 AM PDT 24
Finished Jul 01 11:28:57 AM PDT 24
Peak memory 201796 kb
Host smart-292529e8-54af-4dbd-8cc2-ae619aebb448
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197719612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4197719612
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4255763897
Short name T731
Test name
Test status
Simulation time 362788227173 ps
CPU time 435.29 seconds
Started Jul 01 11:15:44 AM PDT 24
Finished Jul 01 11:23:44 AM PDT 24
Peak memory 201888 kb
Host smart-7c72b7c0-1e9a-4909-929b-b70ff9139e7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255763897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4255763897
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.203774779
Short name T45
Test name
Test status
Simulation time 613683974212 ps
CPU time 352.73 seconds
Started Jul 01 11:15:47 AM PDT 24
Finished Jul 01 11:22:28 AM PDT 24
Peak memory 201836 kb
Host smart-556400a0-fd45-49b5-93d5-abdd8657ce3f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203774779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.203774779
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.759016259
Short name T503
Test name
Test status
Simulation time 37283006659 ps
CPU time 86.03 seconds
Started Jul 01 11:15:48 AM PDT 24
Finished Jul 01 11:18:08 AM PDT 24
Peak memory 201692 kb
Host smart-f1d78a83-d6e5-4032-9f99-d2b5585abcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759016259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.759016259
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3967353821
Short name T718
Test name
Test status
Simulation time 3464687909 ps
CPU time 8.37 seconds
Started Jul 01 11:15:48 AM PDT 24
Finished Jul 01 11:16:50 AM PDT 24
Peak memory 201656 kb
Host smart-8f8df377-1c25-4270-a72f-9f0c4bca2d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967353821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3967353821
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4262001433
Short name T530
Test name
Test status
Simulation time 5953644085 ps
CPU time 4.1 seconds
Started Jul 01 11:15:39 AM PDT 24
Finished Jul 01 11:16:18 AM PDT 24
Peak memory 201668 kb
Host smart-c4f9adbe-c582-4cbd-a6b5-40b6e5149411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262001433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4262001433
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3082453858
Short name T593
Test name
Test status
Simulation time 332858276242 ps
CPU time 152.41 seconds
Started Jul 01 11:15:45 AM PDT 24
Finished Jul 01 11:19:07 AM PDT 24
Peak memory 201872 kb
Host smart-e22a8de3-6a03-472f-ba5f-e9e56b015f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082453858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3082453858
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2311811098
Short name T295
Test name
Test status
Simulation time 128092290537 ps
CPU time 452.26 seconds
Started Jul 01 11:15:46 AM PDT 24
Finished Jul 01 11:24:07 AM PDT 24
Peak memory 210504 kb
Host smart-10d4d6bb-81ef-414d-8403-9481fac81391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311811098 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2311811098
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3503834425
Short name T555
Test name
Test status
Simulation time 441300587 ps
CPU time 1.1 seconds
Started Jul 01 11:15:50 AM PDT 24
Finished Jul 01 11:16:48 AM PDT 24
Peak memory 201528 kb
Host smart-fd379003-2435-48ac-954e-d126eb7c1929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503834425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3503834425
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1237341279
Short name T710
Test name
Test status
Simulation time 185939090468 ps
CPU time 4.18 seconds
Started Jul 01 11:15:47 AM PDT 24
Finished Jul 01 11:16:39 AM PDT 24
Peak memory 201880 kb
Host smart-90c86b2e-4d9c-4508-ac4e-210378de487d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237341279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1237341279
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3958993292
Short name T588
Test name
Test status
Simulation time 162322871652 ps
CPU time 398.4 seconds
Started Jul 01 11:15:48 AM PDT 24
Finished Jul 01 11:23:20 AM PDT 24
Peak memory 201868 kb
Host smart-bd85e89a-a4ca-46bd-b726-4adc96e3ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958993292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3958993292
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1449393751
Short name T514
Test name
Test status
Simulation time 159644303775 ps
CPU time 386.39 seconds
Started Jul 01 11:15:46 AM PDT 24
Finished Jul 01 11:23:01 AM PDT 24
Peak memory 201912 kb
Host smart-efbb88bb-6412-4766-b89e-67189d3027d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449393751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1449393751
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3099012326
Short name T512
Test name
Test status
Simulation time 495127826769 ps
CPU time 596.68 seconds
Started Jul 01 11:15:49 AM PDT 24
Finished Jul 01 11:26:44 AM PDT 24
Peak memory 201824 kb
Host smart-abacbf50-f895-4e98-8e92-f6e7994439ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099012326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3099012326
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3943223804
Short name T461
Test name
Test status
Simulation time 328768238457 ps
CPU time 101.11 seconds
Started Jul 01 11:15:45 AM PDT 24
Finished Jul 01 11:18:16 AM PDT 24
Peak memory 201952 kb
Host smart-48aecd41-591c-4829-afec-f44433f4f3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943223804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3943223804
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3060045352
Short name T702
Test name
Test status
Simulation time 479934011714 ps
CPU time 1066.88 seconds
Started Jul 01 11:15:45 AM PDT 24
Finished Jul 01 11:34:22 AM PDT 24
Peak memory 201836 kb
Host smart-8651aab4-e704-4fff-b038-63eade93bd42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060045352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3060045352
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2388458408
Short name T599
Test name
Test status
Simulation time 196513940283 ps
CPU time 232.31 seconds
Started Jul 01 11:15:46 AM PDT 24
Finished Jul 01 11:20:27 AM PDT 24
Peak memory 201852 kb
Host smart-25aae9c1-75fb-49db-9f35-a41df843a171
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388458408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2388458408
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3302343567
Short name T49
Test name
Test status
Simulation time 94383590545 ps
CPU time 466.46 seconds
Started Jul 01 11:15:49 AM PDT 24
Finished Jul 01 11:24:33 AM PDT 24
Peak memory 202216 kb
Host smart-fb094fb7-ed7c-45bc-9578-1a94db3b592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302343567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3302343567
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3400119862
Short name T489
Test name
Test status
Simulation time 30971550114 ps
CPU time 28.88 seconds
Started Jul 01 11:15:51 AM PDT 24
Finished Jul 01 11:17:16 AM PDT 24
Peak memory 201644 kb
Host smart-edda25b2-642e-4027-9913-2ef14a77c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400119862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3400119862
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1294053479
Short name T486
Test name
Test status
Simulation time 4994211800 ps
CPU time 6.09 seconds
Started Jul 01 11:15:51 AM PDT 24
Finished Jul 01 11:16:53 AM PDT 24
Peak memory 201676 kb
Host smart-ec8cd1d0-45a2-4f81-896e-df1fcc14e4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294053479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1294053479
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2465373608
Short name T511
Test name
Test status
Simulation time 5842936313 ps
CPU time 4.19 seconds
Started Jul 01 11:15:45 AM PDT 24
Finished Jul 01 11:16:39 AM PDT 24
Peak memory 201676 kb
Host smart-ecb63fe6-c4d9-4667-bbcf-4a78d4ae10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465373608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2465373608
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.219685699
Short name T270
Test name
Test status
Simulation time 233186646058 ps
CPU time 93.24 seconds
Started Jul 01 11:15:50 AM PDT 24
Finished Jul 01 11:18:20 AM PDT 24
Peak memory 210200 kb
Host smart-7bede106-2d62-4abc-ad83-daef903ef83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219685699 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.219685699
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3459697765
Short name T493
Test name
Test status
Simulation time 294882242 ps
CPU time 1 seconds
Started Jul 01 11:16:01 AM PDT 24
Finished Jul 01 11:17:21 AM PDT 24
Peak memory 201620 kb
Host smart-9dcfa105-9301-45e7-b5d9-324c40ff010b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459697765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3459697765
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2177362055
Short name T238
Test name
Test status
Simulation time 190892716838 ps
CPU time 227.38 seconds
Started Jul 01 11:15:55 AM PDT 24
Finished Jul 01 11:20:47 AM PDT 24
Peak memory 201844 kb
Host smart-bbd4ee0d-2936-4534-b836-c09d2c9eb12c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177362055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2177362055
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1290710918
Short name T126
Test name
Test status
Simulation time 170611544402 ps
CPU time 397.35 seconds
Started Jul 01 11:15:56 AM PDT 24
Finished Jul 01 11:23:38 AM PDT 24
Peak memory 201872 kb
Host smart-f0ec2ab3-fa86-4164-a2db-708e34aa6f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290710918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1290710918
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2930845242
Short name T297
Test name
Test status
Simulation time 331633785615 ps
CPU time 778.52 seconds
Started Jul 01 11:15:51 AM PDT 24
Finished Jul 01 11:29:46 AM PDT 24
Peak memory 201912 kb
Host smart-5eb9f13f-064d-44c7-8eea-890ed3d5edac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930845242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2930845242
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2780010176
Short name T785
Test name
Test status
Simulation time 163889959252 ps
CPU time 376.9 seconds
Started Jul 01 11:15:56 AM PDT 24
Finished Jul 01 11:23:17 AM PDT 24
Peak memory 201848 kb
Host smart-04ba19bf-5f46-4598-b97f-40a31e9d52d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780010176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2780010176
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3572908644
Short name T628
Test name
Test status
Simulation time 488584661296 ps
CPU time 543.63 seconds
Started Jul 01 11:15:50 AM PDT 24
Finished Jul 01 11:25:51 AM PDT 24
Peak memory 201916 kb
Host smart-8e22b5ad-a76e-48e9-8f13-0621b231a299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572908644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3572908644
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1983514500
Short name T380
Test name
Test status
Simulation time 492127601693 ps
CPU time 326.31 seconds
Started Jul 01 11:15:50 AM PDT 24
Finished Jul 01 11:22:14 AM PDT 24
Peak memory 201844 kb
Host smart-d76ca900-f854-4379-9b53-a5276a88c52a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983514500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1983514500
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2995307116
Short name T535
Test name
Test status
Simulation time 373844173733 ps
CPU time 884.89 seconds
Started Jul 01 11:15:55 AM PDT 24
Finished Jul 01 11:31:45 AM PDT 24
Peak memory 201880 kb
Host smart-714d372c-57fd-48c2-a72d-ea8cfa0deaf3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995307116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2995307116
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1387534906
Short name T534
Test name
Test status
Simulation time 412600905178 ps
CPU time 433.7 seconds
Started Jul 01 11:15:58 AM PDT 24
Finished Jul 01 11:24:23 AM PDT 24
Peak memory 201772 kb
Host smart-af0c46ca-b939-4e75-816e-610d5110a9c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387534906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1387534906
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3147051793
Short name T421
Test name
Test status
Simulation time 84356026289 ps
CPU time 466.01 seconds
Started Jul 01 11:15:56 AM PDT 24
Finished Jul 01 11:24:47 AM PDT 24
Peak memory 202228 kb
Host smart-48738ab8-cf72-4460-8e4d-6bcdfe39e060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147051793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3147051793
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1442618548
Short name T794
Test name
Test status
Simulation time 36520901233 ps
CPU time 47.05 seconds
Started Jul 01 11:15:55 AM PDT 24
Finished Jul 01 11:17:47 AM PDT 24
Peak memory 201652 kb
Host smart-47f92818-6cb1-4d36-aefc-61e347fdef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442618548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1442618548
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3677707285
Short name T643
Test name
Test status
Simulation time 4612745057 ps
CPU time 10.32 seconds
Started Jul 01 11:15:55 AM PDT 24
Finished Jul 01 11:17:10 AM PDT 24
Peak memory 201692 kb
Host smart-f4ba2f33-3c24-48e7-a846-7d45d3f92683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677707285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3677707285
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2190695333
Short name T386
Test name
Test status
Simulation time 6032525442 ps
CPU time 3.96 seconds
Started Jul 01 11:15:51 AM PDT 24
Finished Jul 01 11:16:51 AM PDT 24
Peak memory 201696 kb
Host smart-bc8082d8-ed1b-41cc-873c-67d6544f3f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190695333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2190695333
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3888058734
Short name T48
Test name
Test status
Simulation time 397056706058 ps
CPU time 889.73 seconds
Started Jul 01 11:16:01 AM PDT 24
Finished Jul 01 11:32:10 AM PDT 24
Peak memory 210296 kb
Host smart-9e813454-353f-4610-9865-bc552b84e69f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888058734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3888058734
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2294483086
Short name T169
Test name
Test status
Simulation time 144131384664 ps
CPU time 79.32 seconds
Started Jul 01 11:15:59 AM PDT 24
Finished Jul 01 11:18:29 AM PDT 24
Peak memory 211456 kb
Host smart-fbb4f581-c8c1-42da-a740-0dc68cda560b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294483086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2294483086
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2977250404
Short name T695
Test name
Test status
Simulation time 345444735 ps
CPU time 0.83 seconds
Started Jul 01 11:16:01 AM PDT 24
Finished Jul 01 11:17:31 AM PDT 24
Peak memory 201604 kb
Host smart-be986014-e61b-44dc-9baf-912008a641e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977250404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2977250404
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2223557032
Short name T261
Test name
Test status
Simulation time 161805814892 ps
CPU time 56.7 seconds
Started Jul 01 11:16:01 AM PDT 24
Finished Jul 01 11:18:17 AM PDT 24
Peak memory 201856 kb
Host smart-a42d57af-25e0-40b7-b5d0-7eeaef8ec1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223557032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2223557032
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3030331008
Short name T711
Test name
Test status
Simulation time 491119411477 ps
CPU time 1117.36 seconds
Started Jul 01 11:16:03 AM PDT 24
Finished Jul 01 11:36:08 AM PDT 24
Peak memory 201864 kb
Host smart-cc956ce6-57cc-4e23-8e14-e3871ca86618
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030331008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3030331008
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3034667097
Short name T195
Test name
Test status
Simulation time 489862157478 ps
CPU time 566.15 seconds
Started Jul 01 11:16:02 AM PDT 24
Finished Jul 01 11:26:56 AM PDT 24
Peak memory 201816 kb
Host smart-d3d190cb-fb1d-404f-853c-a548bda26f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034667097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3034667097
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3291454572
Short name T465
Test name
Test status
Simulation time 502801541307 ps
CPU time 102.28 seconds
Started Jul 01 11:16:03 AM PDT 24
Finished Jul 01 11:19:06 AM PDT 24
Peak memory 201780 kb
Host smart-a4b0ed1a-4677-4f56-93c2-490dfb61687a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291454572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3291454572
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1482141633
Short name T658
Test name
Test status
Simulation time 180521569084 ps
CPU time 393.67 seconds
Started Jul 01 11:16:02 AM PDT 24
Finished Jul 01 11:23:54 AM PDT 24
Peak memory 201920 kb
Host smart-13474a69-9092-4c34-a7ef-5884062e30e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482141633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1482141633
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4082863363
Short name T411
Test name
Test status
Simulation time 597904991739 ps
CPU time 359.42 seconds
Started Jul 01 11:16:03 AM PDT 24
Finished Jul 01 11:23:30 AM PDT 24
Peak memory 201832 kb
Host smart-b76cd352-7c07-4ce2-9f51-e3095560fc76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082863363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4082863363
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.51779710
Short name T478
Test name
Test status
Simulation time 76728564993 ps
CPU time 362.43 seconds
Started Jul 01 11:16:01 AM PDT 24
Finished Jul 01 11:23:23 AM PDT 24
Peak memory 202104 kb
Host smart-c0d3f681-090f-454d-85db-b8a4c3a11f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51779710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.51779710
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2921434345
Short name T652
Test name
Test status
Simulation time 38684549938 ps
CPU time 15.85 seconds
Started Jul 01 11:16:02 AM PDT 24
Finished Jul 01 11:17:40 AM PDT 24
Peak memory 201596 kb
Host smart-f8b82ba2-19f7-4a84-ab4c-25328de4bd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921434345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2921434345
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.4192837405
Short name T41
Test name
Test status
Simulation time 3659190003 ps
CPU time 2.83 seconds
Started Jul 01 11:16:02 AM PDT 24
Finished Jul 01 11:17:27 AM PDT 24
Peak memory 201624 kb
Host smart-c2078050-4acf-4f36-8fc3-42d09b77e393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192837405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4192837405
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3319416164
Short name T413
Test name
Test status
Simulation time 5828493126 ps
CPU time 7.52 seconds
Started Jul 01 11:15:59 AM PDT 24
Finished Jul 01 11:17:17 AM PDT 24
Peak memory 201664 kb
Host smart-6d962b74-06cf-4a85-bce3-d5253f6150fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319416164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3319416164
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1219120352
Short name T667
Test name
Test status
Simulation time 498127419117 ps
CPU time 1396.18 seconds
Started Jul 01 11:16:02 AM PDT 24
Finished Jul 01 11:40:40 AM PDT 24
Peak memory 210432 kb
Host smart-e5b8a420-c010-46cb-ab45-34d4ae0a12c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219120352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1219120352
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2372260822
Short name T97
Test name
Test status
Simulation time 46343186155 ps
CPU time 150.77 seconds
Started Jul 01 11:16:00 AM PDT 24
Finished Jul 01 11:19:51 AM PDT 24
Peak memory 210512 kb
Host smart-83d931d7-bdc1-4f67-b923-571ce5e7c8d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372260822 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2372260822
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.246059252
Short name T648
Test name
Test status
Simulation time 477431710 ps
CPU time 1.42 seconds
Started Jul 01 11:16:12 AM PDT 24
Finished Jul 01 11:17:58 AM PDT 24
Peak memory 201532 kb
Host smart-a5284df2-8cf4-4d0e-9fdf-1e9580666974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246059252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.246059252
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3172361062
Short name T427
Test name
Test status
Simulation time 192532171307 ps
CPU time 107.77 seconds
Started Jul 01 11:16:05 AM PDT 24
Finished Jul 01 11:19:12 AM PDT 24
Peak memory 201840 kb
Host smart-98f10a21-5e16-46a0-8730-575ee27b3675
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172361062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3172361062
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3974454634
Short name T231
Test name
Test status
Simulation time 197408959576 ps
CPU time 119.39 seconds
Started Jul 01 11:16:11 AM PDT 24
Finished Jul 01 11:19:30 AM PDT 24
Peak memory 201900 kb
Host smart-8c590656-a78c-4362-b482-98ea0a6faba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974454634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3974454634
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1978277458
Short name T107
Test name
Test status
Simulation time 164284254818 ps
CPU time 390.88 seconds
Started Jul 01 11:16:06 AM PDT 24
Finished Jul 01 11:23:55 AM PDT 24
Peak memory 201856 kb
Host smart-742c6f2b-ee44-4107-b29c-59e7593710a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978277458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1978277458
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3019703933
Short name T676
Test name
Test status
Simulation time 157473570386 ps
CPU time 96.69 seconds
Started Jul 01 11:16:05 AM PDT 24
Finished Jul 01 11:19:01 AM PDT 24
Peak memory 201848 kb
Host smart-622931e8-db7f-4a19-87ac-0b5d355fac0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019703933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3019703933
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2448531285
Short name T142
Test name
Test status
Simulation time 334703612596 ps
CPU time 406.86 seconds
Started Jul 01 11:16:02 AM PDT 24
Finished Jul 01 11:24:11 AM PDT 24
Peak memory 201816 kb
Host smart-18c44014-a378-4d71-bb4f-e4046679d63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448531285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2448531285
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2706741520
Short name T787
Test name
Test status
Simulation time 333128386628 ps
CPU time 774.98 seconds
Started Jul 01 11:16:08 AM PDT 24
Finished Jul 01 11:30:24 AM PDT 24
Peak memory 201928 kb
Host smart-ded42c36-1c4a-4ac6-a4a7-f2baf2f569a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706741520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2706741520
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3179006706
Short name T213
Test name
Test status
Simulation time 655669549848 ps
CPU time 1573.38 seconds
Started Jul 01 11:16:06 AM PDT 24
Finished Jul 01 11:43:38 AM PDT 24
Peak memory 201952 kb
Host smart-2ee016a9-b151-4884-8f95-29427a024ff1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179006706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3179006706
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.527301258
Short name T343
Test name
Test status
Simulation time 411735836091 ps
CPU time 491.43 seconds
Started Jul 01 11:16:07 AM PDT 24
Finished Jul 01 11:25:36 AM PDT 24
Peak memory 201792 kb
Host smart-0d212dd0-731b-44c4-80ed-fc5af006c820
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527301258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.527301258
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.165486617
Short name T688
Test name
Test status
Simulation time 89255344831 ps
CPU time 314.19 seconds
Started Jul 01 11:16:13 AM PDT 24
Finished Jul 01 11:23:08 AM PDT 24
Peak memory 202116 kb
Host smart-5ee7c517-ba5b-4393-abf6-26cb96fa748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165486617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.165486617
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2799880412
Short name T481
Test name
Test status
Simulation time 41925340284 ps
CPU time 93.47 seconds
Started Jul 01 11:16:14 AM PDT 24
Finished Jul 01 11:19:14 AM PDT 24
Peak memory 201640 kb
Host smart-84b3e3a3-3a6d-40ce-8e0d-6115574d4549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799880412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2799880412
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3681938180
Short name T733
Test name
Test status
Simulation time 5302618043 ps
CPU time 3.57 seconds
Started Jul 01 11:16:12 AM PDT 24
Finished Jul 01 11:17:38 AM PDT 24
Peak memory 201664 kb
Host smart-68ef161b-d176-40a6-9b92-5c8ed2d8c23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681938180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3681938180
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.572862287
Short name T523
Test name
Test status
Simulation time 6154992394 ps
CPU time 3.36 seconds
Started Jul 01 11:16:00 AM PDT 24
Finished Jul 01 11:17:23 AM PDT 24
Peak memory 201700 kb
Host smart-a7fb96b1-e51f-4f67-ae8d-c6715ef372e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572862287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.572862287
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1501225053
Short name T557
Test name
Test status
Simulation time 364045417791 ps
CPU time 179.08 seconds
Started Jul 01 11:16:11 AM PDT 24
Finished Jul 01 11:20:34 AM PDT 24
Peak memory 201880 kb
Host smart-cb5f21d8-404c-4e2b-9976-77d85c00e4f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501225053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1501225053
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2331293767
Short name T708
Test name
Test status
Simulation time 92667904073 ps
CPU time 218.89 seconds
Started Jul 01 11:16:11 AM PDT 24
Finished Jul 01 11:21:19 AM PDT 24
Peak memory 210524 kb
Host smart-9d5955a5-0a4d-41b6-8bf1-31fc39ef4530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331293767 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2331293767
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.316800068
Short name T536
Test name
Test status
Simulation time 422651554 ps
CPU time 1.02 seconds
Started Jul 01 11:16:17 AM PDT 24
Finished Jul 01 11:17:57 AM PDT 24
Peak memory 201632 kb
Host smart-c888ccff-1e71-470d-9709-877ba7cf4436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316800068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.316800068
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1808730918
Short name T234
Test name
Test status
Simulation time 172103306119 ps
CPU time 3.24 seconds
Started Jul 01 11:16:22 AM PDT 24
Finished Jul 01 11:17:54 AM PDT 24
Peak memory 201880 kb
Host smart-caf9c62a-e33f-445f-826d-03e493019b12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808730918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1808730918
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3114740832
Short name T285
Test name
Test status
Simulation time 164911853203 ps
CPU time 77.84 seconds
Started Jul 01 11:16:19 AM PDT 24
Finished Jul 01 11:18:58 AM PDT 24
Peak memory 201644 kb
Host smart-4ff4e3ec-a9fd-4edc-a02f-b73e30877048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114740832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3114740832
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2052213583
Short name T737
Test name
Test status
Simulation time 319987783679 ps
CPU time 197.88 seconds
Started Jul 01 11:16:12 AM PDT 24
Finished Jul 01 11:21:14 AM PDT 24
Peak memory 201892 kb
Host smart-9d801db1-9fcf-4565-8453-6b34127c49a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052213583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2052213583
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1617422197
Short name T365
Test name
Test status
Simulation time 323177062263 ps
CPU time 630.38 seconds
Started Jul 01 11:16:18 AM PDT 24
Finished Jul 01 11:28:10 AM PDT 24
Peak memory 201764 kb
Host smart-d3a6aca7-7066-4dfb-80d5-db0933934ed2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617422197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1617422197
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2185054883
Short name T134
Test name
Test status
Simulation time 489903679584 ps
CPU time 214.2 seconds
Started Jul 01 11:16:13 AM PDT 24
Finished Jul 01 11:21:24 AM PDT 24
Peak memory 201936 kb
Host smart-4b5586ff-c36f-4045-b4d2-342b918e86f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185054883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2185054883
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.853448675
Short name T382
Test name
Test status
Simulation time 484018351042 ps
CPU time 373.18 seconds
Started Jul 01 11:16:12 AM PDT 24
Finished Jul 01 11:23:48 AM PDT 24
Peak memory 201820 kb
Host smart-3f8c3995-6d6a-41a2-b8cc-b343f5f76c8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=853448675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.853448675
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.9930084
Short name T724
Test name
Test status
Simulation time 188364623405 ps
CPU time 400.62 seconds
Started Jul 01 11:16:18 AM PDT 24
Finished Jul 01 11:24:21 AM PDT 24
Peak memory 201888 kb
Host smart-b4226e82-0d09-4677-bb5d-67a7dfcc5c44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9930084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wa
keup.9930084
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2448906670
Short name T146
Test name
Test status
Simulation time 609177191937 ps
CPU time 237.59 seconds
Started Jul 01 11:16:18 AM PDT 24
Finished Jul 01 11:21:38 AM PDT 24
Peak memory 201912 kb
Host smart-825c81eb-6c30-47b2-a1cf-7b83dd52819a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448906670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2448906670
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.4066993528
Short name T730
Test name
Test status
Simulation time 116810301980 ps
CPU time 410.1 seconds
Started Jul 01 11:16:18 AM PDT 24
Finished Jul 01 11:24:30 AM PDT 24
Peak memory 202200 kb
Host smart-b51d2b99-c489-446e-8600-e409ec522ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066993528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.4066993528
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1432628765
Short name T341
Test name
Test status
Simulation time 32278577866 ps
CPU time 19.47 seconds
Started Jul 01 11:16:20 AM PDT 24
Finished Jul 01 11:18:00 AM PDT 24
Peak memory 201644 kb
Host smart-c0be1710-ab09-4a74-8769-9eae2b481719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432628765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1432628765
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1537048597
Short name T103
Test name
Test status
Simulation time 3692819449 ps
CPU time 2.78 seconds
Started Jul 01 11:16:19 AM PDT 24
Finished Jul 01 11:17:43 AM PDT 24
Peak memory 201488 kb
Host smart-80cdb4d3-efb5-4596-a960-57f04845acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537048597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1537048597
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3353619499
Short name T633
Test name
Test status
Simulation time 5868190234 ps
CPU time 8.02 seconds
Started Jul 01 11:16:11 AM PDT 24
Finished Jul 01 11:17:42 AM PDT 24
Peak memory 201692 kb
Host smart-03efc317-13a4-4f95-bc4b-70a1c41a80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353619499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3353619499
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.632294680
Short name T521
Test name
Test status
Simulation time 333765452640 ps
CPU time 740.44 seconds
Started Jul 01 11:16:22 AM PDT 24
Finished Jul 01 11:30:11 AM PDT 24
Peak memory 201872 kb
Host smart-90246cf6-3afe-43cf-8735-156448402a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632294680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
632294680
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1327805854
Short name T578
Test name
Test status
Simulation time 415312869 ps
CPU time 1.53 seconds
Started Jul 01 11:16:35 AM PDT 24
Finished Jul 01 11:17:58 AM PDT 24
Peak memory 201612 kb
Host smart-779d37b3-14f5-416d-a319-25435aa7be13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327805854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1327805854
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3386552647
Short name T245
Test name
Test status
Simulation time 165408903163 ps
CPU time 395.71 seconds
Started Jul 01 11:16:28 AM PDT 24
Finished Jul 01 11:24:33 AM PDT 24
Peak memory 201784 kb
Host smart-577487b3-7d35-4af1-9e61-07902c6addcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386552647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3386552647
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2089414518
Short name T316
Test name
Test status
Simulation time 518849303700 ps
CPU time 1147.78 seconds
Started Jul 01 11:16:27 AM PDT 24
Finished Jul 01 11:37:08 AM PDT 24
Peak memory 201904 kb
Host smart-5b892520-ffcb-49a1-a379-60b2fedb3740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089414518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2089414518
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1579224585
Short name T447
Test name
Test status
Simulation time 163468830998 ps
CPU time 34.47 seconds
Started Jul 01 11:16:23 AM PDT 24
Finished Jul 01 11:18:31 AM PDT 24
Peak memory 201788 kb
Host smart-a7c258cd-c4cc-4f39-92ec-85f176c0d8c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579224585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1579224585
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2537466877
Short name T186
Test name
Test status
Simulation time 493258089793 ps
CPU time 1134.32 seconds
Started Jul 01 11:16:23 AM PDT 24
Finished Jul 01 11:36:44 AM PDT 24
Peak memory 201852 kb
Host smart-751afe3f-b7ac-4f35-86be-65a1c5fea300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537466877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2537466877
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.352473459
Short name T466
Test name
Test status
Simulation time 335910457600 ps
CPU time 191.49 seconds
Started Jul 01 11:16:22 AM PDT 24
Finished Jul 01 11:21:01 AM PDT 24
Peak memory 201876 kb
Host smart-262ba26c-a8e2-4d3a-b971-3b0a55547509
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=352473459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.352473459
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2744174743
Short name T252
Test name
Test status
Simulation time 526583577816 ps
CPU time 1161.99 seconds
Started Jul 01 11:16:24 AM PDT 24
Finished Jul 01 11:37:19 AM PDT 24
Peak memory 201892 kb
Host smart-d1a12f52-fc84-4192-8465-0cc973e37189
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744174743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2744174743
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.154442847
Short name T46
Test name
Test status
Simulation time 590511445917 ps
CPU time 399.99 seconds
Started Jul 01 11:16:22 AM PDT 24
Finished Jul 01 11:24:30 AM PDT 24
Peak memory 201868 kb
Host smart-af6e635d-3d08-4264-9dc7-14826d624616
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154442847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.154442847
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1524497271
Short name T500
Test name
Test status
Simulation time 131052781591 ps
CPU time 450.34 seconds
Started Jul 01 11:16:34 AM PDT 24
Finished Jul 01 11:25:27 AM PDT 24
Peak memory 202176 kb
Host smart-21079d10-76f7-4e81-9ece-71465e3fd3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524497271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1524497271
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.350558938
Short name T692
Test name
Test status
Simulation time 24457375360 ps
CPU time 27.99 seconds
Started Jul 01 11:16:39 AM PDT 24
Finished Jul 01 11:18:28 AM PDT 24
Peak memory 201648 kb
Host smart-dd30d2e1-c27f-47a5-9fa5-0c825f833bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350558938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.350558938
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.500828186
Short name T374
Test name
Test status
Simulation time 4288575429 ps
CPU time 8.83 seconds
Started Jul 01 11:16:28 AM PDT 24
Finished Jul 01 11:18:03 AM PDT 24
Peak memory 201676 kb
Host smart-7f1b0780-bc4d-4be7-8a45-f6b94403f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500828186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.500828186
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2921257794
Short name T395
Test name
Test status
Simulation time 5638438825 ps
CPU time 15.39 seconds
Started Jul 01 11:16:17 AM PDT 24
Finished Jul 01 11:18:12 AM PDT 24
Peak memory 201660 kb
Host smart-ef96e0ce-435e-458e-9804-2659d3bf9b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921257794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2921257794
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1266770080
Short name T235
Test name
Test status
Simulation time 767732230116 ps
CPU time 775.65 seconds
Started Jul 01 11:16:34 AM PDT 24
Finished Jul 01 11:30:52 AM PDT 24
Peak memory 210324 kb
Host smart-320fd175-cd91-4cd1-b876-de6b1c7338f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266770080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1266770080
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2960429828
Short name T104
Test name
Test status
Simulation time 212477778529 ps
CPU time 266.96 seconds
Started Jul 01 11:16:33 AM PDT 24
Finished Jul 01 11:22:27 AM PDT 24
Peak memory 210404 kb
Host smart-6b62d676-220a-45ac-8334-cd75111fed94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960429828 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2960429828
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1618063395
Short name T375
Test name
Test status
Simulation time 532296016 ps
CPU time 1.82 seconds
Started Jul 01 11:14:18 AM PDT 24
Finished Jul 01 11:14:20 AM PDT 24
Peak memory 201640 kb
Host smart-32915982-885b-4815-b56e-575a22bddf62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618063395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1618063395
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1611697595
Short name T84
Test name
Test status
Simulation time 200250196533 ps
CPU time 72.76 seconds
Started Jul 01 11:14:07 AM PDT 24
Finished Jul 01 11:15:20 AM PDT 24
Peak memory 201908 kb
Host smart-44a560bf-53c9-47e1-b64d-a1b8583107c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611697595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1611697595
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3404309506
Short name T228
Test name
Test status
Simulation time 355503109274 ps
CPU time 385.86 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:20:27 AM PDT 24
Peak memory 201904 kb
Host smart-554a59cc-3d33-4ba5-a71b-d4258b126992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404309506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3404309506
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3202960408
Short name T226
Test name
Test status
Simulation time 493072025546 ps
CPU time 592.55 seconds
Started Jul 01 11:14:07 AM PDT 24
Finished Jul 01 11:24:00 AM PDT 24
Peak memory 201848 kb
Host smart-84ce779b-aff8-4776-a614-dde0173c961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202960408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3202960408
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3115299678
Short name T188
Test name
Test status
Simulation time 502440090075 ps
CPU time 319.56 seconds
Started Jul 01 11:14:08 AM PDT 24
Finished Jul 01 11:19:28 AM PDT 24
Peak memory 201848 kb
Host smart-db4633b8-711d-4fd8-b44a-500295bfe8bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115299678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3115299678
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3158698868
Short name T139
Test name
Test status
Simulation time 484076017130 ps
CPU time 720.64 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:26:26 AM PDT 24
Peak memory 201928 kb
Host smart-db07006f-3c13-4e41-92f9-923c636acda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158698868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3158698868
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.463644321
Short name T746
Test name
Test status
Simulation time 323479925419 ps
CPU time 303.42 seconds
Started Jul 01 11:14:00 AM PDT 24
Finished Jul 01 11:19:05 AM PDT 24
Peak memory 201920 kb
Host smart-9b258dc7-ca88-4f35-8e46-95e8425382ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=463644321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.463644321
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3257639357
Short name T567
Test name
Test status
Simulation time 170953773228 ps
CPU time 404.4 seconds
Started Jul 01 11:14:13 AM PDT 24
Finished Jul 01 11:20:58 AM PDT 24
Peak memory 201828 kb
Host smart-b0a2de18-52a2-44c6-834f-aa4153a84143
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257639357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3257639357
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3827918813
Short name T418
Test name
Test status
Simulation time 395443031132 ps
CPU time 434.77 seconds
Started Jul 01 11:14:09 AM PDT 24
Finished Jul 01 11:21:24 AM PDT 24
Peak memory 201848 kb
Host smart-a8cadc55-a844-4384-8aef-270f420d436e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827918813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3827918813
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1486819941
Short name T696
Test name
Test status
Simulation time 104595404945 ps
CPU time 369.44 seconds
Started Jul 01 11:14:37 AM PDT 24
Finished Jul 01 11:20:47 AM PDT 24
Peak memory 202376 kb
Host smart-4f512979-3aa1-448c-94ac-da192e1dad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486819941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1486819941
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3287465004
Short name T546
Test name
Test status
Simulation time 27738885739 ps
CPU time 15.61 seconds
Started Jul 01 11:14:07 AM PDT 24
Finished Jul 01 11:14:23 AM PDT 24
Peak memory 201680 kb
Host smart-4494e8e3-aeea-4f96-93bb-f89819e126c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287465004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3287465004
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.204183054
Short name T455
Test name
Test status
Simulation time 4708548509 ps
CPU time 11.16 seconds
Started Jul 01 11:14:04 AM PDT 24
Finished Jul 01 11:14:16 AM PDT 24
Peak memory 201700 kb
Host smart-9abb57bc-2caf-4ba4-bcdd-5d61adc6c6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204183054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.204183054
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1668764280
Short name T61
Test name
Test status
Simulation time 8017619306 ps
CPU time 10.52 seconds
Started Jul 01 11:14:09 AM PDT 24
Finished Jul 01 11:14:20 AM PDT 24
Peak memory 218192 kb
Host smart-3e5b44af-7605-4169-9b8c-6336895d0055
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668764280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1668764280
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2067744035
Short name T533
Test name
Test status
Simulation time 5898666878 ps
CPU time 4.28 seconds
Started Jul 01 11:14:13 AM PDT 24
Finished Jul 01 11:14:18 AM PDT 24
Peak memory 201708 kb
Host smart-48dfce08-2213-47c0-9c5e-0d4402355718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067744035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2067744035
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.460134255
Short name T275
Test name
Test status
Simulation time 202335636555 ps
CPU time 117.85 seconds
Started Jul 01 11:14:09 AM PDT 24
Finished Jul 01 11:16:08 AM PDT 24
Peak memory 201932 kb
Host smart-22a134a9-4b92-46a7-8dce-34d8a732ba04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460134255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.460134255
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3249833456
Short name T101
Test name
Test status
Simulation time 25911141240 ps
CPU time 16.05 seconds
Started Jul 01 11:14:06 AM PDT 24
Finished Jul 01 11:14:22 AM PDT 24
Peak memory 210252 kb
Host smart-db00dbd5-da6d-4ac9-99f5-2bb3b22ede6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249833456 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3249833456
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1701868697
Short name T661
Test name
Test status
Simulation time 428554045 ps
CPU time 1.55 seconds
Started Jul 01 11:16:39 AM PDT 24
Finished Jul 01 11:18:02 AM PDT 24
Peak memory 201612 kb
Host smart-63600458-d6cb-42de-b0c3-977b1f1e15c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701868697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1701868697
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1574790267
Short name T218
Test name
Test status
Simulation time 341100454718 ps
CPU time 343.06 seconds
Started Jul 01 11:16:35 AM PDT 24
Finished Jul 01 11:23:40 AM PDT 24
Peak memory 201852 kb
Host smart-9c54656a-f9db-4a44-bef6-d0acb657ad08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574790267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1574790267
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3748489771
Short name T467
Test name
Test status
Simulation time 332893156546 ps
CPU time 220.08 seconds
Started Jul 01 11:16:39 AM PDT 24
Finished Jul 01 11:21:40 AM PDT 24
Peak memory 201852 kb
Host smart-f1f55a5d-cb8a-43d7-82d6-13cfdc93bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748489771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3748489771
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3597430812
Short name T524
Test name
Test status
Simulation time 330914094553 ps
CPU time 202.89 seconds
Started Jul 01 11:16:34 AM PDT 24
Finished Jul 01 11:21:19 AM PDT 24
Peak memory 201852 kb
Host smart-448d3022-28bd-4c73-af4f-fab1a260d1d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597430812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3597430812
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.4178264867
Short name T690
Test name
Test status
Simulation time 164176193662 ps
CPU time 176.19 seconds
Started Jul 01 11:16:33 AM PDT 24
Finished Jul 01 11:21:03 AM PDT 24
Peak memory 201792 kb
Host smart-59a414ad-a5a6-445b-8928-77dde6c46065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178264867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.4178264867
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.571888721
Short name T381
Test name
Test status
Simulation time 481544009939 ps
CPU time 1164.99 seconds
Started Jul 01 11:16:33 AM PDT 24
Finished Jul 01 11:37:32 AM PDT 24
Peak memory 201812 kb
Host smart-8adb823a-d0a7-4cc7-897f-ec721d97927b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=571888721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.571888721
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1798392617
Short name T302
Test name
Test status
Simulation time 646246348644 ps
CPU time 1507.03 seconds
Started Jul 01 11:16:33 AM PDT 24
Finished Jul 01 11:43:11 AM PDT 24
Peak memory 201880 kb
Host smart-818fb42e-eb38-4966-97c3-da876ce500a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798392617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1798392617
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3789897212
Short name T383
Test name
Test status
Simulation time 197434401431 ps
CPU time 108.87 seconds
Started Jul 01 11:16:34 AM PDT 24
Finished Jul 01 11:19:45 AM PDT 24
Peak memory 202060 kb
Host smart-f2365305-3c52-4a16-be6d-46409dae3e1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789897212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3789897212
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2471484888
Short name T3
Test name
Test status
Simulation time 36243518474 ps
CPU time 21.61 seconds
Started Jul 01 11:16:37 AM PDT 24
Finished Jul 01 11:18:30 AM PDT 24
Peak memory 201668 kb
Host smart-dd407055-ee26-45e1-84c6-109cb378e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471484888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2471484888
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4078149589
Short name T102
Test name
Test status
Simulation time 5068953593 ps
CPU time 11.65 seconds
Started Jul 01 11:16:38 AM PDT 24
Finished Jul 01 11:18:11 AM PDT 24
Peak memory 201680 kb
Host smart-b47310f5-c500-4ffe-bd3a-f16890dab50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078149589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4078149589
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1210313111
Short name T642
Test name
Test status
Simulation time 5654277962 ps
CPU time 10.51 seconds
Started Jul 01 11:16:34 AM PDT 24
Finished Jul 01 11:18:10 AM PDT 24
Peak memory 201652 kb
Host smart-6766fc63-7c4e-4eda-a20a-da213c9905c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210313111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1210313111
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.247062157
Short name T205
Test name
Test status
Simulation time 140171913755 ps
CPU time 467.36 seconds
Started Jul 01 11:16:37 AM PDT 24
Finished Jul 01 11:25:55 AM PDT 24
Peak memory 210360 kb
Host smart-d65018e0-64aa-4d3d-971d-3d48f87e0ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247062157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
247062157
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3959643359
Short name T20
Test name
Test status
Simulation time 141061828122 ps
CPU time 215.89 seconds
Started Jul 01 11:16:39 AM PDT 24
Finished Jul 01 11:21:36 AM PDT 24
Peak memory 217884 kb
Host smart-af36ce14-d321-4bb3-91b2-ad44f4388ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959643359 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3959643359
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.88516694
Short name T538
Test name
Test status
Simulation time 383560105 ps
CPU time 1.05 seconds
Started Jul 01 11:18:03 AM PDT 24
Finished Jul 01 11:18:22 AM PDT 24
Peak memory 201532 kb
Host smart-304a1eb5-c65f-4c4e-867b-ca66abac7ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88516694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.88516694
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.4089328279
Short name T177
Test name
Test status
Simulation time 329630023535 ps
CPU time 216.5 seconds
Started Jul 01 11:18:02 AM PDT 24
Finished Jul 01 11:21:58 AM PDT 24
Peak memory 201864 kb
Host smart-ba7632a5-2d8e-495b-9253-6d17972e35f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089328279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.4089328279
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1879389911
Short name T522
Test name
Test status
Simulation time 164663804182 ps
CPU time 82.1 seconds
Started Jul 01 11:16:45 AM PDT 24
Finished Jul 01 11:19:22 AM PDT 24
Peak memory 201944 kb
Host smart-3ef677b6-47a0-4bb0-adcb-1dc2c37b8856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879389911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1879389911
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.664012076
Short name T679
Test name
Test status
Simulation time 496029658634 ps
CPU time 582.4 seconds
Started Jul 01 11:16:43 AM PDT 24
Finished Jul 01 11:27:46 AM PDT 24
Peak memory 201932 kb
Host smart-42204c38-77b3-46bf-83a5-18ea3c2a79c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664012076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.664012076
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3557734648
Short name T89
Test name
Test status
Simulation time 161654760182 ps
CPU time 83.05 seconds
Started Jul 01 11:16:46 AM PDT 24
Finished Jul 01 11:19:27 AM PDT 24
Peak memory 201808 kb
Host smart-ea17443d-43d1-4589-8559-1b957da2d6f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557734648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3557734648
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1086692098
Short name T173
Test name
Test status
Simulation time 159750264580 ps
CPU time 103.81 seconds
Started Jul 01 11:16:44 AM PDT 24
Finished Jul 01 11:19:44 AM PDT 24
Peak memory 201824 kb
Host smart-f3dfa4a0-6795-4d7d-88fe-53981992bbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086692098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1086692098
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1251023080
Short name T769
Test name
Test status
Simulation time 491796392805 ps
CPU time 537.38 seconds
Started Jul 01 11:16:42 AM PDT 24
Finished Jul 01 11:27:05 AM PDT 24
Peak memory 201776 kb
Host smart-7c23fb84-eade-4eb6-baa8-7be63de25c32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251023080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1251023080
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1430826601
Short name T166
Test name
Test status
Simulation time 380369661708 ps
CPU time 507.69 seconds
Started Jul 01 11:16:44 AM PDT 24
Finished Jul 01 11:26:28 AM PDT 24
Peak memory 201832 kb
Host smart-b1432ff2-66c3-40d9-b42d-6752651fc3ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430826601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1430826601
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2844071269
Short name T624
Test name
Test status
Simulation time 206811120626 ps
CPU time 481.66 seconds
Started Jul 01 11:16:45 AM PDT 24
Finished Jul 01 11:26:06 AM PDT 24
Peak memory 201848 kb
Host smart-3655c45d-1da6-4a26-b061-cde160f9cf03
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844071269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2844071269
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3416901441
Short name T645
Test name
Test status
Simulation time 92549616821 ps
CPU time 393.87 seconds
Started Jul 01 11:16:50 AM PDT 24
Finished Jul 01 11:24:42 AM PDT 24
Peak memory 202208 kb
Host smart-8e64110c-9139-429e-bbf4-d50259536f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416901441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3416901441
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.935307420
Short name T502
Test name
Test status
Simulation time 45498754229 ps
CPU time 104.3 seconds
Started Jul 01 11:17:55 AM PDT 24
Finished Jul 01 11:20:04 AM PDT 24
Peak memory 201668 kb
Host smart-3867cb24-5dff-423a-bb41-a37fbfa98fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935307420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.935307420
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1661146362
Short name T491
Test name
Test status
Simulation time 3421363599 ps
CPU time 1.49 seconds
Started Jul 01 11:16:45 AM PDT 24
Finished Jul 01 11:18:14 AM PDT 24
Peak memory 201700 kb
Host smart-0d378aef-0791-4ae4-b3b4-e38c66c7c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661146362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1661146362
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.746982567
Short name T537
Test name
Test status
Simulation time 5777387589 ps
CPU time 12.1 seconds
Started Jul 01 11:16:40 AM PDT 24
Finished Jul 01 11:18:12 AM PDT 24
Peak memory 201652 kb
Host smart-2f8279ce-4260-4dfc-a220-3d51f1a01fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746982567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.746982567
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1784242506
Short name T773
Test name
Test status
Simulation time 276931507912 ps
CPU time 451.31 seconds
Started Jul 01 11:16:52 AM PDT 24
Finished Jul 01 11:25:35 AM PDT 24
Peak memory 212860 kb
Host smart-c72a427f-d8f2-4ad5-a651-b87c594ecd3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784242506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1784242506
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3348370263
Short name T86
Test name
Test status
Simulation time 137882078870 ps
CPU time 253.98 seconds
Started Jul 01 11:17:56 AM PDT 24
Finished Jul 01 11:22:34 AM PDT 24
Peak memory 210432 kb
Host smart-c6bca975-2cc0-4688-a9db-4cb7247d888b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348370263 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3348370263
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1665521064
Short name T510
Test name
Test status
Simulation time 421848630 ps
CPU time 1.53 seconds
Started Jul 01 11:17:04 AM PDT 24
Finished Jul 01 11:18:11 AM PDT 24
Peak memory 201644 kb
Host smart-b3e1ffd0-cd2b-4a2a-b442-6c4a01a287a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665521064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1665521064
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2313545897
Short name T178
Test name
Test status
Simulation time 165178509715 ps
CPU time 3.72 seconds
Started Jul 01 11:16:56 AM PDT 24
Finished Jul 01 11:18:16 AM PDT 24
Peak memory 201788 kb
Host smart-058a9536-e046-4d87-897a-e5c2ec8fe011
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313545897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2313545897
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1765314480
Short name T301
Test name
Test status
Simulation time 349694827216 ps
CPU time 723.72 seconds
Started Jul 01 11:16:57 AM PDT 24
Finished Jul 01 11:30:11 AM PDT 24
Peak memory 201828 kb
Host smart-35db1bde-99cb-4b0f-bb79-3e129b6fc298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765314480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1765314480
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.447429341
Short name T426
Test name
Test status
Simulation time 166976576461 ps
CPU time 199.49 seconds
Started Jul 01 11:16:56 AM PDT 24
Finished Jul 01 11:21:29 AM PDT 24
Peak memory 201840 kb
Host smart-4d5dfc62-fbf6-4872-b3ec-bfa51b67ee1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=447429341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.447429341
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4193062664
Short name T325
Test name
Test status
Simulation time 326036186873 ps
CPU time 200.68 seconds
Started Jul 01 11:16:50 AM PDT 24
Finished Jul 01 11:21:31 AM PDT 24
Peak memory 201976 kb
Host smart-99b72f51-6b5b-475b-ac2f-82d93cea99ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193062664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4193062664
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.611108649
Short name T670
Test name
Test status
Simulation time 327549353311 ps
CPU time 770.69 seconds
Started Jul 01 11:17:02 AM PDT 24
Finished Jul 01 11:31:03 AM PDT 24
Peak memory 201940 kb
Host smart-f9cde899-c058-4502-9c25-cba92af148f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=611108649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.611108649
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1063283543
Short name T780
Test name
Test status
Simulation time 557386657207 ps
CPU time 322.09 seconds
Started Jul 01 11:17:10 AM PDT 24
Finished Jul 01 11:23:34 AM PDT 24
Peak memory 201940 kb
Host smart-0b46bd27-ce53-409b-8ea4-7208aa35f3f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063283543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1063283543
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.837473570
Short name T548
Test name
Test status
Simulation time 192643605292 ps
CPU time 117.22 seconds
Started Jul 01 11:17:09 AM PDT 24
Finished Jul 01 11:20:10 AM PDT 24
Peak memory 201840 kb
Host smart-066ae6d1-7c54-4111-8d0b-077247d82e9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837473570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.837473570
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.218206792
Short name T206
Test name
Test status
Simulation time 95049181779 ps
CPU time 383.48 seconds
Started Jul 01 11:16:56 AM PDT 24
Finished Jul 01 11:24:31 AM PDT 24
Peak memory 202224 kb
Host smart-3ff9f416-d3ad-45a5-b4a1-11c2f9eeabdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218206792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.218206792
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2296428197
Short name T697
Test name
Test status
Simulation time 23572952033 ps
CPU time 26.27 seconds
Started Jul 01 11:17:08 AM PDT 24
Finished Jul 01 11:18:38 AM PDT 24
Peak memory 201680 kb
Host smart-efb5449e-4f8c-40a3-a30c-4cbecfde744e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296428197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2296428197
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2850525446
Short name T354
Test name
Test status
Simulation time 4728495868 ps
CPU time 2.67 seconds
Started Jul 01 11:16:58 AM PDT 24
Finished Jul 01 11:18:15 AM PDT 24
Peak memory 201560 kb
Host smart-94708d31-4b69-4e0a-8b9c-95cba2f5bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850525446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2850525446
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.13313713
Short name T574
Test name
Test status
Simulation time 5570270458 ps
CPU time 7.51 seconds
Started Jul 01 11:17:03 AM PDT 24
Finished Jul 01 11:18:20 AM PDT 24
Peak memory 201676 kb
Host smart-ca65a443-e623-485b-a424-3383a0175953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13313713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.13313713
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3057457597
Short name T31
Test name
Test status
Simulation time 95555357083 ps
CPU time 469.19 seconds
Started Jul 01 11:17:08 AM PDT 24
Finished Jul 01 11:26:01 AM PDT 24
Peak memory 202164 kb
Host smart-04f18731-246b-47d7-b725-8820738aa3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057457597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3057457597
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3116389972
Short name T298
Test name
Test status
Simulation time 84300010795 ps
CPU time 207.58 seconds
Started Jul 01 11:17:09 AM PDT 24
Finished Jul 01 11:21:40 AM PDT 24
Peak memory 211700 kb
Host smart-f408e921-0887-4278-a5c0-fde6462fb88f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116389972 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3116389972
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4079307767
Short name T653
Test name
Test status
Simulation time 478447900 ps
CPU time 0.87 seconds
Started Jul 01 11:17:12 AM PDT 24
Finished Jul 01 11:18:14 AM PDT 24
Peak memory 201632 kb
Host smart-80124ff3-5980-41de-8692-84651e2b0e7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079307767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4079307767
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1475075486
Short name T621
Test name
Test status
Simulation time 159819017302 ps
CPU time 91.67 seconds
Started Jul 01 11:17:07 AM PDT 24
Finished Jul 01 11:19:44 AM PDT 24
Peak memory 201916 kb
Host smart-be43a6fe-2761-4232-af53-d7da37865e7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475075486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1475075486
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3885455049
Short name T781
Test name
Test status
Simulation time 350932933209 ps
CPU time 798.9 seconds
Started Jul 01 11:17:06 AM PDT 24
Finished Jul 01 11:31:28 AM PDT 24
Peak memory 201876 kb
Host smart-c00fe4bc-d299-474f-bfa9-25882ea6752b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885455049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3885455049
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3995333308
Short name T579
Test name
Test status
Simulation time 163647850169 ps
CPU time 102.38 seconds
Started Jul 01 11:16:58 AM PDT 24
Finished Jul 01 11:19:50 AM PDT 24
Peak memory 201796 kb
Host smart-814d84d9-4029-408f-957f-60f8268a1088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995333308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3995333308
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1880088565
Short name T754
Test name
Test status
Simulation time 161418947493 ps
CPU time 334.19 seconds
Started Jul 01 11:17:02 AM PDT 24
Finished Jul 01 11:23:47 AM PDT 24
Peak memory 201832 kb
Host smart-8cd33d85-4be8-4ee5-897f-a601111f0d7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880088565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1880088565
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3441185565
Short name T757
Test name
Test status
Simulation time 499841776337 ps
CPU time 158.95 seconds
Started Jul 01 11:16:59 AM PDT 24
Finished Jul 01 11:20:47 AM PDT 24
Peak memory 201944 kb
Host smart-29a4e548-10dd-4712-ac48-9ec3445b5ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441185565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3441185565
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2947998137
Short name T429
Test name
Test status
Simulation time 485117488394 ps
CPU time 1118.83 seconds
Started Jul 01 11:16:58 AM PDT 24
Finished Jul 01 11:36:46 AM PDT 24
Peak memory 201828 kb
Host smart-25f117d3-4871-49d0-99fe-9795055fc3de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947998137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2947998137
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1449851638
Short name T763
Test name
Test status
Simulation time 189544648292 ps
CPU time 83.52 seconds
Started Jul 01 11:17:05 AM PDT 24
Finished Jul 01 11:19:38 AM PDT 24
Peak memory 201932 kb
Host smart-cde9dc78-eadf-48a8-a464-8690af40b1c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449851638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1449851638
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.155747800
Short name T607
Test name
Test status
Simulation time 589213670543 ps
CPU time 1237.25 seconds
Started Jul 01 11:17:06 AM PDT 24
Finished Jul 01 11:38:49 AM PDT 24
Peak memory 201876 kb
Host smart-b6817935-9a2e-4a4f-96a6-0a97ba9b1a78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155747800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.155747800
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2380938764
Short name T509
Test name
Test status
Simulation time 119689905214 ps
CPU time 658.29 seconds
Started Jul 01 11:17:06 AM PDT 24
Finished Jul 01 11:29:08 AM PDT 24
Peak memory 202200 kb
Host smart-a12d1a55-d975-4755-8912-d8163ff9287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380938764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2380938764
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2194631531
Short name T590
Test name
Test status
Simulation time 45080021247 ps
CPU time 22.9 seconds
Started Jul 01 11:17:07 AM PDT 24
Finished Jul 01 11:18:32 AM PDT 24
Peak memory 201664 kb
Host smart-a3053314-aab1-41ec-b898-ebc663d46c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194631531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2194631531
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4270483591
Short name T627
Test name
Test status
Simulation time 4233649346 ps
CPU time 1.15 seconds
Started Jul 01 11:16:58 AM PDT 24
Finished Jul 01 11:18:16 AM PDT 24
Peak memory 201680 kb
Host smart-6f188a33-8e81-45ef-bf73-8dfa8185dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270483591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4270483591
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2879385677
Short name T496
Test name
Test status
Simulation time 5867857356 ps
CPU time 13.94 seconds
Started Jul 01 11:17:03 AM PDT 24
Finished Jul 01 11:18:26 AM PDT 24
Peak memory 201664 kb
Host smart-62845a4e-6048-40a9-9639-e444cabf2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879385677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2879385677
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1365790876
Short name T32
Test name
Test status
Simulation time 13686698985 ps
CPU time 30.54 seconds
Started Jul 01 11:17:13 AM PDT 24
Finished Jul 01 11:18:45 AM PDT 24
Peak memory 202056 kb
Host smart-d558141f-ffcc-4a43-b436-a0324b346f31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365790876 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1365790876
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.26993768
Short name T495
Test name
Test status
Simulation time 499003176 ps
CPU time 1.39 seconds
Started Jul 01 11:17:21 AM PDT 24
Finished Jul 01 11:18:14 AM PDT 24
Peak memory 201628 kb
Host smart-64b65356-634e-4bb2-9d2f-06f4e3a43ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26993768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.26993768
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1546110968
Short name T329
Test name
Test status
Simulation time 164393412040 ps
CPU time 55.4 seconds
Started Jul 01 11:17:17 AM PDT 24
Finished Jul 01 11:19:07 AM PDT 24
Peak memory 201872 kb
Host smart-b05162ba-a5c7-4382-b779-45068b3387bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546110968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1546110968
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.791394958
Short name T727
Test name
Test status
Simulation time 495569253021 ps
CPU time 122.75 seconds
Started Jul 01 11:18:24 AM PDT 24
Finished Jul 01 11:20:29 AM PDT 24
Peak memory 201856 kb
Host smart-3f33adfb-840b-4616-b069-70016e269391
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=791394958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.791394958
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.126254694
Short name T229
Test name
Test status
Simulation time 333619002720 ps
CPU time 760.84 seconds
Started Jul 01 11:17:13 AM PDT 24
Finished Jul 01 11:30:53 AM PDT 24
Peak memory 201864 kb
Host smart-a56ce145-3ec3-4fa2-a0b0-56ec32832a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126254694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.126254694
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3808242578
Short name T401
Test name
Test status
Simulation time 498512237454 ps
CPU time 579.16 seconds
Started Jul 01 11:17:12 AM PDT 24
Finished Jul 01 11:27:52 AM PDT 24
Peak memory 201864 kb
Host smart-092ebc20-7a81-4d03-91d9-bc6c1f3c6976
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808242578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3808242578
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4103562985
Short name T744
Test name
Test status
Simulation time 179827214152 ps
CPU time 109.5 seconds
Started Jul 01 11:18:24 AM PDT 24
Finished Jul 01 11:20:15 AM PDT 24
Peak memory 201928 kb
Host smart-e65c181f-013b-4566-85ca-b155e8cbd9b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103562985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4103562985
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3835700887
Short name T603
Test name
Test status
Simulation time 616020875341 ps
CPU time 147.05 seconds
Started Jul 01 11:17:17 AM PDT 24
Finished Jul 01 11:20:38 AM PDT 24
Peak memory 201860 kb
Host smart-cdb83c76-cec7-44cb-a805-09d0e065bb44
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835700887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3835700887
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2093312164
Short name T337
Test name
Test status
Simulation time 127608752983 ps
CPU time 429.13 seconds
Started Jul 01 11:17:17 AM PDT 24
Finished Jul 01 11:25:21 AM PDT 24
Peak memory 202200 kb
Host smart-40a54ac5-1687-4e17-973e-46cce165f560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093312164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2093312164
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3131392065
Short name T344
Test name
Test status
Simulation time 39116198592 ps
CPU time 42.51 seconds
Started Jul 01 11:17:17 AM PDT 24
Finished Jul 01 11:18:54 AM PDT 24
Peak memory 201696 kb
Host smart-1bc072a3-b54f-4c17-afd8-e8b4a80f765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131392065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3131392065
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.553712391
Short name T439
Test name
Test status
Simulation time 5493713237 ps
CPU time 3.88 seconds
Started Jul 01 11:17:19 AM PDT 24
Finished Jul 01 11:18:16 AM PDT 24
Peak memory 201604 kb
Host smart-f1fdb03b-4376-459c-8bad-b4ee5df070a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553712391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.553712391
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1703343079
Short name T482
Test name
Test status
Simulation time 5892067124 ps
CPU time 12.03 seconds
Started Jul 01 11:17:11 AM PDT 24
Finished Jul 01 11:18:27 AM PDT 24
Peak memory 201668 kb
Host smart-dfd3b550-7d39-49ee-bd1d-9acd251735cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703343079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1703343079
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3455159374
Short name T513
Test name
Test status
Simulation time 385348052703 ps
CPU time 442.94 seconds
Started Jul 01 11:17:30 AM PDT 24
Finished Jul 01 11:25:39 AM PDT 24
Peak memory 210576 kb
Host smart-aff81cc5-10eb-4dda-bd59-4126f838b4b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455159374 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3455159374
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3609183904
Short name T641
Test name
Test status
Simulation time 460914544 ps
CPU time 1.6 seconds
Started Jul 01 11:17:29 AM PDT 24
Finished Jul 01 11:18:17 AM PDT 24
Peak memory 201512 kb
Host smart-8472b3ee-019f-4a64-bea5-c5438ad4e028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609183904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3609183904
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.174931554
Short name T563
Test name
Test status
Simulation time 337187022207 ps
CPU time 174.75 seconds
Started Jul 01 11:17:27 AM PDT 24
Finished Jul 01 11:21:09 AM PDT 24
Peak memory 201844 kb
Host smart-975f88ac-5fa7-441f-a092-13725165a589
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174931554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.174931554
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3469204006
Short name T680
Test name
Test status
Simulation time 158585966755 ps
CPU time 339.98 seconds
Started Jul 01 11:17:28 AM PDT 24
Finished Jul 01 11:23:55 AM PDT 24
Peak memory 201872 kb
Host smart-3ca8ba7c-cf9f-4718-8f0c-2074322739aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469204006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3469204006
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2551263797
Short name T328
Test name
Test status
Simulation time 337542711690 ps
CPU time 816.29 seconds
Started Jul 01 11:17:30 AM PDT 24
Finished Jul 01 11:31:52 AM PDT 24
Peak memory 201836 kb
Host smart-7c9e2c3f-3ca3-4038-8100-5d683465af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551263797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2551263797
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1380985288
Short name T26
Test name
Test status
Simulation time 328508093864 ps
CPU time 194.64 seconds
Started Jul 01 11:17:28 AM PDT 24
Finished Jul 01 11:21:29 AM PDT 24
Peak memory 201848 kb
Host smart-c59dfdeb-c6ed-4438-9c1b-c29655868957
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380985288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1380985288
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1470686865
Short name T464
Test name
Test status
Simulation time 492797669140 ps
CPU time 302.25 seconds
Started Jul 01 11:17:21 AM PDT 24
Finished Jul 01 11:23:17 AM PDT 24
Peak memory 201960 kb
Host smart-f555a9cb-9c00-488d-8f38-315f24f104c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470686865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1470686865
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3695085449
Short name T459
Test name
Test status
Simulation time 326996456845 ps
CPU time 716.37 seconds
Started Jul 01 11:17:27 AM PDT 24
Finished Jul 01 11:30:11 AM PDT 24
Peak memory 201900 kb
Host smart-66cecf6d-6f3e-4b70-b212-0bae45328d00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695085449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3695085449
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.563370884
Short name T269
Test name
Test status
Simulation time 161726338714 ps
CPU time 91.69 seconds
Started Jul 01 11:17:33 AM PDT 24
Finished Jul 01 11:19:49 AM PDT 24
Peak memory 201888 kb
Host smart-f96dab53-3691-4625-92fc-5bf7ab913a0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563370884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.563370884
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1586003314
Short name T442
Test name
Test status
Simulation time 393041021893 ps
CPU time 818.33 seconds
Started Jul 01 11:17:29 AM PDT 24
Finished Jul 01 11:31:54 AM PDT 24
Peak memory 201772 kb
Host smart-ae4ffdc7-9d48-4bd9-8441-c1ed3e4f3417
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586003314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1586003314
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.832537888
Short name T204
Test name
Test status
Simulation time 103503917689 ps
CPU time 397.47 seconds
Started Jul 01 11:17:26 AM PDT 24
Finished Jul 01 11:24:52 AM PDT 24
Peak memory 202172 kb
Host smart-0628295d-7e1f-4a14-9f64-a1b707788412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832537888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.832537888
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.660535255
Short name T611
Test name
Test status
Simulation time 42357333783 ps
CPU time 99.65 seconds
Started Jul 01 11:17:28 AM PDT 24
Finished Jul 01 11:19:54 AM PDT 24
Peak memory 201676 kb
Host smart-b335e207-d0b3-44bf-90d7-349776534e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660535255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.660535255
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1905485383
Short name T184
Test name
Test status
Simulation time 2731211903 ps
CPU time 3.83 seconds
Started Jul 01 11:17:28 AM PDT 24
Finished Jul 01 11:18:18 AM PDT 24
Peak memory 201664 kb
Host smart-f0fa38a3-94fa-48ea-a4e5-823ade0858ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905485383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1905485383
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3301872619
Short name T449
Test name
Test status
Simulation time 5834793611 ps
CPU time 4.13 seconds
Started Jul 01 11:17:28 AM PDT 24
Finished Jul 01 11:18:19 AM PDT 24
Peak memory 201692 kb
Host smart-f4923579-ba4d-4461-bca8-397b6e1a3205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301872619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3301872619
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3579152111
Short name T622
Test name
Test status
Simulation time 656582812925 ps
CPU time 541.87 seconds
Started Jul 01 11:17:28 AM PDT 24
Finished Jul 01 11:27:17 AM PDT 24
Peak memory 201876 kb
Host smart-b4f6fc12-439a-4644-858c-d70efee8637e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579152111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3579152111
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2883131627
Short name T571
Test name
Test status
Simulation time 153789129156 ps
CPU time 199.44 seconds
Started Jul 01 11:17:35 AM PDT 24
Finished Jul 01 11:21:37 AM PDT 24
Peak memory 218660 kb
Host smart-bc8207b1-9b7a-4be2-8f58-53ede13cfef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883131627 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2883131627
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3616887415
Short name T370
Test name
Test status
Simulation time 327949727 ps
CPU time 0.79 seconds
Started Jul 01 11:17:43 AM PDT 24
Finished Jul 01 11:18:19 AM PDT 24
Peak memory 201632 kb
Host smart-d5c88190-7b29-43de-9871-1cb41b162d23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616887415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3616887415
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1097146483
Short name T748
Test name
Test status
Simulation time 352224944074 ps
CPU time 254.62 seconds
Started Jul 01 11:17:33 AM PDT 24
Finished Jul 01 11:22:32 AM PDT 24
Peak memory 201768 kb
Host smart-2f537b8d-2c5c-43b1-804c-4679cfa443dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097146483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1097146483
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.761276371
Short name T720
Test name
Test status
Simulation time 354292562044 ps
CPU time 229.59 seconds
Started Jul 01 11:17:34 AM PDT 24
Finished Jul 01 11:22:07 AM PDT 24
Peak memory 201900 kb
Host smart-83cd8031-d624-489a-bc89-c18e2af27e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761276371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.761276371
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2178254492
Short name T515
Test name
Test status
Simulation time 499718652999 ps
CPU time 301.79 seconds
Started Jul 01 11:17:37 AM PDT 24
Finished Jul 01 11:23:20 AM PDT 24
Peak memory 201812 kb
Host smart-bcc73d5d-fef8-44cc-bcc0-0bce97ed01b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178254492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2178254492
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.872546692
Short name T462
Test name
Test status
Simulation time 322033660242 ps
CPU time 740.72 seconds
Started Jul 01 11:17:35 AM PDT 24
Finished Jul 01 11:30:38 AM PDT 24
Peak memory 201784 kb
Host smart-6007e52f-ad03-4a30-a563-2c0ea821cda2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=872546692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.872546692
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.960687439
Short name T294
Test name
Test status
Simulation time 492178371009 ps
CPU time 535.2 seconds
Started Jul 01 11:17:34 AM PDT 24
Finished Jul 01 11:27:12 AM PDT 24
Peak memory 201940 kb
Host smart-08a33e23-6541-4c80-877c-f7a91ac39f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960687439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.960687439
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2081434855
Short name T505
Test name
Test status
Simulation time 333784627820 ps
CPU time 408.3 seconds
Started Jul 01 11:17:34 AM PDT 24
Finished Jul 01 11:25:05 AM PDT 24
Peak memory 201848 kb
Host smart-eab0ae57-89f5-4b9e-a86f-7af230c9d4b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081434855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2081434855
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3681187170
Short name T583
Test name
Test status
Simulation time 197040352346 ps
CPU time 230.1 seconds
Started Jul 01 11:17:34 AM PDT 24
Finished Jul 01 11:22:08 AM PDT 24
Peak memory 201960 kb
Host smart-5d767b69-bd47-4dbd-8b86-1d4ee8ab04ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681187170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3681187170
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1042956046
Short name T516
Test name
Test status
Simulation time 191909180668 ps
CPU time 222.68 seconds
Started Jul 01 11:17:36 AM PDT 24
Finished Jul 01 11:22:01 AM PDT 24
Peak memory 201812 kb
Host smart-2aa3d575-2163-4b37-979e-66c859896ac3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042956046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1042956046
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1991230341
Short name T562
Test name
Test status
Simulation time 35057246669 ps
CPU time 21.45 seconds
Started Jul 01 11:17:36 AM PDT 24
Finished Jul 01 11:18:40 AM PDT 24
Peak memory 201636 kb
Host smart-8f809e13-c36d-4884-aff4-de5319fc69ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991230341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1991230341
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3742821569
Short name T388
Test name
Test status
Simulation time 4549853026 ps
CPU time 3.31 seconds
Started Jul 01 11:17:35 AM PDT 24
Finished Jul 01 11:18:21 AM PDT 24
Peak memory 201612 kb
Host smart-7fb34f86-4aa6-493b-86bc-4734ec29da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742821569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3742821569
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1453410686
Short name T440
Test name
Test status
Simulation time 5866989424 ps
CPU time 1.85 seconds
Started Jul 01 11:17:36 AM PDT 24
Finished Jul 01 11:18:20 AM PDT 24
Peak memory 201612 kb
Host smart-5c1276bb-e6e2-418a-a3fb-f71465e11b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453410686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1453410686
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1652925829
Short name T739
Test name
Test status
Simulation time 330096606061 ps
CPU time 726.33 seconds
Started Jul 01 11:17:43 AM PDT 24
Finished Jul 01 11:30:25 AM PDT 24
Peak memory 201824 kb
Host smart-2149d9e5-102f-4402-a166-5910ff81cb4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652925829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1652925829
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3887127207
Short name T651
Test name
Test status
Simulation time 329887474 ps
CPU time 1.39 seconds
Started Jul 01 11:17:53 AM PDT 24
Finished Jul 01 11:18:20 AM PDT 24
Peak memory 201588 kb
Host smart-bc1b455d-4db0-41d4-ab1b-c77a0b8ff284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887127207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3887127207
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.452385226
Short name T152
Test name
Test status
Simulation time 426108341615 ps
CPU time 210.02 seconds
Started Jul 01 11:17:43 AM PDT 24
Finished Jul 01 11:21:48 AM PDT 24
Peak memory 201920 kb
Host smart-0a1867b1-e907-452e-9986-ddcc7d0528ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452385226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.452385226
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3587417770
Short name T764
Test name
Test status
Simulation time 489161924702 ps
CPU time 1078.82 seconds
Started Jul 01 11:17:50 AM PDT 24
Finished Jul 01 11:36:18 AM PDT 24
Peak memory 201856 kb
Host smart-69e170f8-9986-4d8c-bfbb-ac78dfa91505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587417770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3587417770
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1296067304
Short name T632
Test name
Test status
Simulation time 334702426773 ps
CPU time 784.94 seconds
Started Jul 01 11:17:43 AM PDT 24
Finished Jul 01 11:31:23 AM PDT 24
Peak memory 201880 kb
Host smart-11cd1ab3-f20b-4193-8526-07352a382d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296067304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1296067304
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2630912366
Short name T791
Test name
Test status
Simulation time 500599426247 ps
CPU time 275.83 seconds
Started Jul 01 11:17:50 AM PDT 24
Finished Jul 01 11:22:55 AM PDT 24
Peak memory 201800 kb
Host smart-7d0a0cf7-d452-44fd-ae1e-a93fc2514fba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630912366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2630912366
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.413238053
Short name T194
Test name
Test status
Simulation time 322387312035 ps
CPU time 693.23 seconds
Started Jul 01 11:17:44 AM PDT 24
Finished Jul 01 11:29:51 AM PDT 24
Peak memory 201820 kb
Host smart-53ad2f3a-744b-4fcf-9dae-bd5cebf5042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413238053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.413238053
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3474490043
Short name T419
Test name
Test status
Simulation time 168161415083 ps
CPU time 100.4 seconds
Started Jul 01 11:17:44 AM PDT 24
Finished Jul 01 11:19:59 AM PDT 24
Peak memory 201772 kb
Host smart-20ca357b-ebc0-4822-8d59-bfaa1ca2433c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474490043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3474490043
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3980079820
Short name T289
Test name
Test status
Simulation time 527016280837 ps
CPU time 1214.68 seconds
Started Jul 01 11:17:42 AM PDT 24
Finished Jul 01 11:38:33 AM PDT 24
Peak memory 201876 kb
Host smart-5a53e759-f89e-41d7-a754-ef82fac0483f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980079820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3980079820
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1392329774
Short name T446
Test name
Test status
Simulation time 197059263193 ps
CPU time 215.09 seconds
Started Jul 01 11:17:47 AM PDT 24
Finished Jul 01 11:21:54 AM PDT 24
Peak memory 201828 kb
Host smart-8b3c71e9-6259-4528-bdba-5953ad0f1b71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392329774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1392329774
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.78471051
Short name T460
Test name
Test status
Simulation time 106652456674 ps
CPU time 566.49 seconds
Started Jul 01 11:17:51 AM PDT 24
Finished Jul 01 11:27:45 AM PDT 24
Peak memory 202244 kb
Host smart-b649c780-112c-4730-8aff-712ec7b09e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78471051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.78471051
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1026457761
Short name T595
Test name
Test status
Simulation time 42893483453 ps
CPU time 25.64 seconds
Started Jul 01 11:17:49 AM PDT 24
Finished Jul 01 11:18:44 AM PDT 24
Peak memory 201636 kb
Host smart-5a46a3d7-0251-4821-9823-ef9a0d24d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026457761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1026457761
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.4266753604
Short name T415
Test name
Test status
Simulation time 5327479650 ps
CPU time 13.11 seconds
Started Jul 01 11:17:49 AM PDT 24
Finished Jul 01 11:18:32 AM PDT 24
Peak memory 201672 kb
Host smart-88ac1034-587f-4004-b3bd-1f8d30ddad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266753604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.4266753604
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3021408087
Short name T649
Test name
Test status
Simulation time 5640089228 ps
CPU time 9.41 seconds
Started Jul 01 11:17:44 AM PDT 24
Finished Jul 01 11:18:28 AM PDT 24
Peak memory 201612 kb
Host smart-248964f3-8d75-40e4-a6b5-1dd8915ebb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021408087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3021408087
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1609690022
Short name T239
Test name
Test status
Simulation time 359970260607 ps
CPU time 192.03 seconds
Started Jul 01 11:17:53 AM PDT 24
Finished Jul 01 11:21:31 AM PDT 24
Peak memory 201880 kb
Host smart-5f7bfe5e-860b-4328-99b6-857a8273be87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609690022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1609690022
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2486843006
Short name T700
Test name
Test status
Simulation time 40295862388 ps
CPU time 94.23 seconds
Started Jul 01 11:17:50 AM PDT 24
Finished Jul 01 11:19:53 AM PDT 24
Peak memory 210188 kb
Host smart-299c6989-9b4d-465b-8db7-526c5dfee262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486843006 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2486843006
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1903649892
Short name T406
Test name
Test status
Simulation time 415452127 ps
CPU time 0.86 seconds
Started Jul 01 11:18:04 AM PDT 24
Finished Jul 01 11:18:22 AM PDT 24
Peak memory 201600 kb
Host smart-8eb29a2e-854d-406f-9af5-f41433248100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903649892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1903649892
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.699255466
Short name T190
Test name
Test status
Simulation time 487931717055 ps
CPU time 91.74 seconds
Started Jul 01 11:17:55 AM PDT 24
Finished Jul 01 11:19:51 AM PDT 24
Peak memory 201876 kb
Host smart-7ccdcafb-3c7f-4def-bee5-7de38c16c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699255466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.699255466
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3051315633
Short name T444
Test name
Test status
Simulation time 495812722697 ps
CPU time 560.21 seconds
Started Jul 01 11:17:55 AM PDT 24
Finished Jul 01 11:27:40 AM PDT 24
Peak memory 201756 kb
Host smart-0dc58a17-e414-4742-b962-6facbb159817
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051315633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3051315633
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1230698898
Short name T185
Test name
Test status
Simulation time 166448017073 ps
CPU time 117.04 seconds
Started Jul 01 11:17:54 AM PDT 24
Finished Jul 01 11:20:16 AM PDT 24
Peak memory 201780 kb
Host smart-e4a1322e-4b1e-47a8-8c80-aff89d9c9217
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230698898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1230698898
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4196596917
Short name T330
Test name
Test status
Simulation time 389253831525 ps
CPU time 820.21 seconds
Started Jul 01 11:17:55 AM PDT 24
Finished Jul 01 11:32:00 AM PDT 24
Peak memory 201952 kb
Host smart-2c086608-7b7f-467e-a4fe-04471a3a7dbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196596917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4196596917
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1650434581
Short name T659
Test name
Test status
Simulation time 607940940154 ps
CPU time 732.69 seconds
Started Jul 01 11:17:54 AM PDT 24
Finished Jul 01 11:30:32 AM PDT 24
Peak memory 201980 kb
Host smart-1134b9f9-8e27-4c54-b59a-1e83741e4813
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650434581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1650434581
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3662928055
Short name T85
Test name
Test status
Simulation time 101993034523 ps
CPU time 479.09 seconds
Started Jul 01 11:17:58 AM PDT 24
Finished Jul 01 11:26:19 AM PDT 24
Peak memory 202240 kb
Host smart-4bf256d1-f5f3-429a-9b0c-02c2ecc6831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662928055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3662928055
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2431402103
Short name T776
Test name
Test status
Simulation time 29607428902 ps
CPU time 17.97 seconds
Started Jul 01 11:17:59 AM PDT 24
Finished Jul 01 11:18:38 AM PDT 24
Peak memory 201580 kb
Host smart-3d3af9f4-83d5-44e3-8c1a-5b7a2386b5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431402103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2431402103
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3072120825
Short name T1
Test name
Test status
Simulation time 5548452842 ps
CPU time 12.8 seconds
Started Jul 01 11:17:57 AM PDT 24
Finished Jul 01 11:18:33 AM PDT 24
Peak memory 201688 kb
Host smart-f25e52a2-f508-4856-b66c-721d59275e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072120825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3072120825
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2567500329
Short name T506
Test name
Test status
Simulation time 5816212799 ps
CPU time 4.05 seconds
Started Jul 01 11:17:55 AM PDT 24
Finished Jul 01 11:18:24 AM PDT 24
Peak memory 201632 kb
Host smart-b87e05cc-4817-4cfa-ac2c-b43c564059d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567500329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2567500329
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.879866142
Short name T362
Test name
Test status
Simulation time 331365240 ps
CPU time 0.81 seconds
Started Jul 01 11:18:14 AM PDT 24
Finished Jul 01 11:18:23 AM PDT 24
Peak memory 201608 kb
Host smart-553de198-1178-4b40-bc7d-62593e5f46d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879866142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.879866142
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1252450498
Short name T768
Test name
Test status
Simulation time 217756264042 ps
CPU time 482.76 seconds
Started Jul 01 11:18:09 AM PDT 24
Finished Jul 01 11:26:25 AM PDT 24
Peak memory 201864 kb
Host smart-27c7f1c8-803a-4c63-8951-78c8f9367744
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252450498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1252450498
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4001625039
Short name T722
Test name
Test status
Simulation time 327399280887 ps
CPU time 191.44 seconds
Started Jul 01 11:18:08 AM PDT 24
Finished Jul 01 11:21:33 AM PDT 24
Peak memory 201864 kb
Host smart-9613948b-4303-4d92-b337-eb6b8b9d144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001625039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4001625039
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1829920071
Short name T582
Test name
Test status
Simulation time 495993713808 ps
CPU time 1190.05 seconds
Started Jul 01 11:18:04 AM PDT 24
Finished Jul 01 11:38:12 AM PDT 24
Peak memory 201944 kb
Host smart-d63fe738-3e60-4299-84bd-c7c93587960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829920071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1829920071
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3242193969
Short name T792
Test name
Test status
Simulation time 490507401781 ps
CPU time 1239.68 seconds
Started Jul 01 11:18:03 AM PDT 24
Finished Jul 01 11:39:01 AM PDT 24
Peak memory 201748 kb
Host smart-36e15a2f-f718-4231-832e-29b3ee788ed0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242193969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3242193969
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1888290622
Short name T779
Test name
Test status
Simulation time 496056066501 ps
CPU time 1074.82 seconds
Started Jul 01 11:18:05 AM PDT 24
Finished Jul 01 11:36:16 AM PDT 24
Peak memory 201852 kb
Host smart-bd14250c-3ddf-40f1-9503-565f15d009ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888290622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1888290622
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1114260776
Short name T176
Test name
Test status
Simulation time 523522845949 ps
CPU time 171.48 seconds
Started Jul 01 11:18:03 AM PDT 24
Finished Jul 01 11:21:13 AM PDT 24
Peak memory 201892 kb
Host smart-014099df-52f2-43d4-ae93-9eccfffeea42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114260776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1114260776
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.4047908856
Short name T390
Test name
Test status
Simulation time 599234552008 ps
CPU time 1399.11 seconds
Started Jul 01 11:18:09 AM PDT 24
Finished Jul 01 11:41:41 AM PDT 24
Peak memory 201852 kb
Host smart-4781a28e-a64f-46f9-8230-d80e8d5a7df4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047908856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.4047908856
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.163940114
Short name T203
Test name
Test status
Simulation time 83839761470 ps
CPU time 230.01 seconds
Started Jul 01 11:18:13 AM PDT 24
Finished Jul 01 11:22:12 AM PDT 24
Peak memory 202204 kb
Host smart-28b8f2ca-59e3-4cf0-b5ab-8b96259f83cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163940114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.163940114
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2088152284
Short name T714
Test name
Test status
Simulation time 42763735295 ps
CPU time 45.63 seconds
Started Jul 01 11:18:08 AM PDT 24
Finished Jul 01 11:19:08 AM PDT 24
Peak memory 201680 kb
Host smart-f4035747-4fdc-4dc6-b70f-9942f28048ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088152284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2088152284
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2380903952
Short name T673
Test name
Test status
Simulation time 2897267174 ps
CPU time 7.42 seconds
Started Jul 01 11:18:09 AM PDT 24
Finished Jul 01 11:18:29 AM PDT 24
Peak memory 201684 kb
Host smart-21db91ce-063e-483a-9b23-685f61914079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380903952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2380903952
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2178181465
Short name T345
Test name
Test status
Simulation time 6134860476 ps
CPU time 7.66 seconds
Started Jul 01 11:18:04 AM PDT 24
Finished Jul 01 11:18:29 AM PDT 24
Peak memory 201640 kb
Host smart-41a9a3a1-fcfa-4a2f-b8b0-7254cd967d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178181465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2178181465
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2029515977
Short name T472
Test name
Test status
Simulation time 117815360637 ps
CPU time 604.84 seconds
Started Jul 01 11:18:15 AM PDT 24
Finished Jul 01 11:28:28 AM PDT 24
Peak memory 202248 kb
Host smart-dd8db0f7-4969-469e-95cf-c699e6538561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029515977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2029515977
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.4155967986
Short name T625
Test name
Test status
Simulation time 284159293198 ps
CPU time 159.28 seconds
Started Jul 01 11:18:14 AM PDT 24
Finished Jul 01 11:21:02 AM PDT 24
Peak memory 217888 kb
Host smart-f1edc289-8bd3-43b4-b202-b253e0aff091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155967986 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.4155967986
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1077728154
Short name T453
Test name
Test status
Simulation time 448451733 ps
CPU time 0.88 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:14:34 AM PDT 24
Peak memory 201752 kb
Host smart-907b3f08-c37b-4b46-91d1-933c6ee6104b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077728154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1077728154
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2825655406
Short name T716
Test name
Test status
Simulation time 185968424072 ps
CPU time 335.87 seconds
Started Jul 01 11:14:08 AM PDT 24
Finished Jul 01 11:19:44 AM PDT 24
Peak memory 201844 kb
Host smart-066b1239-7dd7-4c8c-92ee-f0c556ee4b10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825655406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2825655406
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1371312196
Short name T296
Test name
Test status
Simulation time 490894464863 ps
CPU time 1206.19 seconds
Started Jul 01 11:14:12 AM PDT 24
Finished Jul 01 11:34:18 AM PDT 24
Peak memory 201888 kb
Host smart-a708e5fe-af71-4dd2-8c15-d69e0b63e32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371312196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1371312196
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3672962993
Short name T424
Test name
Test status
Simulation time 328756457270 ps
CPU time 716.11 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:26:19 AM PDT 24
Peak memory 201856 kb
Host smart-b112a640-ebdb-4098-a046-22e3d6ca2e31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672962993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3672962993
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3479773734
Short name T735
Test name
Test status
Simulation time 501773471648 ps
CPU time 182.39 seconds
Started Jul 01 11:14:32 AM PDT 24
Finished Jul 01 11:17:35 AM PDT 24
Peak memory 201852 kb
Host smart-44c17aca-64d5-4d2f-8180-876f7984dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479773734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3479773734
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1829286108
Short name T531
Test name
Test status
Simulation time 159303835081 ps
CPU time 333.27 seconds
Started Jul 01 11:14:05 AM PDT 24
Finished Jul 01 11:19:39 AM PDT 24
Peak memory 201828 kb
Host smart-a1214d64-eb1f-4225-9317-0cffd5f777a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829286108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1829286108
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2101273956
Short name T258
Test name
Test status
Simulation time 184519683005 ps
CPU time 167.69 seconds
Started Jul 01 11:14:23 AM PDT 24
Finished Jul 01 11:17:11 AM PDT 24
Peak memory 201872 kb
Host smart-4e5c712b-d5c8-42f3-a3fb-b4a47e69c1a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101273956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2101273956
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1140874349
Short name T771
Test name
Test status
Simulation time 614863100924 ps
CPU time 209.01 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:17:51 AM PDT 24
Peak memory 201868 kb
Host smart-0cc965f7-f06c-4fd7-a353-9614c81924db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140874349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1140874349
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1050546112
Short name T338
Test name
Test status
Simulation time 96642258659 ps
CPU time 414.17 seconds
Started Jul 01 11:14:11 AM PDT 24
Finished Jul 01 11:21:06 AM PDT 24
Peak memory 202192 kb
Host smart-c73a5fbc-24f7-47f6-83e3-c976c278f666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050546112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1050546112
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3202780086
Short name T158
Test name
Test status
Simulation time 31200750729 ps
CPU time 70.07 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:15:25 AM PDT 24
Peak memory 201632 kb
Host smart-fd1dfb3d-9fd7-4f1b-b241-71848cd77db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202780086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3202780086
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3979665730
Short name T420
Test name
Test status
Simulation time 3872414810 ps
CPU time 3.14 seconds
Started Jul 01 11:14:23 AM PDT 24
Finished Jul 01 11:14:27 AM PDT 24
Peak memory 201624 kb
Host smart-00cc5a59-0e66-43e6-afdc-239e94d0c7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979665730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3979665730
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2997473118
Short name T501
Test name
Test status
Simulation time 5696354479 ps
CPU time 9.82 seconds
Started Jul 01 11:14:24 AM PDT 24
Finished Jul 01 11:14:34 AM PDT 24
Peak memory 201676 kb
Host smart-2b7bf6a0-6bdf-4252-87ff-96385aa5e794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997473118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2997473118
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2323443334
Short name T545
Test name
Test status
Simulation time 175893453718 ps
CPU time 112.65 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:16:33 AM PDT 24
Peak memory 201908 kb
Host smart-7e679435-3999-48a5-abee-be53597ee0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323443334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2323443334
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.377250380
Short name T790
Test name
Test status
Simulation time 381656544500 ps
CPU time 90.97 seconds
Started Jul 01 11:14:12 AM PDT 24
Finished Jul 01 11:15:43 AM PDT 24
Peak memory 210520 kb
Host smart-e581edec-bd09-4ce4-9792-d70c05c737d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377250380 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.377250380
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1912524667
Short name T742
Test name
Test status
Simulation time 285359603 ps
CPU time 1.3 seconds
Started Jul 01 11:14:10 AM PDT 24
Finished Jul 01 11:14:12 AM PDT 24
Peak memory 201604 kb
Host smart-e05faf04-687e-44cd-93e4-1edb913f94c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912524667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1912524667
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3013614141
Short name T28
Test name
Test status
Simulation time 199222101722 ps
CPU time 217.21 seconds
Started Jul 01 11:14:12 AM PDT 24
Finished Jul 01 11:17:50 AM PDT 24
Peak memory 201880 kb
Host smart-9723aaba-2220-42ce-99f8-92961235e804
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013614141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3013614141
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3411880213
Short name T90
Test name
Test status
Simulation time 166969187414 ps
CPU time 199.78 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:17:53 AM PDT 24
Peak memory 201812 kb
Host smart-e4ac04bc-b1d8-40cf-8c62-f61149f7fb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411880213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3411880213
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.279345817
Short name T248
Test name
Test status
Simulation time 161894066876 ps
CPU time 368.93 seconds
Started Jul 01 11:14:12 AM PDT 24
Finished Jul 01 11:20:21 AM PDT 24
Peak memory 201864 kb
Host smart-dc2da671-c49c-402e-ac0c-bba5a9ef7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279345817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.279345817
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3954060153
Short name T349
Test name
Test status
Simulation time 329453687230 ps
CPU time 312.04 seconds
Started Jul 01 11:14:29 AM PDT 24
Finished Jul 01 11:19:42 AM PDT 24
Peak memory 201792 kb
Host smart-8258e23b-1989-4c92-ac6b-7f247a54113e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954060153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3954060153
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.525504504
Short name T520
Test name
Test status
Simulation time 494178583434 ps
CPU time 1069.38 seconds
Started Jul 01 11:14:32 AM PDT 24
Finished Jul 01 11:32:22 AM PDT 24
Peak memory 201888 kb
Host smart-e93ccf44-16e8-4770-a9b5-485ca4009386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525504504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.525504504
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.555215164
Short name T570
Test name
Test status
Simulation time 486870998590 ps
CPU time 297.81 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:19:29 AM PDT 24
Peak memory 201828 kb
Host smart-346af689-9c49-4a6a-80be-9b93f693e117
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=555215164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.555215164
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3754296328
Short name T256
Test name
Test status
Simulation time 179403521863 ps
CPU time 97.18 seconds
Started Jul 01 11:14:31 AM PDT 24
Finished Jul 01 11:16:09 AM PDT 24
Peak memory 201936 kb
Host smart-d97cc1d1-7d87-488e-8885-ff3ca4709a6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754296328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3754296328
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3620708572
Short name T616
Test name
Test status
Simulation time 407212543663 ps
CPU time 405.27 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:21:08 AM PDT 24
Peak memory 201852 kb
Host smart-d0e1ce27-4684-4f05-b220-eb758c172316
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620708572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3620708572
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2182396692
Short name T497
Test name
Test status
Simulation time 87096758455 ps
CPU time 340.31 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:20:14 AM PDT 24
Peak memory 202184 kb
Host smart-d57584ad-6486-4828-9260-6e9864cd3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182396692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2182396692
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1037827659
Short name T657
Test name
Test status
Simulation time 27967452519 ps
CPU time 62.25 seconds
Started Jul 01 11:14:11 AM PDT 24
Finished Jul 01 11:15:14 AM PDT 24
Peak memory 201580 kb
Host smart-087a3ce4-da0d-4aa3-9704-255710ac2c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037827659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1037827659
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1059015621
Short name T409
Test name
Test status
Simulation time 5235281994 ps
CPU time 7.12 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:14:41 AM PDT 24
Peak memory 201680 kb
Host smart-64e98d8d-a58d-4817-95b5-167060abae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059015621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1059015621
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2275545820
Short name T448
Test name
Test status
Simulation time 5817794027 ps
CPU time 14.12 seconds
Started Jul 01 11:14:11 AM PDT 24
Finished Jul 01 11:14:26 AM PDT 24
Peak memory 201656 kb
Host smart-83606fd9-cce4-417d-aaf8-cce279e3e21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275545820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2275545820
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2986119876
Short name T154
Test name
Test status
Simulation time 200237400411 ps
CPU time 447.74 seconds
Started Jul 01 11:14:46 AM PDT 24
Finished Jul 01 11:22:16 AM PDT 24
Peak memory 201868 kb
Host smart-e980c3e7-aaf3-4dbc-88f5-9cbe1349ce4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986119876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2986119876
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2976889958
Short name T187
Test name
Test status
Simulation time 317197543 ps
CPU time 0.8 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:14:16 AM PDT 24
Peak memory 201616 kb
Host smart-b62e7d65-7f8c-4072-bd56-90cdff8cb602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976889958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2976889958
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1556286051
Short name T247
Test name
Test status
Simulation time 343286325230 ps
CPU time 793.33 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:27:28 AM PDT 24
Peak memory 201864 kb
Host smart-64c8a462-eb24-4d0e-9a4c-c5bfe45b4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556286051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1556286051
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1515547543
Short name T385
Test name
Test status
Simulation time 328782161092 ps
CPU time 118.81 seconds
Started Jul 01 11:14:25 AM PDT 24
Finished Jul 01 11:16:25 AM PDT 24
Peak memory 201800 kb
Host smart-60056a96-adae-4ada-aa0b-990cea93cf0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515547543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1515547543
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1628528840
Short name T525
Test name
Test status
Simulation time 492028684898 ps
CPU time 1013.71 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:31:16 AM PDT 24
Peak memory 201816 kb
Host smart-d22b6ede-5b10-48bf-9569-0134e87a7abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628528840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1628528840
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1241207608
Short name T367
Test name
Test status
Simulation time 492752840987 ps
CPU time 535.26 seconds
Started Jul 01 11:14:34 AM PDT 24
Finished Jul 01 11:23:30 AM PDT 24
Peak memory 201852 kb
Host smart-b87c9b3a-e1c3-4430-a7d0-ee25fc352ec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241207608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1241207608
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3699236206
Short name T8
Test name
Test status
Simulation time 390420803751 ps
CPU time 162.22 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:17:05 AM PDT 24
Peak memory 201796 kb
Host smart-e1d6617d-d798-4d84-a514-ad6354de8036
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699236206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3699236206
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.89541028
Short name T339
Test name
Test status
Simulation time 78660306644 ps
CPU time 299.49 seconds
Started Jul 01 11:14:16 AM PDT 24
Finished Jul 01 11:19:16 AM PDT 24
Peak memory 202252 kb
Host smart-be5afcdc-1309-4ce9-b0e1-7eceb3a8e553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89541028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.89541028
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.706481594
Short name T93
Test name
Test status
Simulation time 28548965305 ps
CPU time 28.94 seconds
Started Jul 01 11:14:19 AM PDT 24
Finished Jul 01 11:14:48 AM PDT 24
Peak memory 201660 kb
Host smart-a14e2872-1ebe-469e-9b75-39bb1dc60661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706481594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.706481594
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1327525285
Short name T558
Test name
Test status
Simulation time 4839937240 ps
CPU time 11.55 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:14:53 AM PDT 24
Peak memory 201704 kb
Host smart-a79ae193-237f-4f69-b4b4-9d663c79bf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327525285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1327525285
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3388505078
Short name T564
Test name
Test status
Simulation time 5777227666 ps
CPU time 13.35 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:14:48 AM PDT 24
Peak memory 201600 kb
Host smart-fd5246da-d937-465c-9f3c-f638953f2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388505078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3388505078
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1322011415
Short name T321
Test name
Test status
Simulation time 205467813753 ps
CPU time 240.47 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:18:15 AM PDT 24
Peak memory 201776 kb
Host smart-054d4dee-649e-4ef9-9362-5b2927fa0f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322011415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1322011415
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2052643437
Short name T80
Test name
Test status
Simulation time 109354465701 ps
CPU time 149.24 seconds
Started Jul 01 11:14:16 AM PDT 24
Finished Jul 01 11:16:46 AM PDT 24
Peak memory 210508 kb
Host smart-067badc5-bffa-48c8-9812-9d6a195fbbf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052643437 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2052643437
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3618718867
Short name T620
Test name
Test status
Simulation time 385218392 ps
CPU time 1.45 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:14:44 AM PDT 24
Peak memory 201612 kb
Host smart-8431ed80-a77d-45cf-b38a-9a8e79213fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618718867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3618718867
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1710430990
Short name T287
Test name
Test status
Simulation time 161328259389 ps
CPU time 101.86 seconds
Started Jul 01 11:14:45 AM PDT 24
Finished Jul 01 11:16:29 AM PDT 24
Peak memory 201884 kb
Host smart-ec966cd4-f9ef-46fb-bfa2-8524af23bbe3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710430990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1710430990
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.111932140
Short name T528
Test name
Test status
Simulation time 190288530459 ps
CPU time 215.09 seconds
Started Jul 01 11:14:17 AM PDT 24
Finished Jul 01 11:17:53 AM PDT 24
Peak memory 201888 kb
Host smart-390bffc0-9b42-4444-8705-48a8a6109bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111932140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.111932140
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2087039027
Short name T170
Test name
Test status
Simulation time 332582645029 ps
CPU time 137.89 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:16:57 AM PDT 24
Peak memory 201888 kb
Host smart-c029c75e-feda-404c-92b1-0aac2030c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087039027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2087039027
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2594201671
Short name T745
Test name
Test status
Simulation time 495012044726 ps
CPU time 1117.76 seconds
Started Jul 01 11:14:15 AM PDT 24
Finished Jul 01 11:32:53 AM PDT 24
Peak memory 201680 kb
Host smart-ffd8df76-bffc-46f3-be54-28014f564e4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594201671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2594201671
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2946608151
Short name T2
Test name
Test status
Simulation time 171392076770 ps
CPU time 372.14 seconds
Started Jul 01 11:14:33 AM PDT 24
Finished Jul 01 11:20:46 AM PDT 24
Peak memory 201856 kb
Host smart-bd9d7f44-83e4-4fea-8896-b1966a8b4d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946608151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2946608151
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1556394266
Short name T789
Test name
Test status
Simulation time 160831876598 ps
CPU time 46.61 seconds
Started Jul 01 11:14:16 AM PDT 24
Finished Jul 01 11:15:03 AM PDT 24
Peak memory 201848 kb
Host smart-53741eac-48ac-4b42-8490-384e337321b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556394266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1556394266
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1751214853
Short name T280
Test name
Test status
Simulation time 172197483770 ps
CPU time 406.74 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:21:30 AM PDT 24
Peak memory 201868 kb
Host smart-299432fa-843a-43ed-bc32-285c845d3f6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751214853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1751214853
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3559527962
Short name T577
Test name
Test status
Simulation time 392695655322 ps
CPU time 408.98 seconds
Started Jul 01 11:14:15 AM PDT 24
Finished Jul 01 11:21:05 AM PDT 24
Peak memory 201872 kb
Host smart-e53e5bb2-4d6c-49a8-b161-26bb1475c1c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559527962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3559527962
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2310731037
Short name T397
Test name
Test status
Simulation time 114681754734 ps
CPU time 453.17 seconds
Started Jul 01 11:14:30 AM PDT 24
Finished Jul 01 11:22:04 AM PDT 24
Peak memory 202120 kb
Host smart-5874772d-804f-477d-b592-a9a1f5126f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310731037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2310731037
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2599157330
Short name T713
Test name
Test status
Simulation time 35376792786 ps
CPU time 80.85 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:15:35 AM PDT 24
Peak memory 201640 kb
Host smart-c6f60949-28b6-469a-b18d-dbf4eb323ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599157330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2599157330
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2731125872
Short name T494
Test name
Test status
Simulation time 3140825692 ps
CPU time 4.28 seconds
Started Jul 01 11:14:19 AM PDT 24
Finished Jul 01 11:14:23 AM PDT 24
Peak memory 201672 kb
Host smart-f6e3e17b-1d10-4179-984b-463192559262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731125872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2731125872
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3510043222
Short name T106
Test name
Test status
Simulation time 6080683086 ps
CPU time 7.69 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:14:52 AM PDT 24
Peak memory 201712 kb
Host smart-e390240c-2cac-4ec4-994b-11507263d239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510043222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3510043222
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1815711460
Short name T761
Test name
Test status
Simulation time 503767210623 ps
CPU time 542.39 seconds
Started Jul 01 11:14:16 AM PDT 24
Finished Jul 01 11:23:19 AM PDT 24
Peak memory 201936 kb
Host smart-0a52626a-1597-47dd-8bf6-91cc14fb3fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815711460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1815711460
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1269022524
Short name T668
Test name
Test status
Simulation time 21007154336 ps
CPU time 72.8 seconds
Started Jul 01 11:14:15 AM PDT 24
Finished Jul 01 11:15:28 AM PDT 24
Peak memory 210404 kb
Host smart-2fa203b9-404c-4c84-99ce-62b7d382d2ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269022524 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1269022524
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1025112298
Short name T350
Test name
Test status
Simulation time 539778060 ps
CPU time 1.26 seconds
Started Jul 01 11:14:41 AM PDT 24
Finished Jul 01 11:14:43 AM PDT 24
Peak memory 201620 kb
Host smart-732fc7d5-5fe2-4fff-87fc-7ba000f86cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025112298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1025112298
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.39354813
Short name T259
Test name
Test status
Simulation time 513613448872 ps
CPU time 602.71 seconds
Started Jul 01 11:14:19 AM PDT 24
Finished Jul 01 11:24:22 AM PDT 24
Peak memory 201872 kb
Host smart-42f8ab74-035f-4d2f-91de-f839d5488b22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39354813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating
.39354813
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3340232601
Short name T230
Test name
Test status
Simulation time 164435602376 ps
CPU time 361.8 seconds
Started Jul 01 11:14:17 AM PDT 24
Finished Jul 01 11:20:19 AM PDT 24
Peak memory 201836 kb
Host smart-550a9771-ace3-4233-9689-0ed0499c9a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340232601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3340232601
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4060414348
Short name T550
Test name
Test status
Simulation time 327430306285 ps
CPU time 191.97 seconds
Started Jul 01 11:14:35 AM PDT 24
Finished Jul 01 11:17:48 AM PDT 24
Peak memory 202008 kb
Host smart-c3f5b636-3544-4864-9a78-9b7def6c3114
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060414348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4060414348
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.288507658
Short name T9
Test name
Test status
Simulation time 492769802378 ps
CPU time 98.77 seconds
Started Jul 01 11:14:42 AM PDT 24
Finished Jul 01 11:16:23 AM PDT 24
Peak memory 201896 kb
Host smart-01f3f479-90ff-4a20-9e08-11ef60f93897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288507658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.288507658
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2702346538
Short name T92
Test name
Test status
Simulation time 329123543387 ps
CPU time 334.55 seconds
Started Jul 01 11:14:39 AM PDT 24
Finished Jul 01 11:20:14 AM PDT 24
Peak memory 201776 kb
Host smart-2243ad1a-3b87-4af6-aae6-37b7a79cf185
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702346538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2702346538
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.426572048
Short name T619
Test name
Test status
Simulation time 567263696822 ps
CPU time 311.06 seconds
Started Jul 01 11:14:14 AM PDT 24
Finished Jul 01 11:19:26 AM PDT 24
Peak memory 201944 kb
Host smart-004a9db4-12c0-40f9-9c4e-c90b3343981a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426572048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.426572048
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2946272879
Short name T445
Test name
Test status
Simulation time 406540393540 ps
CPU time 229.72 seconds
Started Jul 01 11:14:22 AM PDT 24
Finished Jul 01 11:18:13 AM PDT 24
Peak memory 201832 kb
Host smart-9214c76b-166a-48ea-9fac-342bc43e91b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946272879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2946272879
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2438568400
Short name T694
Test name
Test status
Simulation time 68559124402 ps
CPU time 329.25 seconds
Started Jul 01 11:14:20 AM PDT 24
Finished Jul 01 11:19:50 AM PDT 24
Peak memory 202196 kb
Host smart-cd4a99b2-d5d8-4922-9181-adcf6cdb2689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438568400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2438568400
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.562091811
Short name T351
Test name
Test status
Simulation time 23781519107 ps
CPU time 9.79 seconds
Started Jul 01 11:14:40 AM PDT 24
Finished Jul 01 11:14:52 AM PDT 24
Peak memory 201616 kb
Host smart-168404e0-39eb-4549-a440-36ead7ffdb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562091811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.562091811
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1809788179
Short name T474
Test name
Test status
Simulation time 4440894685 ps
CPU time 9.69 seconds
Started Jul 01 11:14:47 AM PDT 24
Finished Jul 01 11:14:58 AM PDT 24
Peak memory 201680 kb
Host smart-0a198603-9c9e-4aa2-9d17-156a37e70899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809788179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1809788179
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.556558534
Short name T581
Test name
Test status
Simulation time 5671254200 ps
CPU time 14.46 seconds
Started Jul 01 11:14:15 AM PDT 24
Finished Jul 01 11:14:30 AM PDT 24
Peak memory 201688 kb
Host smart-1633a741-c187-4567-b3ea-49ec1e7586b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556558534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.556558534
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2836541110
Short name T304
Test name
Test status
Simulation time 175328682030 ps
CPU time 145.14 seconds
Started Jul 01 11:14:38 AM PDT 24
Finished Jul 01 11:17:04 AM PDT 24
Peak memory 201916 kb
Host smart-2a70625f-e2d9-4b9e-bccb-6964f119d41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836541110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2836541110
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1666555887
Short name T18
Test name
Test status
Simulation time 103277877895 ps
CPU time 171.41 seconds
Started Jul 01 11:14:38 AM PDT 24
Finished Jul 01 11:17:30 AM PDT 24
Peak memory 218644 kb
Host smart-9d65483c-776c-441c-81ca-29d174b0a4b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666555887 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1666555887
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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