Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7025	1			T2	11		T6	66		T7	20
testmodes[AdcCtrlTestmodeNormal]	5757	1			T2	9		T3	1		T6	70
testmodes[AdcCtrlTestmodeLowpower]	5842	1			T1	1		T5	1		T6	54
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3803	1			T2	7		T6	26		T7	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1765	1			T2	4		T6	24		T10	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1342	1			T6	16		T10	1		T40	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1755	1			T2	4		T6	28		T10	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2131	1			T2	4		T6	24		T8	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1524	1			T6	18		T40	17		T42	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1350	1			T6	11		T40	28		T42	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1513	1			T6	22		T10	1		T11	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2743	1			T6	20		T10	14		T12	2