Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23281

1

T1

22

T2

20

T5

7

auto[ADC_CTRL_FILTER_COND_OUT]

3430

1

T3

1

T8

2

T10

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20299

1

T2

20

T3

1

T6

180

auto[1]

6412

1

T1

22

T5

7

T6

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	384	1			T6	10		T40	5		T42	5
values[0]	42	1			T144	19		T32	1		T57	5
values[1]	732	1			T11	25		T44	2		T139	2
values[2]	2788	1			T5	7		T9	12		T11	13
values[3]	629	1			T8	1		T65	28		T66	21
values[4]	731	1			T65	8		T131	27		T215	18
values[5]	866	1			T10	23		T12	11		T13	22
values[6]	427	1			T8	1		T132	6		T146	15
values[7]	669	1			T1	22		T12	12		T55	1
values[8]	657	1			T39	4		T42	1		T150	1
values[9]	1488	1			T3	1		T8	1		T12	6
minimum	17298	1			T2	20		T6	180		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	884	1			T11	25		T44	2		T150	1
values[1]	2843	1			T5	7		T9	12		T11	13
values[2]	587	1			T8	1		T133	22		T66	15
values[3]	793	1			T55	1		T65	8		T131	27
values[4]	791	1			T10	23		T12	11		T13	22
values[5]	524	1			T1	22		T47	5		T140	16
values[6]	556	1			T8	1		T12	12		T42	1
values[7]	754	1			T39	4		T173	7		T132	12
values[8]	1066	1			T3	1		T8	1		T12	6
values[9]	242	1			T13	21		T34	22		T53	13
minimum	17671	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T139	2		T35	1		T216	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	17		T44	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T5	7		T9	12		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	11		T65	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T217	5		T49	3		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T133	11		T66	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T65	3		T131	16		T219	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	1		T215	18		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	13		T48	12		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	13		T12	11		T220	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	12		T47	3		T140	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T137	15		T221	8		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T135	5		T49	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T12	12		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T39	4		T173	1		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T132	1		T133	16		T215	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T8	1		T12	6		T13	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	1		T43	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	13		T34	12		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T53	3		T219	12		T223	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17561	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	10		T141	7		T136	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	8		T44	1		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1046	1			T48	11		T225	9		T226	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	2		T65	15		T66	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T217	13		T218	4		T227	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T133	11		T66	6		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T65	5		T131	11		T56	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T229	11		T27	9		T206	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	9		T48	12		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	10		T220	9		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	10		T47	2		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T137	14		T230	9		T130	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T49	1		T51	1		T56	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	5		T153	9		T231	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T173	6		T140	7		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T132	11		T133	15		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	10		T46	2		T133	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T217	15		T167	12		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T13	8		T34	10		T168	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T53	10		T223	5		T232	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	1		T46	1		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T6	10		T40	5		T42	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T233	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T144	14		T32	1		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T234	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T139	1		T35	1		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	17		T44	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T5	7		T9	12		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	11		T150	2		T133	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	3		T235	21		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	1		T65	13		T66	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T65	3		T131	16		T217	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T215	18		T142	1		T229	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T13	13		T48	12		T137	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	13		T12	11		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T236	1		T147	3		T237	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T8	1		T132	1		T146	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	12		T47	3		T140	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	12		T55	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	4		T173	1		T134	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T42	1		T150	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	450	1			T8	1		T12	6		T13	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T3	1		T43	1		T53	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17190	1			T2	20		T6	180		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T238	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T233	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T144	5		T57	4		T20	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	10		T141	7		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	8		T44	1		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T48	11		T225	9		T226	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	2		T133	11		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T90	10		T147	9		T239	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T65	15		T66	9		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T65	5		T131	11		T217	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T229	11		T220	9		T240	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	9		T48	12		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	10		T227	7		T241	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T147	2		T237	4		T242	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T132	5		T146	12		T243	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T1	10		T47	2		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T137	14		T153	9		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T173	6		T140	7		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T132	11		T133	15		T231	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T13	18		T34	10		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T53	10		T143	5		T217	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T139	2		T35	11		T216	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	9		T44	2		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T5	1		T9	1		T48	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	3		T65	16		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T217	14		T49	1		T218	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T133	12		T66	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T65	6		T131	12		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	1		T215	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	10		T48	13		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	11		T12	1		T220	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	11		T47	5		T140	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T137	15		T221	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T135	1		T49	2		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T12	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	4		T173	7		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T132	12		T133	16		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T8	1		T12	1		T13	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T43	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T13	9		T34	11		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T53	11		T219	1		T223	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17671	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	13		T229	11		T144	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	16		T224	6		T154	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T5	6		T9	11		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	10		T65	12		T66	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T217	4		T49	2		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T133	10		T66	8		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T65	2		T131	15		T219	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T215	16		T229	11		T221	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	12		T48	11		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	12		T12	10		T220	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	11		T140	7		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T137	14		T221	7		T230	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T135	4		T235	13		T56	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	11		T153	11		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T134	5		T140	7		T135	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T133	15		T215	18		T246	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	5		T13	10		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T135	12		T217	4		T247	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T13	12		T34	11		T134	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T53	2		T219	11		T223	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T6	10		T40	5		T42	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T233	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T144	6		T32	1		T57	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T234	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T139	1		T35	11		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	9		T44	2		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T5	1		T9	1		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	3		T150	2		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	1		T235	1		T90	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T65	16		T66	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T65	6		T131	12		T217	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T215	2		T142	1		T229	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T13	10		T48	13		T137	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	11		T12	1		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T236	1		T147	3		T237	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T132	6		T146	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	11		T47	5		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T55	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T39	4		T173	7		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	1		T150	1		T132	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T8	1		T12	1		T13	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T3	1		T43	1		T53	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17298	1			T2	20		T6	180		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T233	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T144	13		T20	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T134	13		T136	13		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	16		T224	6		T154	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T5	6		T9	11		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	10		T133	10		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	2		T235	20		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T65	12		T66	10		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T65	2		T131	15		T217	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T215	16		T229	11		T220	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	12		T48	11		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	12		T12	10		T227	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T147	2		T237	2		T248	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T146	2		T221	7		T243	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T1	11		T140	7		T56	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	11		T137	14		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T134	5		T140	7		T135	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T133	15		T215	18		T245	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T12	5		T13	22		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T53	2		T135	12		T217	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23355

1

T2

20

T5

7

T6

190

auto[ADC_CTRL_FILTER_COND_OUT]

3356

1

T1

22

T3

1

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21056

1

T1

22

T2

20

T3

1

auto[1]

5655

1

T5

7

T8

3

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T244	1		T181	1		-	-
values[0]	71	1			T229	24		T144	18		T182	12
values[1]	672	1			T8	2		T11	25		T150	1
values[2]	648	1			T48	24		T35	11		T134	22
values[3]	596	1			T3	1		T10	23		T13	21
values[4]	781	1			T12	18		T13	21		T34	22
values[5]	2858	1			T5	7		T8	1		T9	12
values[6]	799	1			T1	22		T65	28		T35	1
values[7]	662	1			T11	13		T48	14		T44	2
values[8]	613	1			T12	11		T43	1		T150	1
values[9]	1343	1			T13	22		T53	13		T46	7
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	876	1			T8	2		T11	25		T48	24
values[1]	603	1			T150	1		T131	27		T35	11
values[2]	638	1			T3	1		T12	6		T13	21
values[3]	2922	1			T5	7		T9	12		T10	23
values[4]	618	1			T8	1		T55	1		T65	8
values[5]	864	1			T1	22		T48	14		T55	1
values[6]	541	1			T11	13		T44	2		T47	5
values[7]	798	1			T13	22		T43	1		T150	1
values[8]	841	1			T12	11		T46	7		T133	31
values[9]	263	1			T53	13		T163	1		T235	21
minimum	17747	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	1		T48	12		T133	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	1		T11	17		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	16		T35	1		T135	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T150	1		T133	11		T136	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	13		T39	4		T215	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	1		T12	6		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T5	7		T9	12		T10	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	12		T13	11		T34	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T55	1		T35	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T65	3		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T48	3		T55	1		T65	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	12		T134	6		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	3		T141	1		T135	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	11		T44	1		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T139	1		T143	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	13		T43	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	11		T137	11		T167	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	5		T133	16		T66	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T53	3		T163	1		T235	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T88	4		T200	23		T249	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17559	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T165	13		T182	1		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	12		T133	4		T246	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	8		T229	11		T218	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	11		T35	10		T50	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T133	11		T136	12		T57	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	8		T251	15		T30	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T132	11		T140	7		T252	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T10	10		T225	9		T226	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	10		T34	10		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T140	11		T154	12		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T65	5		T224	4		T132	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T48	11		T65	15		T66	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	10		T137	14		T217	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T47	2		T141	7		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	2		T44	1		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T143	5		T153	9		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	9		T173	6		T217	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T137	10		T167	23		T240	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	2		T133	15		T66	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T53	10		T253	1		T250	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T88	3		T200	19		T241	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T182	10		T250	8		T254	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T244	1		T181	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T144	1		T182	1		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T229	13		T256	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T133	5		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T11	17		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T48	12		T35	1		T135	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	22		T141	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	13		T13	13		T131	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T3	1		T55	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T39	4		T42	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	18		T13	11		T34	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T5	7		T9	12		T55	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T65	3		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T65	13		T35	1		T66	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	12		T132	1		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	3		T141	1		T135	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	11		T44	1		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	11		T139	1		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	1		T150	1		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T53	3		T137	11		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	449	1			T13	13		T46	5		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T144	17		T182	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T229	11		T256	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T133	4		T246	6		T227	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	8		T218	4		T231	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	12		T35	10		T50	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T257	4		T237	9		T258	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	10		T13	8		T131	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T132	11		T133	11		T136	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T251	4		T149	10		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	10		T34	10		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T225	9		T140	11		T226	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T65	5		T224	4		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T65	15		T66	6		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	10		T132	5		T137	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	11		T141	7		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	2		T44	1		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	2		T143	5		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T251	8		T258	8		T259	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T53	10		T137	10		T167	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T13	9		T46	2		T173	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1