Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20880

1

T2

20

T3

1

T6

190

auto[ADC_CTRL_FILTER_COND_OUT]

5831

1

T1

22

T5

7

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20801

1

T2

20

T3

1

T6

190

auto[1]

5910

1

T1

22

T5

7

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	165	1			T55	1		T133	22		T228	3
values[0]	61	1			T132	12		T309	23		T98	8
values[1]	619	1			T10	23		T13	22		T150	1
values[2]	544	1			T8	1		T34	22		T42	1
values[3]	661	1			T12	12		T55	1		T215	18
values[4]	708	1			T1	22		T3	1		T11	25
values[5]	720	1			T150	1		T46	7		T139	1
values[6]	824	1			T48	24		T39	4		T53	13
values[7]	846	1			T48	14		T139	1		T173	7
values[8]	465	1			T8	1		T35	11		T66	15
values[9]	3432	1			T5	7		T8	1		T9	12
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	428	1			T10	23		T139	1		T47	5
values[1]	2847	1			T5	7		T8	1		T9	12
values[2]	649	1			T12	23		T55	1		T215	18
values[3]	887	1			T1	22		T3	1		T11	25
values[4]	708	1			T53	13		T150	1		T139	1
values[5]	685	1			T48	38		T39	4		T55	1
values[6]	820	1			T139	1		T35	11		T173	7
values[7]	573	1			T8	2		T13	21		T131	27
values[8]	978	1			T11	13		T13	21		T44	2
values[9]	161	1			T163	1		T251	16		T30	1
minimum	17975	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T47	3		T133	16		T134	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	13		T139	1		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	1		T150	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1508	1			T5	7		T9	12		T34	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	11		T215	10		T144	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	12		T55	1		T215	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	1		T11	17		T12	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	12		T43	1		T66	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T216	1		T141	1		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	3		T150	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	15		T39	4		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	3		T140	8		T219	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T35	1		T215	19		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T139	1		T173	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	1		T13	11		T224	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	1		T131	16		T66	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	11		T44	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T13	13		T65	13		T133	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T163	1		T30	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T251	1		T89	1		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	13		T231	1		T234	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T47	2		T133	15		T291	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T10	10		T138	1		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T136	10		T51	1		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1112	1			T34	10		T225	9		T226	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T144	5		T244	4		T195	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	10		T57	12		T237	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	8		T46	2		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	10		T66	3		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T167	12		T229	11		T168	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T53	10		T143	5		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	23		T49	1		T218	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T65	5		T140	8		T270	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T35	10		T136	12		T246	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T173	6		T132	5		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	10		T224	4		T217	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T131	11		T66	6		T144	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	2		T44	1		T133	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	8		T65	15		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T158	1		T262	5		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T251	15		T258	8		T317	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T13	9		T231	4		T234	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T55	1		T228	1		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T133	11		T251	1		T24	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T132	1		T309	13		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T150	1		T47	3		T133	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	13		T13	13		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	1		T150	1		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T34	12		T42	1		T217	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T215	10		T52	3		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	12		T55	1		T215	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T11	17		T12	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	12		T43	1		T66	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	5		T216	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T150	1		T139	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T48	12		T39	4		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T53	3		T65	3		T140	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T48	3		T215	19		T136	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T139	1		T173	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	1		T217	5		T235	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T8	1		T66	9		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	1		T11	11		T13	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1733	1			T5	7		T9	12		T13	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T228	2		T285	17		T241	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T133	11		T251	15		T318	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T132	11		T309	10		T98	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T47	2		T133	15		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	10		T13	9		T138	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T136	10		T51	1		T30	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	10		T217	13		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T244	4		T27	9		T266	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T137	10		T144	10		T57	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	8		T140	7		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	10		T66	3		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T46	2		T167	12		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T143	5		T229	11		T56	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	12		T218	4		T251	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T53	10		T65	5		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	11		T136	12		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T173	6		T132	5		T141	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T35	10		T217	15		T251	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T66	6		T50	6		T90	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	2		T13	10		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1209	1			T13	8		T65	15		T131	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T47	5		T133	16		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	11		T139	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	1		T150	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1449	1			T5	1		T9	1		T34	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T215	1		T144	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	1		T55	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	1		T11	9		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	11		T43	1		T66	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T216	1		T141	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T53	11		T150	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	25		T39	4		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T65	6		T140	9		T219	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T35	11		T215	1		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T139	1		T173	7		T132	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	1		T13	11		T224	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	1		T131	12		T66	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	3		T44	2		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T13	9		T65	16		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T163	1		T30	1		T158	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T251	16		T89	1		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17752	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	10		T231	5		T234	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T133	15		T134	21		T135	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T10	12		T134	13		T227	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T136	13		T165	12		T27	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1171	1			T5	6		T9	11		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	10		T215	9		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	11		T215	7		T135	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	16		T12	5		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	11		T66	2		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T135	12		T229	11		T168	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	2		T138	7		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	13		T266	8		T233	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T65	2		T140	7		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T215	18		T136	12		T247	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T137	14		T267	3		T200	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	10		T224	6		T217	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T131	15		T66	8		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	10		T133	4		T134	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T13	12		T65	12		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T268	16		T262	5		T319	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T258	9		T259	6		T317	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T140	11		T88	3		T242	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	12		T234	1		T175	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T55	1		T228	3		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T133	12		T251	16		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T132	12		T309	11		T98	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T150	1		T47	5		T133	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	11		T13	10		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	1		T150	1		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	11		T42	1		T217	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T215	1		T52	2		T244	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	1		T55	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	1		T11	9		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	11		T43	1		T66	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	6		T216	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T150	1		T139	1		T143	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	13		T39	4		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T53	11		T65	6		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	12		T215	1		T136	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T139	1		T173	7		T132	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	11		T217	16		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T8	1		T66	7		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T8	1		T11	3		T13	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1576	1			T5	1		T9	1		T13	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T285	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T133	10		T24	9		T320	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T309	12		T250	3		T186	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T133	15		T134	21		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	12		T13	12		T134	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T136	13		T165	12		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T34	11		T217	4		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T215	9		T52	1		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	11		T215	7		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	16		T12	15		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	11		T66	2		T135	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T46	1		T229	11		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T229	11		T235	13		T56	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T48	11		T135	12		T257	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T53	2		T65	2		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T48	2		T215	18		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T137	14		T267	3		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T217	4		T235	20		T24	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T66	8		T200	20		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	10		T13	10		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1366	1			T5	6		T9	11		T13	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11