Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23159

1

T1

22

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3552

1

T8

1

T10

23

T12

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20796

1

T1

22

T2

20

T6

190

auto[1]

5915

1

T3

1

T5

7

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	18	1			T237	16		T321	2		-	-
values[0]	60	1			T271	9		T322	10		T312	16
values[1]	667	1			T139	1		T131	27		T134	22
values[2]	2789	1			T5	7		T9	12		T13	21
values[3]	589	1			T55	2		T35	1		T132	12
values[4]	759	1			T8	1		T11	13		T12	12
values[5]	684	1			T13	22		T150	1		T134	14
values[6]	682	1			T12	6		T34	22		T43	1
values[7]	741	1			T1	22		T3	1		T173	7
values[8]	724	1			T10	23		T48	38		T55	1
values[9]	1332	1			T8	2		T11	25		T12	11
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	932	1			T13	21		T42	1		T139	1
values[1]	2730	1			T5	7		T9	12		T55	1
values[2]	615	1			T35	1		T132	12		T140	39
values[3]	687	1			T8	1		T11	13		T12	12
values[4]	774	1			T34	22		T53	13		T150	1
values[5]	670	1			T3	1		T12	6		T43	1
values[6]	757	1			T1	22		T55	1		T173	7
values[7]	803	1			T10	23		T48	38		T39	4
values[8]	831	1			T8	1		T150	1		T139	1
values[9]	237	1			T8	1		T11	25		T12	11
minimum	17675	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T139	1		T131	16		T134	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T13	11		T42	1		T66	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T5	7		T9	12		T170	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	1		T163	1		T144	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T35	1		T140	12		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T132	1		T140	8		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	11		T12	12		T13	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	1		T13	13		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T34	12		T53	3		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T150	1		T139	1		T215	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T133	5		T134	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	6		T43	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	12		T55	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T163	1		T229	12		T247	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	12		T39	4		T65	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T10	13		T48	3		T46	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T139	1		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T150	1		T35	1		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T8	1		T11	17		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T12	11		T178	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T219	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T131	11		T66	3		T228	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	10		T66	6		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T225	9		T133	11		T226	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	5		T257	4		T57	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T140	11		T167	12		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T132	11		T140	8		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	2		T13	9		T220	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	8		T65	5		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	10		T53	10		T217	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T136	12		T168	14		T251	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	4		T251	4		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	5		T133	15		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	10		T173	6		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T229	11		T206	14		T285	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	12		T65	15		T240	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	10		T48	11		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	2		T224	4		T50	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T35	10		T246	6		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T11	8		T44	1		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T30	8		T237	15		T241	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T321	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T237	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T271	9		T322	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T312	14		T313	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T139	1		T131	16		T134	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T66	9		T135	5		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1433	1			T5	7		T9	12		T170	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	11		T42	1		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	1		T142	1		T138	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T55	2		T132	1		T140	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	11		T12	12		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T13	13		T65	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	13		T134	14		T217	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T150	1		T215	19		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	12		T53	3		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T12	6		T43	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	12		T3	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T141	1		T163	1		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	12		T55	1		T215	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	13		T48	3		T46	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T8	2		T11	17		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T12	11		T150	1		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T321	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T237	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T322	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T312	2		T313	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	11		T66	3		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T66	6		T227	11		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T225	9		T133	11		T226	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	10		T136	10		T144	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T167	12		T243	2		T293	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T132	11		T140	8		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	2		T140	11		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	8		T65	5		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	9		T217	13		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T137	10		T168	14		T324	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T34	10		T53	10		T133	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T132	5		T133	15		T143	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	10		T173	6		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T141	7		T167	11		T206	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	12		T305	11		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	10		T48	11		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T11	8		T44	1		T65	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T35	10		T220	3		T246	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	1		T131	12		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	11		T42	1		T66	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T5	1		T9	1		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	1		T163	1		T144	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T35	1		T140	12		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T132	12		T140	9		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	3		T12	1		T13	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T13	9		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	11		T53	11		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	1		T139	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T133	5		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T43	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	11		T55	1		T173	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T163	1		T229	12		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T48	13		T39	4		T65	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	11		T48	12		T46	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	1		T139	1		T47	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T150	1		T35	11		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T8	1		T11	9		T44	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T12	1		T178	1		T30	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T219	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T131	15		T134	21		T66	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	10		T66	8		T135	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T5	6		T9	11		T170	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T144	13		T257	4		T266	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T140	11		T138	7		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T140	7		T137	14		T24	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	10		T12	11		T13	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	12		T65	2		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	11		T53	2		T217	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T215	18		T136	12		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T133	4		T134	13		T135	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	5		T133	15		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	11		T215	7		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T229	11		T247	12		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	11		T65	12		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	12		T48	2		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T224	6		T221	9		T245	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T246	8		T267	3		T57	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T11	16		T24	9		T155	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T12	10		T241	12		T315	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T219	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T321	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T237	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T271	1		T322	10		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T312	3		T313	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T139	1		T131	12		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T66	7		T135	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T5	1		T9	1		T170	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	11		T42	1		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	1		T142	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T55	2		T132	12		T140	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	3		T12	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T13	9		T65	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	10		T134	1		T217	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T150	1		T215	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T34	11		T53	11		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T43	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	11		T3	1		T173	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T141	8		T163	1		T167	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	13		T55	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	11		T48	12		T46	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	405	1			T8	2		T11	9		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T12	1		T150	1		T35	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T271	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T312	13		T313	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T131	15		T134	21		T66	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T66	8		T135	4		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1106	1			T5	6		T9	11		T170	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	10		T136	13		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	7		T145	6		T221	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T140	7		T270	10		T200	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	10		T12	11		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	12		T65	2		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	12		T134	13		T217	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T215	18		T137	10		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T34	11		T53	2		T133	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	5		T133	15		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	11		T215	7		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T247	12		T52	1		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	11		T215	9		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	12		T48	2		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T11	16		T65	12		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	10		T220	1		T246	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11