Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23296

1

T1

22

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3415

1

T8

2

T10

23

T11

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20402

1

T2

20

T6

180

T7

20

auto[1]

6309

1

T1

22

T3

1

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	743	1			T6	10		T13	21		T34	22
values[0]	15	1			T32	1		T20	13		T325	1
values[1]	765	1			T11	25		T44	2		T139	1
values[2]	2817	1			T5	7		T9	12		T11	13
values[3]	582	1			T8	1		T65	28		T133	22
values[4]	699	1			T55	1		T65	8		T131	27
values[5]	896	1			T10	23		T12	11		T13	22
values[6]	464	1			T8	1		T140	16		T178	1
values[7]	657	1			T1	22		T12	12		T47	5
values[8]	693	1			T39	4		T42	1		T55	1
values[9]	1082	1			T3	1		T8	1		T12	6
minimum	17298	1			T2	20		T6	180		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	661	1			T11	38		T44	2		T139	3
values[1]	2776	1			T5	7		T9	12		T48	14
values[2]	676	1			T8	1		T65	28		T133	22
values[3]	741	1			T55	1		T65	8		T131	27
values[4]	784	1			T10	23		T12	11		T13	22
values[5]	560	1			T8	1		T140	16		T137	29
values[6]	506	1			T1	22		T12	12		T150	1
values[7]	804	1			T39	4		T42	1		T55	1
values[8]	1054	1			T3	1		T8	1		T12	6
values[9]	218	1			T13	21		T34	22		T53	13
minimum	17931	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T139	2		T35	1		T216	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	28		T44	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T5	7		T9	12		T170	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	3		T150	2		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T66	9		T49	3		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T65	13		T133	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T131	16		T219	6		T220	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T55	1		T65	3		T215	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	13		T48	12		T145	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	13		T12	11		T137	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T178	1		T251	1		T130	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T140	8		T137	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	12		T12	12		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T150	1		T132	1		T235	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T42	1		T173	1		T133	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	4		T55	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T3	1		T8	1		T12	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T43	1		T228	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	13		T134	22		T219	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T34	12		T53	3		T55	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T154	16		T270	11		T236	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T35	10		T229	11		T240	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	10		T44	1		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T225	9		T226	5		T301	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	11		T66	3		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T66	6		T218	4		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T65	15		T133	11		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T131	11		T220	9		T56	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T65	5		T229	11		T27	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	9		T48	12		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	10		T137	10		T220	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T251	8		T130	6		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T140	8		T137	14		T230	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	10		T47	2		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T132	5		T231	4		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T173	6		T133	15		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T132	11		T143	5		T246	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	10		T46	2		T133	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T167	12		T144	10		T175	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T13	8		T232	3		T326	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T34	10		T53	10		T223	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T154	12		T270	10		T316	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	510	1			T6	10		T13	13		T40	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T34	12		T53	3		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T32	1		T20	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T325	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T139	1		T35	1		T216	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	17		T44	1		T224	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T5	7		T9	12		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	11		T48	3		T150	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T66	9		T49	3		T267	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T65	13		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	16		T219	6		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T55	1		T65	3		T215	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	13		T48	12		T145	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T10	13		T12	11		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T178	1		T130	9		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T8	1		T140	8		T221	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	12		T12	12		T47	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T132	1		T137	15		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T42	1		T173	1		T133	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	4		T55	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T3	1		T8	1		T12	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T43	1		T143	1		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17190	1			T2	20		T6	180		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	8		T133	4		T50	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T34	10		T53	10		T223	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T20	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	10		T141	7		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	8		T44	1		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T225	9		T226	5		T301	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	2		T48	11		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T66	6		T155	11		T90	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T65	15		T133	11		T66	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	11		T218	4		T220	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T65	5		T217	13		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	9		T48	12		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	10		T137	10		T220	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T130	6		T147	2		T237	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T140	8		T243	2		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	10		T47	2		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T132	5		T137	14		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T173	6		T133	15		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T132	11		T231	4		T195	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	10		T46	2		T217	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T143	5		T167	12		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T139	2		T35	11		T216	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	12		T44	2		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T5	1		T9	1		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	12		T150	2		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T66	7		T49	1		T218	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	1		T65	16		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T131	12		T219	1		T220	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T55	1		T65	6		T215	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	10		T48	13		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	11		T12	1		T137	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T178	1		T251	9		T130	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	1		T140	9		T137	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	11		T12	1		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T150	1		T132	6		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T42	1		T173	7		T133	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T39	4		T55	1		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T3	1		T8	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T43	1		T228	1		T167	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T13	9		T134	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T34	11		T53	11		T55	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17735	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T154	13		T270	11		T236	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T229	11		T24	13		T240	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	26		T224	6		T24	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T5	6		T9	11		T170	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	2		T134	13		T66	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T66	8		T49	2		T267	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T65	12		T133	10		T217	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T131	15		T219	5		T220	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T65	2		T215	16		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	12		T48	11		T145	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	12		T12	10		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T130	6		T147	2		T316	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T140	7		T137	14		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T1	11		T12	11		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T235	13		T245	13		T258	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T133	15		T134	5		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T215	18		T246	13		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	5		T13	10		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T247	13		T144	7		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	12		T134	21		T219	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T34	11		T53	2		T223	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T136	13		T144	13		T233	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T154	15		T270	10		T316	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	492	1			T6	10		T13	9		T40	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T34	11		T53	11		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T32	1		T20	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T325	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T139	1		T35	11		T216	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	9		T44	2		T224	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T5	1		T9	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	3		T48	12		T150	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T66	7		T49	1		T267	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	1		T65	16		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	12		T219	1		T218	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T55	1		T65	6		T215	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	10		T48	13		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T10	11		T12	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T178	1		T130	9		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	1		T140	9		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	11		T12	1		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T132	6		T137	15		T244	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T42	1		T173	7		T133	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T39	4		T55	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T3	1		T8	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T43	1		T143	6		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17298	1			T2	20		T6	180		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	12		T133	4		T134	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T34	11		T53	2		T223	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T20	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T136	13		T144	13		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	16		T224	6		T134	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T5	6		T9	11		T170	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	10		T48	2		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T66	8		T49	2		T267	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T65	12		T133	10		T66	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	15		T219	5		T220	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T65	2		T215	16		T217	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	12		T48	11		T145	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	12		T12	10		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	6		T147	2		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T140	7		T221	7		T243	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T1	11		T12	11		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T137	14		T245	13		T271	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T133	15		T134	5		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T215	18		T235	13		T245	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	5		T13	10		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T247	13		T144	7		T145	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11