Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23337

1

T2

20

T5

7

T6

190

auto[ADC_CTRL_FILTER_COND_OUT]

3374

1

T1

22

T3

1

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21029

1

T1

22

T2

20

T3

1

auto[1]

5682

1

T5

7

T8

1

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	216	1			T53	13		T46	7		T163	1
values[0]	39	1			T8	1		T229	1		T144	18
values[1]	729	1			T8	1		T11	25		T150	1
values[2]	634	1			T48	24		T35	11		T141	1
values[3]	607	1			T3	1		T13	21		T39	4
values[4]	737	1			T10	23		T12	18		T13	21
values[5]	2872	1			T5	7		T8	1		T9	12
values[6]	759	1			T1	22		T55	1		T65	28
values[7]	704	1			T11	13		T48	14		T44	2
values[8]	632	1			T12	11		T150	1		T139	1
values[9]	1116	1			T13	22		T43	1		T173	7
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	627	1			T8	1		T11	25		T150	1
values[1]	597	1			T48	24		T150	1		T131	27
values[2]	625	1			T3	1		T12	6		T13	21
values[3]	2966	1			T5	7		T9	12		T10	23
values[4]	639	1			T8	1		T55	1		T139	1
values[5]	848	1			T1	22		T48	14		T55	1
values[6]	554	1			T11	13		T44	2		T47	5
values[7]	748	1			T12	11		T43	1		T150	1
values[8]	1004	1			T13	22		T46	7		T173	7
values[9]	133	1			T53	13		T327	1		T88	7
minimum	17970	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T150	1		T134	14		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T11	17		T134	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T48	12		T131	16		T135	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	1		T35	1		T219	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	13		T39	4		T133	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T3	1		T12	6		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T5	7		T9	12		T10	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	12		T13	11		T34	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T55	1		T35	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	1		T139	1		T224	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T48	3		T55	1		T65	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	12		T134	6		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	11		T47	3		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T44	1		T135	2		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T150	1		T139	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	11		T43	1		T217	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T137	11		T163	1		T167	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	13		T46	5		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T53	3		T327	1		T88	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T249	14		T328	12		T329	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17619	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T133	5		T165	13		T229	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T246	6		T227	11		T305	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	8		T229	11		T90	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	12		T131	11		T50	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	10		T57	4		T198	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	8		T133	11		T251	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T132	11		T140	7		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T10	10		T225	9		T226	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	10		T34	10		T65	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T140	11		T154	12		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T224	4		T132	5		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T48	11		T65	15		T66	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	10		T137	14		T217	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	2		T47	2		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T44	1		T146	12		T155	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T143	5		T153	9		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T217	13		T251	8		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T137	10		T167	23		T240	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	9		T46	2		T173	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T53	10		T88	3		T253	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T309	10		T330	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T133	4		T218	4		T231	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T53	3		T163	1		T145	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T46	5		T247	13		T144	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T8	1		T144	1		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T229	1		T255	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	1		T134	14		T215	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	1		T11	17		T133	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T48	12		T141	1		T135	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	1		T163	1		T219	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	13		T39	4		T131	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T3	1		T55	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	13		T42	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	18		T13	11		T34	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T5	7		T9	12		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T65	3		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T55	1		T65	13		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	12		T132	1		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	11		T48	3		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T44	1		T135	2		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T150	1		T139	1		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	11		T251	1		T147	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T137	11		T167	2		T235	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T13	13		T43	1		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T53	10		T195	7		T88	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T46	2		T144	10		T309	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T144	17		T182	11		T331	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T246	6		T227	11		T305	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	8		T133	4		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T48	12		T50	6		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T35	10		T57	4		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	8		T131	11		T133	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T132	11		T136	12		T252	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	10		T251	4		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	10		T34	10		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T225	9		T136	10		T226	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T65	5		T224	4		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T65	15		T66	6		T140	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	10		T132	5		T137	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	2		T48	11		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T44	1		T217	15		T144	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T47	2		T143	5		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T251	8		T147	2		T258	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	10		T167	23		T240	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T13	9		T173	6		T133	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	1		T134	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T11	9		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	13		T131	12		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	1		T35	11		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	9		T39	4		T133	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	1		T12	1		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T5	1		T9	1		T10	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T13	11		T34	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T55	1		T35	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T139	1		T224	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T48	12		T55	1		T65	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	11		T134	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	3		T47	5		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T44	2		T135	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T150	1		T139	1		T143	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	1		T43	1		T217	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T137	11		T163	1		T167	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	10		T46	6		T173	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T53	11		T327	1		T88	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T249	1		T328	1		T329	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17744	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T133	5		T165	1		T229	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T134	13		T221	15		T246	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	16		T134	21		T138	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	11		T131	15		T135	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T219	5		T247	13		T198	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	12		T133	10		T219	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T12	5		T215	7		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T5	6		T9	11		T10	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	11		T13	10		T34	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T140	11		T154	2		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T224	6		T215	18		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	2		T65	12		T66	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	11		T134	5		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	10		T135	12		T220	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T135	1		T146	2		T155	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T153	11		T245	10		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	10		T217	4		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T137	10		T235	20		T145	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	12		T46	1		T133	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T53	2		T88	3		T253	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T249	13		T328	11		T329	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T215	9		T130	2		T232	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T133	4		T165	12		T219	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T53	11		T163	1		T145	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T46	6		T247	1		T144	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T8	1		T144	18		T182	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T229	1		T255	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T150	1		T134	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	1		T11	9		T133	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	13		T141	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T35	11		T163	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	9		T39	4		T131	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	1		T55	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	11		T42	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	2		T13	11		T34	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T5	1		T9	1		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	1		T65	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T55	1		T65	16		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	11		T132	6		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	3		T48	12		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T44	2		T135	1		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T150	1		T139	1		T47	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T251	9		T147	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T137	11		T167	25		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T13	10		T43	1		T173	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T53	2		T145	6		T24	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T46	1		T247	12		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T331	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	13		T215	9		T246	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	16		T133	4		T134	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	11		T135	4		T220	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T219	5		T247	13		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	12		T131	15		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T215	7		T136	12		T56	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	12		T219	11		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	16		T13	10		T34	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T5	6		T9	11		T170	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T65	2		T224	6		T215	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T65	12		T66	8		T140	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	11		T134	5		T137	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	10		T48	2		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T135	1		T217	4		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T153	11		T245	10		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T12	10		T147	2		T258	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T137	10		T235	20		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	12		T133	15		T66	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11