Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23218

1

T1

22

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3493

1

T12

23

T13

64

T48

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20694

1

T1

22

T2

20

T3

1

auto[1]

6017

1

T5

7

T8

2

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	272	1			T8	1		T140	23		T141	1
values[0]	55	1			T155	21		T304	14		T254	20
values[1]	741	1			T8	1		T11	13		T55	1
values[2]	1020	1			T139	1		T35	11		T224	11
values[3]	605	1			T13	21		T55	1		T216	1
values[4]	612	1			T34	22		T65	28		T150	1
values[5]	606	1			T3	1		T10	23		T11	25
values[6]	694	1			T1	22		T13	43		T43	1
values[7]	665	1			T12	12		T42	1		T139	1
values[8]	633	1			T8	1		T12	6		T53	13
values[9]	3142	1			T5	7		T9	12		T12	11
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	796	1			T8	1		T11	13		T55	1
values[1]	955	1			T13	21		T139	1		T224	11
values[2]	685	1			T34	22		T55	1		T133	22
values[3]	597	1			T48	14		T65	28		T150	1
values[4]	542	1			T3	1		T10	23		T11	25
values[5]	689	1			T1	22		T13	43		T42	1
values[6]	2945	1			T5	7		T8	1		T9	12
values[7]	690	1			T44	2		T55	1		T134	22
values[8]	850	1			T12	11		T48	24		T150	1
values[9]	117	1			T8	1		T50	7		T155	31
minimum	17845	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T8	1		T11	11		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T216	1		T167	1		T247	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T139	1		T224	7		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T13	13		T132	1		T133	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T34	12		T133	11		T168	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	1		T138	1		T145	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T65	13		T150	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	3		T134	14		T215	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	1		T10	13		T11	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	4		T43	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	12		T139	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	24		T42	1		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T5	7		T8	1		T9	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	12		T53	3		T215	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T55	1		T134	22		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T44	1		T215	8		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T150	1		T140	12		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	11		T48	12		T46	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T8	1		T50	1		T155	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T200	1		T262	6		T331	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17587	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T65	3		T132	1		T49	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	2		T131	11		T35	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T167	11		T144	10		T220	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T224	4		T137	14		T217	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	8		T132	11		T133	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	10		T133	11		T168	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	1		T220	8		T231	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T65	15		T173	6		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	11		T218	4		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	10		T11	8		T66	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T133	4		T136	12		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	10		T153	9		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	19		T30	8		T257	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T225	9		T226	5		T301	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T53	10		T167	12		T246	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T229	11		T251	15		T57	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T44	1		T217	13		T144	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T140	11		T143	5		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	12		T46	2		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T50	6		T155	17		T302	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T262	5		T331	9		T303	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	1		T46	1		T47	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T65	5		T132	5		T285	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T8	1		T140	12		T50	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T141	1		T51	1		T220	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T155	10		T254	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T304	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	1		T11	11		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T65	3		T132	1		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T139	1		T35	1		T224	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T132	1		T133	16		T66	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T221	10		T244	1		T296	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	13		T55	1		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	12		T65	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	1		T229	1		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T10	13		T11	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T48	3		T39	4		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	12		T35	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	24		T43	1		T133	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T139	1		T153	12		T144	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	12		T42	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T12	6		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T53	3		T215	10		T217	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T5	7		T9	12		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	11		T48	12		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T140	11		T50	6		T88	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T220	3		T266	13		T332	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T155	11		T254	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T304	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	2		T131	11		T47	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T65	5		T132	5		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T35	10		T224	4		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T132	11		T133	15		T66	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T244	4		T56	3		T198	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	8		T220	8		T231	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	10		T65	15		T173	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T138	1		T218	4		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	10		T11	8		T66	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T48	11		T136	12		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	10		T227	7		T305	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	19		T133	4		T30	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	9		T144	5		T270	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T167	12		T246	6		T240	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T52	1		T251	15		T57	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T53	10		T217	13		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T225	9		T143	5		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	12		T44	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	1		T11	3		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T216	1		T167	12		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T139	1		T224	5		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	9		T132	12		T133	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	11		T133	12		T168	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T55	1		T138	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T65	16		T150	1		T173	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	12		T134	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	1		T10	11		T11	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	4		T43	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	11		T139	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	21		T42	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T5	1		T8	1		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T53	11		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	1		T134	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T44	2		T215	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T150	1		T140	12		T143	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	1		T48	13		T46	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T8	1		T50	7		T155	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T200	1		T262	6		T331	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17719	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T65	6		T132	6		T49	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	10		T131	15		T134	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T247	12		T144	7		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T224	6		T137	14		T217	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	12		T133	15		T66	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	11		T133	10		T168	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T145	6		T220	10		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T65	12		T140	7		T221	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	2		T134	13		T215	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	12		T11	16		T66	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T133	4		T135	4		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	11		T153	11		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	22		T145	9		T245	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T5	6		T9	11		T12	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	11		T53	2		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T134	21		T229	11		T235	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T215	7		T135	1		T217	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T140	11		T165	12		T227	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	10		T48	11		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T155	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T262	5		T331	8		T303	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T154	2		T155	9		T254	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T65	2		T49	2		T285	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T8	1		T140	12		T50	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T141	1		T51	1		T220	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T155	12		T254	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T304	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T11	3		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T65	6		T132	6		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T139	1		T35	11		T224	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T132	12		T133	16		T66	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T221	1		T244	5		T296	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	9		T55	1		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T34	11		T65	16		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T138	2		T229	1		T218	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T10	11		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T48	12		T39	4		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	11		T35	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	21		T43	1		T133	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T139	1		T153	10		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T42	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	1		T12	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T53	11		T215	1		T217	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T5	1		T9	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	1		T48	13		T44	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T140	11		T88	3		T260	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T220	1		T266	8		T332	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T155	9		T254	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	10		T131	15		T134	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T65	2		T49	2		T220	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T224	6		T140	7		T135	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T133	15		T66	8		T219	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T221	9		T56	1		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	12		T145	6		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	11		T65	12		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T249	11		T293	12		T309	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	12		T11	16		T66	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T48	2		T134	13		T215	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	11		T235	13		T227	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	22		T133	4		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T153	11		T144	13		T270	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	11		T145	9		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	5		T138	7		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	2		T215	9		T217	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T5	6		T9	11		T170	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	10		T48	11		T46	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11