Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23325

1

T2

20

T5

7

T6

190

auto[ADC_CTRL_FILTER_COND_OUT]

3386

1

T1

22

T3

1

T8

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20408

1

T2

20

T6

190

T7

20

auto[1]

6303

1

T1

22

T3

1

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	323	1			T43	1		T140	16		T141	8
values[0]	65	1			T220	19		T272	29		T278	17
values[1]	687	1			T66	15		T142	1		T163	1
values[2]	755	1			T1	22		T13	21		T48	14
values[3]	728	1			T10	23		T12	11		T139	1
values[4]	716	1			T8	1		T12	12		T133	22
values[5]	654	1			T3	1		T8	1		T11	25
values[6]	614	1			T34	22		T42	1		T65	28
values[7]	702	1			T8	1		T11	13		T13	22
values[8]	2896	1			T5	7		T9	12		T39	4
values[9]	905	1			T12	6		T13	21		T48	24
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T13	21		T48	14		T142	1
values[1]	686	1			T1	22		T150	1		T46	7
values[2]	825	1			T8	1		T10	23		T12	11
values[3]	649	1			T3	1		T8	1		T11	25
values[4]	649	1			T34	22		T65	8		T139	2
values[5]	599	1			T13	22		T42	1		T65	28
values[6]	2950	1			T5	7		T8	1		T9	12
values[7]	726	1			T39	4		T53	13		T55	1
values[8]	900	1			T12	6		T13	21		T48	24
values[9]	112	1			T140	16		T221	16		T240	22
minimum	17892	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	13		T48	3		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T229	12		T252	13		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T150	1		T131	16		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	12		T46	5		T140	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	11		T139	1		T215	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	1		T10	13		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T66	3		T244	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T8	1		T11	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	12		T173	1		T224	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T65	3		T139	2		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	1		T133	5		T134	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	13		T65	13		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T5	7		T9	12		T11	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T150	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T39	4		T53	3		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T47	3		T138	1		T217	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	6		T13	11		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	12		T43	1		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T221	16		T273	1		T274	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T140	8		T240	14		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17667	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T66	9		T163	1		T240	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	8		T48	11		T154	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T229	11		T252	1		T285	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	11		T57	12		T234	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	10		T46	2		T140	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T153	20		T130	6		T266	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	10		T167	12		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T66	3		T206	14		T56	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	8		T133	11		T137	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	10		T173	6		T224	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T65	5		T35	10		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T133	4		T88	3		T266	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	9		T65	15		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T11	2		T225	9		T143	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T132	11		T133	15		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T53	10		T137	10		T251	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T47	2		T138	1		T217	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	10		T44	1		T195	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T48	12		T141	7		T217	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T274	8		T101	8		T298	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T140	8		T240	8		T286	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T66	6		T240	7		T313	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T195	10		T320	13		T260	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T43	1		T140	8		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T220	11		T272	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T278	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T142	1		T51	1		T220	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T66	9		T163	1		T229	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	13		T48	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	12		T46	5		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	11		T139	1		T215	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	13		T216	1		T140	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T66	3		T153	12		T145	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T12	12		T133	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T173	1		T224	7		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T8	1		T11	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	12		T42	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T65	13		T150	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	11		T228	1		T219	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	1		T13	13		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T5	7		T9	12		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	1		T47	3		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T12	6		T13	11		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T48	12		T55	1		T134	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T195	7		T184	12		T275	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T140	8		T141	7		T251	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T220	8		T272	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T278	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T220	9		T244	4		T257	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T66	6		T229	11		T240	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	8		T48	11		T131	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	10		T46	2		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T153	11		T57	12		T281	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	10		T140	7		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T66	3		T153	9		T206	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T133	11		T137	14		T167	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T173	6		T224	4		T168	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	8		T65	5		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T34	10		T132	5		T133	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T65	15		T35	10		T220	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	2		T228	2		T30	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	9		T132	11		T133	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T225	9		T137	10		T143	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	2		T138	1		T217	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	10		T44	1		T53	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	12		T217	13		T240	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	9		T48	12		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T229	12		T252	3		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T150	1		T131	12		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	11		T46	6		T140	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T139	1		T215	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	1		T10	11		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T66	4		T244	1		T206	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T8	1		T11	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T34	11		T173	7		T224	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T65	6		T139	2		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	1		T133	5		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	10		T65	16		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T5	1		T9	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	1		T150	1		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	4		T53	11		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	5		T138	2		T217	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	1		T13	11		T44	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T48	13		T43	1		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T221	1		T273	1		T274	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T140	9		T240	9		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17751	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T66	7		T163	1		T240	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	12		T48	2		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T229	11		T252	11		T285	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T131	15		T145	9		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	11		T46	1		T140	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	10		T215	16		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	12		T154	15		T246	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T66	2		T56	2		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	16		T12	11		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	11		T224	6		T135	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T65	2		T229	11		T333	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T133	4		T134	21		T88	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	12		T65	12		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T5	6		T9	11		T11	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T133	15		T219	8		T247	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T53	2		T137	10		T243	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T217	4		T52	1		T245	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	5		T13	10		T215	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	11		T134	13		T135	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T221	15		T274	8		T260	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T140	7		T240	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T220	25		T221	9		T257	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T66	8		T240	2		T313	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T195	8		T320	1		T260	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T43	1		T140	9		T141	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T220	9		T272	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T278	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T142	1		T51	1		T220	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T66	7		T163	1		T229	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	9		T48	12		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	11		T46	6		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T139	1		T215	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	11		T216	1		T140	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T66	4		T153	10		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	1		T12	1		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T173	7		T224	5		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T8	1		T11	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	11		T42	1		T132	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T65	16		T150	1		T35	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	3		T228	3		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	1		T13	10		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T5	1		T9	1		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T150	1		T47	5		T138	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T13	11		T44	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T48	13		T55	1		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T195	9		T320	12		T260	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T140	7		T309	12		T334	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T220	10		T272	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T278	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T220	15		T221	9		T257	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T66	8		T229	11		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	12		T48	2		T131	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	11		T46	1		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	10		T215	16		T49	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	12		T140	7		T154	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T66	2		T153	11		T145	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	11		T133	10		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T224	6		T135	4		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	16		T65	2		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	11		T133	4		T134	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T65	12		T235	20		T220	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	10		T219	11		T235	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	12		T133	15		T136	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T5	6		T9	11		T170	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T217	4		T52	1		T194	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	5		T13	10		T53	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	11		T134	13		T135	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11