Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22907

1

T1

22

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3804

1

T8

2

T10

23

T12

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21109

1

T1

22

T2

20

T3

1

auto[1]

5602

1

T5

7

T8

3

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	259	1			T55	1		T135	5		T247	13
values[0]	36	1			T88	7		T285	25		T159	1
values[1]	779	1			T8	1		T12	6		T13	21
values[2]	687	1			T8	1		T13	21		T48	24
values[3]	574	1			T8	1		T34	22		T39	4
values[4]	820	1			T11	25		T131	27		T215	10
values[5]	3009	1			T1	22		T5	7		T9	12
values[6]	662	1			T10	23		T13	22		T43	1
values[7]	719	1			T55	1		T35	11		T133	31
values[8]	714	1			T53	13		T65	8		T46	7
values[9]	786	1			T3	1		T12	23		T42	1
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	715	1			T12	6		T150	1		T139	1
values[1]	638	1			T8	1		T13	21		T48	24
values[2]	700	1			T8	1		T11	25		T34	22
values[3]	3003	1			T5	7		T9	12		T170	22
values[4]	772	1			T1	22		T10	23		T11	13
values[5]	666	1			T13	22		T43	1		T35	11
values[6]	686	1			T55	1		T215	8		T135	13
values[7]	732	1			T53	13		T65	8		T46	7
values[8]	801	1			T3	1		T12	23		T42	1
values[9]	60	1			T55	1		T139	1		T51	1
minimum	17938	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	6		T139	1		T217	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T150	1		T134	6		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	12		T150	2		T219	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T13	13		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	17		T34	12		T224	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	1		T39	4		T133	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T5	7		T9	12		T170	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T215	10		T140	12		T154	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	12		T11	11		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	13		T48	3		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T43	1		T132	1		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	13		T35	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	1		T215	8		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T135	13		T142	1		T144	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T136	13		T50	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T53	3		T65	3		T46	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	1		T12	11		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	12		T139	1		T133	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T196	1		T286	1		T292	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T55	1		T139	1		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17604	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	11		T314	19		T89	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T217	13		T251	15		T291	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T228	2		T229	11		T246	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	12		T220	9		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	8		T140	7		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	8		T34	10		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T133	11		T167	11		T218	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T131	11		T225	9		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T140	11		T154	12		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	10		T11	2		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	10		T48	11		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T132	5		T133	15		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	9		T35	10		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T229	11		T198	14		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	5		T220	8		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T136	12		T50	6		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	10		T65	5		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T140	8		T244	4		T240	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T133	4		T66	6		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T286	12		T335	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T130	6		T266	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T13	10		T57	4		T198	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T237	3		T285	18		T336	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T55	1		T135	5		T247	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T88	4		T290	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T285	11		T159	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	1		T12	6		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T13	11		T228	1		T235	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	12		T219	6		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T13	13		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	12		T150	2		T224	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T8	1		T39	4		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T11	17		T131	16		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T215	10		T140	12		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T1	12		T5	7		T9	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	3		T55	1		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T43	1		T132	1		T135	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	13		T13	13		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T55	1		T133	16		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T35	1		T135	13		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T215	8		T136	13		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T53	3		T65	3		T46	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T12	11		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T12	12		T139	2		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T237	4		T285	17		T286	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T144	17		T195	7		T130	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T88	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T285	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T217	13		T251	15		T198	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	10		T228	2		T246	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	12		T220	9		T291	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	8		T229	11		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	10		T224	4		T66	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	11		T140	7		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	8		T131	11		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	11		T154	12		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T1	10		T11	2		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	11		T47	2		T173	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T132	5		T153	11		T337	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	10		T13	9		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T133	15		T49	1		T231	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T35	10		T144	5		T220	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	12		T50	6		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T53	10		T65	5		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T140	8		T51	1		T244	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	4		T66	6		T138	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T139	1		T217	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T150	1		T134	1		T228	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	13		T150	2		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	1		T13	9		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	9		T34	11		T224	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	1		T39	4		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T5	1		T9	1		T170	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T215	1		T140	12		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	11		T11	3		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	11		T48	12		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T43	1		T132	6		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	10		T35	11		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T55	1		T215	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T135	1		T142	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T136	13		T50	7		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T53	11		T65	6		T46	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T12	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T139	1		T133	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T196	1		T286	13		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T55	1		T139	1		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17702	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	11		T314	1		T89	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T12	5		T217	4		T198	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T134	5		T229	11		T235	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	11		T219	5		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	12		T140	7		T154	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	16		T34	11		T224	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T133	10		T134	21		T130	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T5	6		T9	11		T170	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T215	9		T140	11		T154	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	11		T11	10		T65	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	12		T48	2		T219	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T133	15		T135	1		T165	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	12		T137	10		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T215	7		T229	11		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T135	12		T144	13		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T136	12		T52	1		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T53	2		T65	2		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	10		T140	7		T240	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	11		T133	4		T66	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T292	19		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T130	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T24	9		T88	3		T184	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T13	10		T314	18		T198	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T237	5		T285	18		T336	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T55	1		T135	1		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T88	4		T290	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T285	15		T159	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T12	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T13	11		T228	3		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	13		T219	1		T220	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	1		T13	9		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T34	11		T150	2		T224	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T39	4		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	9		T131	12		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T215	1		T140	12		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T1	11		T5	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T48	12		T55	1		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	1		T132	6		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	11		T13	10		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T55	1		T133	16		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	11		T135	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T215	1		T136	13		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T53	11		T65	6		T46	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T12	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	1		T139	2		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T237	2		T285	17		T292	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T135	4		T247	12		T195	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T88	3		T290	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T285	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T12	5		T217	4		T24	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	10		T235	20		T246	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	11		T219	5		T220	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	12		T134	5		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	11		T224	6		T66	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T133	10		T134	21		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	16		T131	15		T136	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T215	9		T140	11		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T1	11		T5	6		T9	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T48	2		T144	7		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T135	1		T165	12		T247	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	12		T13	12		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T133	15		T235	13		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	12		T144	13		T220	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T215	7		T136	12		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	2		T65	2		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	10		T140	7		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	11		T133	4		T134	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11