Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	1		T48	13		T133	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	1		T11	9		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T131	12		T35	11		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	1		T133	12		T136	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	9		T39	4		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T12	1		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T5	1		T9	1		T10	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	1		T13	11		T34	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T55	1		T35	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	1		T65	6		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T48	12		T55	1		T65	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	11		T134	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	5		T141	8		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	3		T44	2		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T139	1		T143	6		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	10		T43	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	1		T137	11		T167	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T46	6		T133	16		T66	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T53	11		T163	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T88	4		T200	22		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17684	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T165	1		T182	11		T250	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	11		T133	4		T134	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	16		T134	21		T138	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T131	15		T135	4		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T133	10		T136	12		T219	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	12		T215	7		T219	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T12	5		T140	7		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T5	6		T9	11		T10	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	11		T13	10		T34	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T140	11		T154	2		T246	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T65	2		T224	6		T215	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	2		T65	12		T66	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	11		T134	5		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T135	12		T220	1		T230	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	10		T135	1		T146	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T153	11		T245	10		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	12		T217	4		T258	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	10		T137	10		T145	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	1		T133	15		T66	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T53	2		T235	20		T24	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T88	3		T200	20		T249	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T165	12		T250	10		T254	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T244	1		T181	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T144	18		T182	12		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T229	13		T256	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T133	5		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T11	9		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T48	13		T35	11		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T134	1		T141	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	11		T13	9		T131	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T55	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	4		T42	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	2		T13	11		T34	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T5	1		T9	1		T55	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T65	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T65	16		T35	1		T66	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	11		T132	6		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	12		T141	8		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	3		T44	2		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T139	1		T47	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T43	1		T150	1		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T53	11		T137	11		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	424	1			T13	10		T46	6		T173	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T229	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	4		T134	13		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	16		T138	7		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	11		T135	4		T220	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T134	21		T219	5		T247	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	12		T13	12		T131	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T133	10		T136	12		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T219	11		T52	1		T194	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	16		T13	10		T34	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T5	6		T9	11		T170	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T65	2		T224	6		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T65	12		T66	8		T136	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	11		T134	5		T215	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	2		T135	12		T144	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	10		T135	1		T217	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	10		T153	11		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T258	9		T259	13		T260	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T53	2		T137	10		T235	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T13	12		T46	1		T133	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11