Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20858

1

T2

20

T3

1

T6

190

auto[ADC_CTRL_FILTER_COND_OUT]

5853

1

T1

22

T5

7

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20777

1

T2

20

T3

1

T6

190

auto[1]

5934

1

T1

22

T5

7

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T163	1		-	-		-	-
values[0]	41	1			T231	5		T222	1		T98	9
values[1]	626	1			T10	23		T13	22		T150	1
values[2]	595	1			T8	1		T34	22		T42	1
values[3]	660	1			T12	12		T55	1		T215	18
values[4]	636	1			T1	22		T3	1		T11	25
values[5]	809	1			T65	8		T150	1		T46	7
values[6]	780	1			T48	24		T39	4		T53	13
values[7]	760	1			T48	14		T139	1		T173	7
values[8]	526	1			T8	1		T35	11		T215	19
values[9]	3611	1			T5	7		T8	1		T9	12
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	769	1			T10	23		T13	22		T139	1
values[1]	2839	1			T5	7		T8	1		T9	12
values[2]	619	1			T12	23		T55	1		T215	18
values[3]	773	1			T3	1		T11	25		T12	6
values[4]	799	1			T1	22		T53	13		T150	1
values[5]	740	1			T48	38		T39	4		T55	1
values[6]	718	1			T139	1		T35	11		T173	7
values[7]	633	1			T8	1		T13	21		T131	27
values[8]	975	1			T8	1		T11	13		T13	21
values[9]	170	1			T163	1		T145	7		T251	16
minimum	17676	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T47	3		T132	1		T133	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T10	13		T13	13		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	1		T150	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1525	1			T5	7		T9	12		T34	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	11		T215	10		T144	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	12		T55	1		T215	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	1		T11	17		T12	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T43	1		T153	12		T235	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T216	1		T141	1		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	12		T53	3		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T48	15		T39	4		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T65	3		T140	8		T219	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T35	1		T136	13		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T139	1		T173	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	11		T224	7		T215	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T131	16		T66	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T11	11		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T13	13		T65	13		T133	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T163	1		T145	7		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T251	1		T89	1		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17567	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T261	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	2		T132	11		T133	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	10		T13	9		T138	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T136	10		T51	1		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1120	1			T34	10		T225	9		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T144	5		T244	4		T195	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T252	1		T57	12		T237	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	8		T46	2		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T153	9		T52	1		T56	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T167	12		T168	14		T220	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	10		T53	10		T66	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	23		T218	4		T251	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T65	5		T140	8		T181	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T35	10		T136	12		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T173	6		T132	5		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	10		T224	4		T217	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T131	11		T66	6		T144	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	2		T44	1		T133	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	8		T65	15		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T158	1		T262	5		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T251	15		T258	8		T16	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T163	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T222	1		T98	1		T186	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T231	1		T98	1		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	1		T47	3		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	13		T13	13		T134	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T150	1		T133	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T34	12		T42	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T215	10		T163	1		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	12		T55	1		T215	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	1		T11	17		T12	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	12		T43	1		T66	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T46	5		T216	1		T140	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T65	3		T150	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T48	12		T39	4		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	3		T140	8		T138	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T48	3		T136	13		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T139	1		T173	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T35	1		T215	19		T217	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T8	1		T66	9		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T8	1		T11	11		T13	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1787	1			T5	7		T9	12		T13	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T98	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T231	4		T265	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T47	2		T132	11		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	10		T13	9		T206	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T133	15		T136	10		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	10		T138	1		T217	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T244	4		T27	9		T195	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T137	10		T144	10		T57	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	8		T154	12		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	10		T66	3		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	2		T140	7		T167	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T65	5		T246	6		T56	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	12		T218	4		T251	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	10		T140	8		T143	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	11		T136	12		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T173	6		T132	5		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	10		T217	15		T251	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T66	6		T141	7		T50	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	2		T13	10		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1234	1			T13	8		T65	15		T131	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	5		T132	12		T133	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	11		T13	10		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T8	1		T150	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1455	1			T5	1		T9	1		T34	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	1		T215	1		T144	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	1		T55	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T11	9		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	1		T153	10		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T216	1		T141	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	11		T53	11		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T48	25		T39	4		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T65	6		T140	9		T219	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	11		T136	13		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T139	1		T173	7		T132	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	11		T224	5		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T8	1		T131	12		T66	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	1		T11	3		T44	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	9		T65	16		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T163	1		T145	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T251	16		T89	1		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17668	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T261	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T133	15		T140	11		T135	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	12		T13	12		T134	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T136	13		T165	12		T52	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1190	1			T5	6		T9	11		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	10		T215	9		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T12	11		T215	7		T135	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	16		T12	5		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T153	11		T235	13		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T135	12		T168	10		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	11		T53	2		T66	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T48	13		T155	13		T266	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T65	2		T140	7		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T136	12		T247	12		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T137	14		T267	3		T200	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	10		T224	6		T215	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T131	15		T66	8		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	10		T133	4		T134	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T13	12		T65	12		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T145	6		T268	16		T262	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T258	9		T16	9		T259	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T269	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T163	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T222	1		T98	8		T186	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T231	5		T98	1		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T150	1		T47	5		T132	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	11		T13	10		T134	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	1		T150	1		T133	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	11		T42	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T215	1		T163	1		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	1		T55	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T11	9		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	11		T43	1		T66	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	6		T216	1		T140	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T65	6		T150	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T48	13		T39	4		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	11		T140	9		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T48	12		T136	13		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T139	1		T173	7		T132	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T35	11		T215	1		T217	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	1		T66	7		T141	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T8	1		T11	3		T13	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1617	1			T5	1		T9	1		T13	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T186	3		T269	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T265	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T140	11		T135	4		T88	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	12		T13	12		T134	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T133	15		T136	13		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T34	11		T217	4		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T215	9		T52	1		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	11		T215	7		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	16		T12	15		T49	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	11		T66	2		T135	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	1		T140	7		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T65	2		T235	13		T246	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	11		T135	12		T257	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	2		T140	7		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	2		T136	12		T221	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T137	14		T267	3		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T215	18		T217	4		T247	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T66	8		T200	20		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	10		T13	10		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1404	1			T5	6		T9	11		T13	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11