Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23397

1

T2

20

T5

7

T6

190

auto[ADC_CTRL_FILTER_COND_OUT]

3314

1

T1

22

T3

1

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20513

1

T2

20

T6

190

T7

20

auto[1]

6198

1

T1

22

T3

1

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T43	1		T195	17		T98	1
values[0]	85	1			T220	19		T186	8		T272	29
values[1]	691	1			T66	15		T142	1		T163	1
values[2]	762	1			T1	22		T13	21		T48	14
values[3]	663	1			T10	23		T12	23		T139	1
values[4]	757	1			T8	1		T65	8		T133	22
values[5]	610	1			T3	1		T8	1		T11	25
values[6]	681	1			T34	22		T65	28		T35	11
values[7]	673	1			T8	1		T11	13		T13	22
values[8]	2849	1			T5	7		T9	12		T39	4
values[9]	1225	1			T12	6		T13	21		T48	24
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	943	1			T13	21		T48	14		T66	15
values[1]	667	1			T1	22		T150	1		T46	7
values[2]	823	1			T8	1		T10	23		T12	11
values[3]	650	1			T3	1		T8	1		T12	12
values[4]	651	1			T11	25		T34	22		T65	8
values[5]	627	1			T13	22		T42	1		T65	28
values[6]	2907	1			T5	7		T8	1		T9	12
values[7]	768	1			T39	4		T44	2		T53	13
values[8]	846	1			T12	6		T13	21		T48	24
values[9]	163	1			T55	1		T140	16		T24	10
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	13		T48	3		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T66	9		T163	1		T229	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T150	1		T131	16		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	12		T46	5		T140	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	1		T12	11		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	13		T167	2		T154	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T66	3		T244	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T8	1		T12	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	12		T173	1		T224	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	17		T65	3		T139	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T42	1		T133	5		T134	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	13		T65	13		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T5	7		T9	12		T11	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T150	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T39	4		T44	1		T53	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T55	1		T47	3		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T12	6		T13	11		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T48	12		T43	1		T134	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T273	1		T274	9		T101	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T55	1		T140	8		T24	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	8		T48	11		T154	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T66	6		T229	11		T240	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T131	11		T144	10		T234	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	10		T46	2		T140	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T153	20		T57	12		T130	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	10		T167	23		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T66	3		T206	14		T56	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T137	14		T146	12		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T34	10		T173	6		T224	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	8		T65	5		T35	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T133	4		T88	3		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	9		T65	15		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T11	2		T225	9		T143	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T132	11		T133	15		T144	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	1		T53	10		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	2		T138	1		T217	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	10		T195	7		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	12		T141	7		T217	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T274	8		T101	8		T275	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T140	8		T240	8		T276	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T195	10		T261	2		T277	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T43	1		T98	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T220	11		T186	8		T272	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T278	8		T279	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T142	1		T51	1		T220	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T66	9		T163	1		T229	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	13		T48	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	12		T46	5		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	11		T139	1		T215	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	13		T12	12		T140	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	1		T153	12		T145	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T65	3		T133	11		T137	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T42	1		T173	1		T224	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T8	1		T11	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T34	12		T132	1		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T65	13		T35	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	11		T141	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	1		T13	13		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T5	7		T9	12		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	1		T150	1		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T12	6		T13	11		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T48	12		T55	1		T134	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T195	7		T261	1		T280	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T220	8		T272	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T278	9		T279	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T220	9		T244	4		T257	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T66	6		T229	11		T240	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	8		T48	11		T131	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	10		T46	2		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T153	11		T57	12		T281	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	10		T140	7		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T153	9		T206	14		T56	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T65	5		T133	11		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T173	6		T224	4		T66	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	8		T229	11		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T34	10		T132	5		T133	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T65	15		T35	10		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	2		T143	5		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	9		T132	11		T133	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T225	9		T137	10		T226	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	2		T138	1		T217	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	10		T44	1		T53	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T48	12		T140	8		T141	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T13	9		T48	12		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T66	7		T163	1		T229	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T150	1		T131	12		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	11		T46	6		T140	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	1		T12	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	11		T167	25		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T66	4		T244	1		T206	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T8	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T34	11		T173	7		T224	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	9		T65	6		T139	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T42	1		T133	5		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T13	10		T65	16		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T5	1		T9	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	1		T150	1		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	4		T44	2		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	1		T47	5		T138	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T13	11		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T48	13		T43	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T273	1		T274	9		T101	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T55	1		T140	9		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	12		T48	2		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T66	8		T229	11		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T131	15		T144	7		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	11		T46	1		T140	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	10		T215	16		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	12		T154	15		T246	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T66	2		T56	2		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	11		T137	14		T146	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	11		T224	6		T135	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	16		T65	2		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T133	4		T134	21		T88	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	12		T65	12		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T5	6		T9	11		T11	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T133	15		T219	8		T247	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T53	2		T134	5		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T217	4		T52	1		T200	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	5		T13	10		T215	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T48	11		T134	13		T135	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T274	8		T101	8		T282	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T140	7		T24	9		T240	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T195	8		T261	2		T277	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T43	1		T98	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T220	9		T186	1		T272	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T278	10		T279	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T142	1		T51	1		T220	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T66	7		T163	1		T229	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	9		T48	12		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	11		T46	6		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T139	1		T215	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	11		T12	1		T140	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	1		T153	10		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T65	6		T133	12		T137	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T42	1		T173	7		T224	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	1		T8	1		T11	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	11		T132	6		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T65	16		T35	11		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	3		T141	1		T143	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T13	10		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T5	1		T9	1		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T55	1		T150	1		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T12	1		T13	11		T44	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T48	13		T55	1		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T195	9		T261	1		T280	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T220	10		T186	7		T272	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T278	7		T279	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T220	15		T221	9		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T66	8		T229	11		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	12		T48	2		T131	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	11		T46	1		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	10		T215	16		T49	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	12		T12	11		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	11		T145	6		T56	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T65	2		T133	10		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T224	6		T66	2		T135	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	16		T229	11		T146	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	11		T133	4		T134	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T65	12		T235	20		T220	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	10		T219	11		T235	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	12		T133	15		T136	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T5	6		T9	11		T170	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T217	4		T52	1		T267	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T12	5		T13	10		T53	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	11		T134	13		T140	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11