Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22922

1

T1

22

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3789

1

T8

2

T10

23

T12

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21109

1

T1

22

T2

20

T3

1

auto[1]

5602

1

T5

7

T8

3

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T55	1		T283	1		T284	5
values[0]	105	1			T88	7		T175	14		T285	25
values[1]	670	1			T8	1		T12	6		T13	21
values[2]	753	1			T8	1		T13	21		T48	24
values[3]	502	1			T8	1		T34	22		T150	2
values[4]	912	1			T11	25		T39	4		T65	28
values[5]	2949	1			T5	7		T9	12		T11	13
values[6]	706	1			T1	22		T10	23		T13	22
values[7]	705	1			T55	1		T35	11		T133	31
values[8]	659	1			T53	13		T65	8		T215	27
values[9]	1052	1			T3	1		T12	23		T42	1
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	980	1			T8	1		T12	6		T13	21
values[1]	597	1			T48	24		T150	1		T140	15
values[2]	739	1			T8	2		T11	25		T13	21
values[3]	2961	1			T5	7		T9	12		T55	1
values[4]	886	1			T1	22		T10	23		T11	13
values[5]	568	1			T13	22		T43	1		T132	6
values[6]	714	1			T55	1		T35	11		T215	8
values[7]	731	1			T53	13		T46	7		T35	1
values[8]	760	1			T3	1		T12	12		T42	1
values[9]	109	1			T12	11		T55	1		T139	1
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	1		T12	6		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T13	11		T150	1		T134	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	12		T150	1		T219	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T140	8		T154	16		T267	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	17		T34	12		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	2		T13	13		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T5	7		T9	12		T170	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T55	1		T215	10		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	12		T11	11		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	13		T48	3		T47	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T43	1		T132	1		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	13		T216	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T55	1		T215	8		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T35	1		T135	13		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T136	13		T50	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T53	3		T46	5		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	1		T42	1		T140	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	12		T65	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T12	11		T285	3		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T55	1		T139	1		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T217	13		T251	15		T88	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T13	10		T228	2		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	12		T220	9		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T140	7		T154	12		T56	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	8		T34	10		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	8		T133	11		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T131	11		T225	9		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T140	11		T154	12		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	10		T11	2		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	10		T48	11		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T132	5		T133	15		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	9		T137	10		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T229	11		T198	14		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	10		T144	5		T220	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T136	12		T50	6		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T53	10		T46	2		T138	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T140	8		T244	4		T240	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T65	5		T133	4		T66	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T285	7		T286	12		T287	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T130	6		T266	1		T258	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T283	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T55	1		T284	1		T288	25
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T88	4		T289	7		T290	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T175	7		T285	11		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	1		T12	6		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	11		T228	1		T235	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	12		T219	6		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T8	1		T13	13		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	12		T150	2		T224	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T8	1		T133	11		T134	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T11	17		T65	13		T131	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	4		T215	10		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T5	7		T9	12		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T48	3		T55	1		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	12		T43	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	13		T13	13		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T55	1		T133	16		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T35	1		T216	1		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T215	8		T136	13		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T53	3		T65	3		T215	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	1		T12	11		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T12	12		T46	5		T139	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T284	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T88	3		T289	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T175	7		T285	14		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T217	13		T251	15		T198	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	10		T228	2		T246	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	12		T220	9		T291	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	8		T229	11		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	10		T224	4		T141	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T133	11		T140	7		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	8		T65	15		T131	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T140	11		T167	11		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T11	2		T225	9		T132	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	11		T47	2		T173	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	10		T44	1		T132	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	10		T13	9		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T133	15		T49	1		T90	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	10		T144	5		T220	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T136	12		T50	6		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T53	10		T65	5		T167	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T140	8		T51	1		T244	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T46	2		T133	4		T66	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	1		T12	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T13	11		T150	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	13		T150	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T140	8		T154	13		T267	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	9		T34	11		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	2		T13	9		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T5	1		T9	1		T170	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T55	1		T215	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T1	11		T11	3		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	11		T48	12		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T43	1		T132	6		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	10		T216	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T55	1		T215	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	11		T135	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T136	13		T50	7		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T53	11		T46	6		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T42	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T65	6		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T12	1		T285	8		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T55	1		T139	1		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T12	5		T217	4		T24	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T13	10		T134	5		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	11		T219	5		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T140	7		T154	15		T267	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	16		T34	11		T224	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	12		T133	10		T134	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T5	6		T9	11		T170	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T215	9		T140	11		T154	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	11		T11	10		T65	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	12		T48	2		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T133	15		T135	1		T247	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T13	12		T137	10		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T215	7		T229	11		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T135	12		T144	13		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T136	12		T52	1		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T53	2		T46	1		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	7		T240	13		T234	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	11		T65	2		T133	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T12	10		T285	2		T292	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T130	6		T253	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T283	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T55	1		T284	5		T288	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T88	4		T289	5		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T175	8		T285	15		T149	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	1		T12	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	11		T228	3		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	13		T219	1		T220	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	1		T13	9		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	11		T150	2		T224	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	1		T133	12		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T11	9		T65	16		T131	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	4		T215	1		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T5	1		T9	1		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	12		T55	1		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	11		T43	1		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	11		T13	10		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T55	1		T133	16		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T35	11		T216	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T215	1		T136	13		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T53	11		T65	6		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T12	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T12	1		T46	6		T139	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T288	23		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T88	3		T289	6		T290	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T175	6		T285	10		T293	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	5		T217	4		T267	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	10		T235	20		T246	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T48	11		T219	5		T220	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	12		T134	5		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T34	11		T224	6		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T133	10		T134	21		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	16		T65	12		T131	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T215	9		T140	11		T219	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T5	6		T9	11		T11	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	2		T49	2		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	11		T135	1		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	12		T13	12		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T133	15		T235	13		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T135	12		T144	13		T220	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T215	7		T136	12		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T53	2		T65	2		T215	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	10		T140	7		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T12	11		T46	1		T133	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11