Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23293

1

T1

22

T2

20

T5

7

auto[ADC_CTRL_FILTER_COND_OUT]

3418

1

T3

1

T8

2

T11

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20479

1

T1

22

T2

20

T3

1

auto[1]

6232

1

T5

7

T8

1

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	192	1			T150	1		T215	8		T66	6
values[0]	1	1			T8	1		-	-		-	-
values[1]	793	1			T11	25		T48	14		T55	1
values[2]	584	1			T55	1		T150	1		T35	1
values[3]	669	1			T1	22		T13	21		T65	28
values[4]	3051	1			T5	7		T9	12		T12	18
values[5]	748	1			T12	11		T43	1		T47	5
values[6]	657	1			T139	1		T134	28		T140	23
values[7]	769	1			T39	4		T42	1		T44	2
values[8]	646	1			T13	43		T34	22		T55	1
values[9]	935	1			T3	1		T8	2		T10	23
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	790	1			T48	14		T55	2		T150	1
values[1]	545	1			T150	1		T35	1		T132	6
values[2]	715	1			T1	22		T12	6		T13	21
values[3]	3022	1			T5	7		T9	12		T12	12
values[4]	691	1			T12	11		T43	1		T215	10
values[5]	674	1			T44	2		T53	13		T139	1
values[6]	929	1			T13	22		T34	22		T39	4
values[7]	622	1			T3	1		T8	1		T10	23
values[8]	740	1			T8	1		T11	13		T65	8
values[9]	98	1			T163	1		T229	23		T145	7
minimum	17885	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T55	1		T150	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T48	3		T55	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T133	5		T247	14		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	1		T35	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	12		T12	6		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	14		T178	1		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T5	7		T9	12		T170	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	12		T48	12		T133	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	11		T151	1		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	1		T215	10		T217	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T44	1		T53	3		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T133	11		T134	22		T140	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T39	4		T173	1		T134	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T13	13		T34	12		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	13		T55	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T8	1		T13	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T65	3		T215	8		T66	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	1		T11	11		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T229	12		T145	7		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T163	1		T88	4		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	17		T46	5		T251	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T154	12		T237	4		T239	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	11		T144	17		T246	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T133	4		T220	9		T244	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T132	5		T51	1		T57	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	10		T13	10		T65	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T136	10		T234	1		T285	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T47	2		T225	9		T224	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	12		T133	15		T168	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T220	8		T251	15		T266	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T217	15		T49	1		T240	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T44	1		T53	10		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T133	11		T140	11		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T173	6		T137	24		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	9		T34	10		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	10		T141	7		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	8		T243	2		T240	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T65	5		T66	3		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	2		T131	11		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T229	11		T295	3		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T88	3		T294	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T11	8		T46	2		T251	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T215	8		T66	3		T135	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T150	1		T228	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T8	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T55	1		T150	1		T216	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	17		T48	3		T46	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T247	14		T51	1		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	1		T150	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	12		T13	11		T65	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T296	1		T89	1		T57	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T5	7		T9	12		T12	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	12		T48	12		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	11		T47	3		T138	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	1		T215	10		T217	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T139	1		T134	6		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T134	22		T140	12		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T39	4		T44	1		T53	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T42	1		T35	1		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	1		T134	14		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	26		T34	12		T243	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	13		T65	3		T140	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	1		T8	2		T11	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T66	3		T229	11		T239	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T88	3		T198	14		T294	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T154	12		T237	4		T242	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	8		T48	11		T46	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T220	9		T17	2		T239	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T132	5		T246	14		T181	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	10		T13	10		T65	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T57	12		T285	17		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T225	9		T224	4		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	12		T133	15		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	2		T217	13		T220	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T217	15		T49	1		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T153	11		T144	10		T220	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T140	11		T228	2		T56	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T44	1		T53	10		T173	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	10		T133	11		T66	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T141	7		T137	14		T138	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	17		T34	10		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T10	10		T65	5		T140	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	2		T131	11		T143	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T55	1		T150	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	12		T55	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	5		T247	1		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T150	1		T35	1		T132	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T1	11		T12	1		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	11		T178	1		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T5	1		T9	1		T170	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T48	13		T133	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T151	1		T220	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T43	1		T215	1		T217	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	2		T53	11		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T133	12		T134	1		T140	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T39	4		T173	7		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	10		T34	11		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	11		T55	1		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T8	1		T13	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T65	6		T215	1		T66	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	1		T11	3		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T229	12		T145	1		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T163	1		T88	4		T294	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17686	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T11	9		T46	6		T251	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T154	15		T267	3		T249	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	2		T215	18		T219	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	4		T247	13		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T24	5		T245	10		T57	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	11		T12	5		T13	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T136	13		T267	9		T234	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T5	6		T9	11		T170	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	11		T48	11		T133	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	10		T220	10		T266	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T215	9		T217	4		T219	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T53	2		T134	5		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T133	10		T134	21		T140	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T134	13		T137	24		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	12		T34	11		T66	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	12		T153	11		T56	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	12		T235	20		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T65	2		T215	7		T66	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	10		T131	15		T135	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T229	11		T145	6		T295	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T88	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T297	12		T298	9		T282	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T11	16		T46	1		T27	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T215	1		T66	4		T135	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T150	1		T228	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T8	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	1		T150	1		T216	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	9		T48	12		T46	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T247	1		T51	1		T220	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	1		T150	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	11		T13	11		T65	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T296	1		T89	1		T57	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T5	1		T9	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T48	13		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	1		T47	5		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T43	1		T215	1		T217	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T139	1		T134	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T134	1		T140	12		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T39	4		T44	2		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T42	1		T35	11		T133	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	1		T134	1		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	19		T34	11		T243	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	11		T65	6		T140	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T8	2		T11	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T215	7		T66	2		T135	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T88	3		T198	9		T299	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T154	15		T267	3		T249	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	16		T48	2		T46	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T247	13		T220	15		T24	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T215	18		T246	13		T24	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	11		T13	10		T65	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T57	10		T249	11		T285	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T5	6		T9	11		T12	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	11		T48	11		T133	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	10		T138	7		T217	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T215	9		T217	4		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T134	5		T144	7		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T134	21		T140	11		T221	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T53	2		T137	10		T229	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T133	10		T66	8		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T134	13		T137	14		T49	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	24		T34	11		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	12		T65	2		T140	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	10		T131	15		T135	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11