Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23190

1

T1

22

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3521

1

T12

23

T13

64

T48

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20850

1

T1

22

T2

20

T3

1

auto[1]

5861

1

T5

7

T8

2

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	50	1			T101	23		T255	1		T300	1
values[0]	28	1			T47	5		T132	6		T49	3
values[1]	739	1			T8	1		T55	1		T65	8
values[2]	1011	1			T11	13		T139	1		T35	11
values[3]	690	1			T13	21		T34	22		T55	1
values[4]	517	1			T65	28		T150	1		T173	7
values[5]	668	1			T3	1		T10	23		T11	25
values[6]	672	1			T1	22		T13	21		T43	1
values[7]	621	1			T12	12		T42	1		T139	1
values[8]	671	1			T8	1		T12	6		T53	13
values[9]	3378	1			T5	7		T8	1		T9	12
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	991	1			T8	1		T11	13		T55	1
values[1]	987	1			T13	21		T139	1		T224	11
values[2]	696	1			T34	22		T55	1		T150	1
values[3]	551	1			T48	14		T65	28		T173	7
values[4]	531	1			T3	1		T10	23		T11	25
values[5]	683	1			T1	22		T13	43		T42	1
values[6]	2881	1			T5	7		T8	1		T9	12
values[7]	763	1			T44	2		T55	1		T134	22
values[8]	761	1			T46	7		T140	23		T136	24
values[9]	201	1			T8	1		T12	11		T48	24
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T8	1		T11	11		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T65	3		T139	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T139	1		T224	7		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T13	13		T132	1		T133	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T34	12		T150	1		T133	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T55	1		T145	7		T220	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T65	13		T173	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	3		T134	14		T215	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T10	13		T11	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T39	4		T43	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	12		T139	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	24		T42	1		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T5	7		T8	1		T9	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	12		T53	3		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	1		T134	22		T135	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T44	1		T215	18		T217	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T46	5		T140	12		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T229	12		T51	1		T220	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T8	1		T150	1		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T12	11		T48	12		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	2		T131	11		T47	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T65	5		T132	5		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T224	4		T137	14		T217	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	8		T132	11		T133	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	10		T133	11		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T220	8		T240	8		T175	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T65	15		T173	6		T141	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	11		T136	12		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	10		T11	8		T66	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T133	4		T154	12		T266	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	10		T153	9		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	19		T30	8		T257	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T225	9		T226	5		T301	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	10		T167	12		T246	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T251	15		T57	4		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	1		T217	13		T144	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	2		T140	11		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T229	11		T220	3		T146	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T50	6		T155	17		T302	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T48	12		T232	5		T262	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T101	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T255	1		T300	1		T303	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T47	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T132	1		T49	3		T304	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	1		T55	1		T131	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T65	3		T139	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	11		T139	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T66	9		T219	21		T247	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	12		T168	11		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	13		T55	1		T133	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T65	13		T150	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	1		T218	1		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T10	13		T11	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	13		T48	3		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	12		T35	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	11		T43	1		T133	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T139	1		T178	1		T153	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	12		T42	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	1		T12	6		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T53	3		T215	10		T217	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T5	7		T8	1		T9	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T12	11		T48	12		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T101	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T303	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T47	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T132	5		T304	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T131	11		T154	12		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T65	5		T132	11		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	2		T35	10		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T66	6		T153	11		T144	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	10		T168	14		T231	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	8		T133	15		T220	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T65	15		T173	6		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T138	1		T218	4		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	10		T11	8		T66	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	9		T48	11		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	10		T227	7		T305	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	10		T133	4		T30	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T153	9		T270	10		T200	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T167	12		T246	6		T240	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T49	1		T144	5		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T53	10		T217	13		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T46	2		T225	9		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T48	12		T44	1		T229	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T8	1		T11	3		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T65	6		T139	1		T132	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T139	1		T224	5		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T13	9		T132	12		T133	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	11		T150	1		T133	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	1		T145	1		T220	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T65	16		T173	7		T141	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	12		T134	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	1		T10	11		T11	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	4		T43	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	11		T139	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	21		T42	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T5	1		T8	1		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T53	11		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T55	1		T134	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T44	2		T215	2		T217	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T46	6		T140	12		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T229	12		T51	1		T220	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T8	1		T150	1		T50	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T12	1		T48	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T11	10		T131	15		T134	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T65	2		T49	2		T247	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T224	6		T137	14		T217	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T13	12		T133	15		T66	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T34	11		T133	10		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T145	6		T220	10		T24	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T65	12		T233	2		T223	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	2		T134	13		T215	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	12		T11	16		T66	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T133	4		T135	4		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	11		T153	11		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	22		T145	9		T245	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T5	6		T9	11		T12	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	11		T53	2		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T134	21		T135	1		T235	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T215	16		T217	4		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	1		T140	11		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T229	11		T220	1		T146	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T155	13		T306	7		T307	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T12	10		T48	11		T259	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T101	14		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T255	1		T300	1		T303	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T47	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T132	6		T49	1		T304	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	1		T55	1		T131	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T65	6		T139	1		T132	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	3		T139	1		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T66	7		T219	2		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	11		T168	15		T231	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	9		T55	1		T133	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T65	16		T150	1		T173	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	2		T218	5		T51	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T10	11		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	10		T48	12		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	11		T35	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	11		T43	1		T133	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T139	1		T178	1		T153	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	1		T42	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	1		T12	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	11		T215	1		T217	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T5	1		T8	1		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T12	1		T48	13		T44	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T101	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T303	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T49	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T131	15		T134	5		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T65	2		T220	15		T285	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	10		T224	6		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T66	8		T219	19		T247	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	11		T168	10		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	12		T133	15		T145	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T65	12		T133	10		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T24	5		T249	11		T293	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	12		T11	16		T66	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	12		T48	2		T134	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	11		T235	13		T227	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	10		T133	4		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T153	11		T270	10		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	11		T145	9		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	5		T138	7		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	2		T215	9		T217	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T5	6		T9	11		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	10		T48	11		T215	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11