Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

22

T2

20

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23148

1

T1

22

T2

20

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3563

1

T8

1

T10

23

T12

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20786

1

T1

22

T2

20

T6

190

auto[1]

5925

1

T3

1

T5

7

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22717

1

T1

12

T2

20

T3

1

auto[1]

3994

1

T1

10

T10

10

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	223	1			T8	1		T44	2		T139	1
values[0]	40	1			T312	16		T313	24		-	-
values[1]	664	1			T139	1		T131	27		T66	21
values[2]	2812	1			T5	7		T9	12		T13	21
values[3]	530	1			T55	1		T35	1		T132	12
values[4]	745	1			T8	1		T11	13		T12	12
values[5]	777	1			T13	22		T53	13		T150	1
values[6]	694	1			T12	6		T34	22		T43	1
values[7]	730	1			T1	22		T3	1		T173	7
values[8]	741	1			T10	23		T48	38		T55	1
values[9]	1089	1			T8	1		T11	25		T12	11
minimum	17666	1			T2	20		T6	190		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	804	1			T13	21		T42	1		T139	1
values[1]	2702	1			T5	7		T9	12		T55	1
values[2]	574	1			T35	1		T132	12		T140	39
values[3]	730	1			T8	1		T11	13		T12	12
values[4]	757	1			T13	22		T53	13		T150	1
values[5]	693	1			T3	1		T12	6		T34	22
values[6]	827	1			T1	22		T55	1		T173	7
values[7]	692	1			T10	23		T48	38		T39	4
values[8]	929	1			T8	2		T11	25		T150	1
values[9]	189	1			T12	11		T44	2		T244	1
minimum	17814	1			T2	20		T6	190		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

4093

1

T1

11

T5

6

T9

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T139	1		T131	16		T134	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	11		T42	1		T66	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T5	7		T9	12		T170	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	1		T136	14		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T35	1		T140	12		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T132	1		T140	8		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	11		T12	12		T154	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	1		T13	13		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	13		T53	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T150	1		T215	19		T136	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T34	12		T133	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	6		T43	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	12		T55	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T163	1		T229	12		T247	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	12		T39	4		T65	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	13		T48	3		T46	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	2		T11	17		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T150	1		T35	1		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T44	1		T24	10		T155	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T12	11		T244	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17578	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T219	9		T314	19		T253	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	11		T66	3		T228	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	10		T66	6		T144	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T225	9		T133	11		T226	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T136	10		T144	5		T257	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T140	11		T167	12		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T132	11		T140	8		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	2		T154	12		T220	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	8		T65	5		T137	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	9		T53	10		T217	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T136	12		T168	14		T251	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	10		T133	4		T251	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	5		T133	15		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	10		T173	6		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T229	11		T206	14		T285	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	12		T65	15		T240	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	10		T48	11		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	8		T47	2		T224	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T35	10		T246	6		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T44	1		T155	17		T308	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T30	8		T237	15		T241	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	1		T46	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T253	1		T33	7		T312	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T8	1		T44	1		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T246	9		T30	1		T252	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T312	14		T313	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T139	1		T131	16		T66	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T66	9		T135	5		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T5	7		T9	12		T170	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	11		T42	1		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T35	1		T142	1		T138	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T55	1		T132	1		T140	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	11		T12	12		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	1		T13	13		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	13		T53	3		T217	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T150	1		T215	19		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	12		T139	1		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	6		T43	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	12		T3	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T163	1		T167	1		T247	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	12		T55	1		T215	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	13		T48	3		T46	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T8	1		T11	17		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	11		T150	1		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T44	1		T155	17		T233	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T246	6		T30	8		T252	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T312	2		T313	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	11		T66	3		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T66	6		T227	11		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T225	9		T133	11		T226	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	10		T136	10		T144	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T167	12		T243	2		T130	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T132	11		T140	8		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	2		T140	11		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	8		T65	5		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	9		T53	10		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T136	12		T137	10		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T34	10		T133	4		T218	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T132	5		T133	15		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	10		T173	6		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T167	11		T206	14		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T48	12		T305	11		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	10		T48	11		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	8		T65	15		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T35	10		T220	3		T57	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T46	1		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T139	1		T131	12		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	11		T42	1		T66	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T5	1		T9	1		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	1		T136	11		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T35	1		T140	12		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T132	12		T140	9		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	3		T12	1		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	1		T13	9		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	10		T53	11		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T150	1		T215	1		T136	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T34	11		T133	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T43	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T1	11		T55	1		T173	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T163	1		T229	12		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	13		T39	4		T65	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	11		T48	12		T46	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	2		T11	9		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T150	1		T35	11		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T44	2		T24	1		T155	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T12	1		T244	1		T30	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17693	1			T2	20		T6	190		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T219	1		T314	1		T253	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T131	15		T134	21		T66	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	10		T66	8		T135	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T5	6		T9	11		T170	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T136	13		T144	13		T257	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T140	11		T138	7		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T140	7		T24	5		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	10		T12	11		T154	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	12		T65	2		T137	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	12		T53	2		T217	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T215	18		T136	12		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	11		T133	4		T134	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	5		T133	15		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	11		T215	7		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T229	11		T247	12		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	11		T65	12		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	12		T48	2		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	16		T224	6		T221	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T246	8		T267	3		T57	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T24	9		T155	13		T306	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T12	10		T241	12		T315	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T309	12		T213	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T219	8		T314	18		T253	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T8	1		T44	2		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T246	7		T30	9		T252	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T312	3		T313	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T139	1		T131	12		T66	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T66	7		T135	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T5	1		T9	1		T170	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	11		T42	1		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	1		T142	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T55	1		T132	12		T140	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	3		T12	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T13	9		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	10		T53	11		T217	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T150	1		T215	1		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	11		T139	1		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	1		T43	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	11		T3	1		T173	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T163	1		T167	12		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	13		T55	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T10	11		T48	12		T46	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T8	1		T11	9		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	1		T150	1		T35	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T6	190		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T155	13		T233	6		T157	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T246	8		T234	1		T316	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T312	13		T313	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	15		T66	2		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T66	8		T135	4		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T5	6		T9	11		T170	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	10		T136	13		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T138	7		T145	6		T221	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T140	7		T24	5		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	10		T12	11		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	12		T65	2		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	12		T53	2		T217	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T215	18		T136	12		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T34	11		T133	4		T134	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	5		T133	15		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	11		T215	7		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T247	12		T52	1		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	11		T215	9		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	12		T48	2		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T11	16		T65	12		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	10		T220	1		T267	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22618

1

T1

11

T2

20

T3

1

auto[1]

auto[0]

4093

1

T1

11

T5

6

T9

11