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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.17


Total test records in report: 918
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T303 /workspace/coverage/default/5.adc_ctrl_clock_gating.574877886 Jul 01 05:28:03 PM PDT 24 Jul 01 05:31:56 PM PDT 24 350085309108 ps
T799 /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1609578609 Jul 01 05:27:39 PM PDT 24 Jul 01 05:33:07 PM PDT 24 412689621513 ps
T800 /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.944478347 Jul 01 05:28:10 PM PDT 24 Jul 01 05:40:34 PM PDT 24 328727854517 ps
T70 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.817440103 Jul 01 04:31:34 PM PDT 24 Jul 01 04:31:47 PM PDT 24 533414574 ps
T62 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.217256533 Jul 01 04:31:49 PM PDT 24 Jul 01 04:32:03 PM PDT 24 4580772824 ps
T801 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4198010985 Jul 01 04:31:46 PM PDT 24 Jul 01 04:31:59 PM PDT 24 442335376 ps
T106 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2389780607 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:42 PM PDT 24 1045030352 ps
T71 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3252262126 Jul 01 04:31:53 PM PDT 24 Jul 01 04:32:04 PM PDT 24 607936443 ps
T802 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1662373170 Jul 01 04:31:40 PM PDT 24 Jul 01 04:31:53 PM PDT 24 502628403 ps
T72 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1956545329 Jul 01 04:31:29 PM PDT 24 Jul 01 04:31:42 PM PDT 24 489572094 ps
T803 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.214673825 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:38 PM PDT 24 470363420 ps
T63 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.940145743 Jul 01 04:31:27 PM PDT 24 Jul 01 04:32:08 PM PDT 24 26027041527 ps
T67 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.383751598 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:55 PM PDT 24 4056310038 ps
T804 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2643614213 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:49 PM PDT 24 398666915 ps
T805 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1003533723 Jul 01 04:31:37 PM PDT 24 Jul 01 04:31:50 PM PDT 24 422243756 ps
T122 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2573422291 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:40 PM PDT 24 1900263601 ps
T64 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1168198820 Jul 01 04:31:44 PM PDT 24 Jul 01 04:32:11 PM PDT 24 4589597132 ps
T76 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3609278549 Jul 01 04:31:38 PM PDT 24 Jul 01 04:31:52 PM PDT 24 361298636 ps
T68 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3996758546 Jul 01 04:31:31 PM PDT 24 Jul 01 04:32:06 PM PDT 24 8656497985 ps
T806 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.594926812 Jul 01 04:31:38 PM PDT 24 Jul 01 04:31:50 PM PDT 24 491085762 ps
T84 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1257502632 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:43 PM PDT 24 530283937 ps
T807 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3151558446 Jul 01 04:31:17 PM PDT 24 Jul 01 04:31:29 PM PDT 24 411771550 ps
T808 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.297656289 Jul 01 04:31:59 PM PDT 24 Jul 01 04:32:10 PM PDT 24 463813302 ps
T81 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2893989381 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:44 PM PDT 24 416089904 ps
T809 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1335969229 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:49 PM PDT 24 410718623 ps
T810 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.250271954 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:37 PM PDT 24 379026979 ps
T77 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.490442064 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:46 PM PDT 24 365833886 ps
T811 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4152788730 Jul 01 04:31:48 PM PDT 24 Jul 01 04:31:59 PM PDT 24 346084637 ps
T123 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3005187934 Jul 01 04:31:26 PM PDT 24 Jul 01 04:31:43 PM PDT 24 2372004966 ps
T69 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3109994793 Jul 01 04:31:45 PM PDT 24 Jul 01 04:32:00 PM PDT 24 4656509208 ps
T128 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3185669161 Jul 01 04:31:29 PM PDT 24 Jul 01 04:31:43 PM PDT 24 1130889704 ps
T812 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3933532425 Jul 01 04:31:37 PM PDT 24 Jul 01 04:31:49 PM PDT 24 599788011 ps
T95 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2401018792 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:45 PM PDT 24 553065481 ps
T813 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1436022302 Jul 01 04:31:41 PM PDT 24 Jul 01 04:31:54 PM PDT 24 374064522 ps
T814 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2406374199 Jul 01 04:31:36 PM PDT 24 Jul 01 04:31:49 PM PDT 24 370326325 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3811534116 Jul 01 04:31:25 PM PDT 24 Jul 01 04:32:36 PM PDT 24 26274959845 ps
T78 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1557476846 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:39 PM PDT 24 617463289 ps
T124 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.672657782 Jul 01 04:31:52 PM PDT 24 Jul 01 04:32:13 PM PDT 24 3953520301 ps
T340 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1590841167 Jul 01 04:31:34 PM PDT 24 Jul 01 04:31:57 PM PDT 24 4624567218 ps
T125 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3766413136 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:41 PM PDT 24 2203520614 ps
T815 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2407392910 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:48 PM PDT 24 515940408 ps
T816 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4113942077 Jul 01 04:31:27 PM PDT 24 Jul 01 04:31:39 PM PDT 24 426695930 ps
T817 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1730401018 Jul 01 04:31:27 PM PDT 24 Jul 01 04:31:47 PM PDT 24 864560562 ps
T818 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1182070123 Jul 01 04:31:29 PM PDT 24 Jul 01 04:32:03 PM PDT 24 8286627099 ps
T82 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.708101841 Jul 01 04:31:26 PM PDT 24 Jul 01 04:31:49 PM PDT 24 4230422312 ps
T80 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1060762394 Jul 01 04:31:30 PM PDT 24 Jul 01 04:31:44 PM PDT 24 519946720 ps
T83 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.64267562 Jul 01 04:31:47 PM PDT 24 Jul 01 04:32:00 PM PDT 24 767998428 ps
T819 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2413322270 Jul 01 04:31:26 PM PDT 24 Jul 01 04:31:40 PM PDT 24 411337310 ps
T820 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3077039125 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:39 PM PDT 24 488851934 ps
T821 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3932802069 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:46 PM PDT 24 549570375 ps
T822 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3398521226 Jul 01 04:31:38 PM PDT 24 Jul 01 04:31:50 PM PDT 24 325606635 ps
T823 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2984525374 Jul 01 04:31:40 PM PDT 24 Jul 01 04:31:55 PM PDT 24 4858373402 ps
T107 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.511557225 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:39 PM PDT 24 483114665 ps
T824 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3906925541 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:44 PM PDT 24 632807832 ps
T825 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.105280762 Jul 01 04:31:37 PM PDT 24 Jul 01 04:31:50 PM PDT 24 420307427 ps
T826 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3429925059 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:47 PM PDT 24 462275196 ps
T126 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.735902639 Jul 01 04:31:46 PM PDT 24 Jul 01 04:31:58 PM PDT 24 486597761 ps
T108 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.517362602 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:46 PM PDT 24 592383305 ps
T827 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.953651984 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:44 PM PDT 24 465756681 ps
T828 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1568740050 Jul 01 04:31:43 PM PDT 24 Jul 01 04:31:55 PM PDT 24 466391606 ps
T829 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.213771934 Jul 01 04:31:47 PM PDT 24 Jul 01 04:31:59 PM PDT 24 468812549 ps
T830 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3246554892 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:40 PM PDT 24 1031179232 ps
T831 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1896627468 Jul 01 04:31:40 PM PDT 24 Jul 01 04:31:52 PM PDT 24 333442982 ps
T127 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2644873185 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:46 PM PDT 24 387082022 ps
T832 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.407762433 Jul 01 04:31:39 PM PDT 24 Jul 01 04:31:52 PM PDT 24 332425613 ps
T833 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3895284594 Jul 01 04:31:54 PM PDT 24 Jul 01 04:32:10 PM PDT 24 9601818269 ps
T341 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3283552930 Jul 01 04:31:40 PM PDT 24 Jul 01 04:31:58 PM PDT 24 4428567179 ps
T834 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2231958440 Jul 01 04:31:41 PM PDT 24 Jul 01 04:31:53 PM PDT 24 468497807 ps
T835 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3628482592 Jul 01 04:31:16 PM PDT 24 Jul 01 04:31:30 PM PDT 24 1635508045 ps
T109 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2024018482 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:48 PM PDT 24 437118455 ps
T836 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1207598135 Jul 01 04:31:46 PM PDT 24 Jul 01 04:31:58 PM PDT 24 357284431 ps
T837 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.129037641 Jul 01 04:31:34 PM PDT 24 Jul 01 04:31:47 PM PDT 24 641866832 ps
T838 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4025950805 Jul 01 04:31:41 PM PDT 24 Jul 01 04:31:53 PM PDT 24 343965935 ps
T839 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1891192299 Jul 01 04:31:48 PM PDT 24 Jul 01 04:32:00 PM PDT 24 363331578 ps
T840 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.603182289 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:40 PM PDT 24 386095186 ps
T338 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1168732487 Jul 01 04:31:34 PM PDT 24 Jul 01 04:31:53 PM PDT 24 4803685529 ps
T841 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1811643471 Jul 01 04:31:37 PM PDT 24 Jul 01 04:31:50 PM PDT 24 431913846 ps
T115 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.376167326 Jul 01 04:31:16 PM PDT 24 Jul 01 04:31:29 PM PDT 24 481442463 ps
T842 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.698594891 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:45 PM PDT 24 474369311 ps
T843 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1164655550 Jul 01 04:31:36 PM PDT 24 Jul 01 04:31:49 PM PDT 24 337509645 ps
T110 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4156756003 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:44 PM PDT 24 335243882 ps
T111 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3214766073 Jul 01 04:31:43 PM PDT 24 Jul 01 04:31:56 PM PDT 24 391010969 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1411179377 Jul 01 04:31:22 PM PDT 24 Jul 01 04:31:34 PM PDT 24 371036683 ps
T845 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.828632059 Jul 01 04:31:49 PM PDT 24 Jul 01 04:32:01 PM PDT 24 638537366 ps
T846 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.224994175 Jul 01 04:31:54 PM PDT 24 Jul 01 04:32:05 PM PDT 24 363101601 ps
T847 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3457012665 Jul 01 04:31:16 PM PDT 24 Jul 01 04:31:39 PM PDT 24 8943534567 ps
T848 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.660150579 Jul 01 04:31:48 PM PDT 24 Jul 01 04:32:01 PM PDT 24 551904442 ps
T849 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.279019967 Jul 01 04:31:38 PM PDT 24 Jul 01 04:31:50 PM PDT 24 449841393 ps
T850 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1773181249 Jul 01 04:31:48 PM PDT 24 Jul 01 04:32:00 PM PDT 24 385917768 ps
T851 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1316017762 Jul 01 04:31:26 PM PDT 24 Jul 01 04:31:38 PM PDT 24 572063516 ps
T112 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2914810778 Jul 01 04:31:46 PM PDT 24 Jul 01 04:31:59 PM PDT 24 352412063 ps
T852 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2541651588 Jul 01 04:31:38 PM PDT 24 Jul 01 04:31:52 PM PDT 24 655327434 ps
T116 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3476482879 Jul 01 04:31:37 PM PDT 24 Jul 01 04:31:50 PM PDT 24 348733870 ps
T113 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3856652623 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:41 PM PDT 24 778412046 ps
T853 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1587583595 Jul 01 04:31:33 PM PDT 24 Jul 01 04:32:03 PM PDT 24 4071934737 ps
T854 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3176579166 Jul 01 04:31:30 PM PDT 24 Jul 01 04:31:53 PM PDT 24 4598195962 ps
T855 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1510640496 Jul 01 04:31:26 PM PDT 24 Jul 01 04:31:42 PM PDT 24 4655464467 ps
T342 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3048132056 Jul 01 04:31:48 PM PDT 24 Jul 01 04:32:20 PM PDT 24 8382881475 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2436885103 Jul 01 04:31:47 PM PDT 24 Jul 01 04:32:00 PM PDT 24 596696970 ps
T857 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1746551294 Jul 01 04:31:46 PM PDT 24 Jul 01 04:31:59 PM PDT 24 467559710 ps
T858 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4218857449 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:44 PM PDT 24 1061878404 ps
T859 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2734632146 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:55 PM PDT 24 4685898942 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2965347095 Jul 01 04:31:22 PM PDT 24 Jul 01 04:31:35 PM PDT 24 359326113 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1659556493 Jul 01 04:31:25 PM PDT 24 Jul 01 04:32:01 PM PDT 24 26128420956 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2159960417 Jul 01 04:31:23 PM PDT 24 Jul 01 04:31:36 PM PDT 24 403746561 ps
T118 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.872586665 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:38 PM PDT 24 468478036 ps
T861 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3055059173 Jul 01 04:31:44 PM PDT 24 Jul 01 04:31:56 PM PDT 24 383860759 ps
T862 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1613406781 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:49 PM PDT 24 320571623 ps
T863 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1716504803 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:48 PM PDT 24 1233415114 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2637728591 Jul 01 04:31:50 PM PDT 24 Jul 01 04:32:09 PM PDT 24 2334162151 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3547638855 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:28 PM PDT 24 384124151 ps
T866 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1251536474 Jul 01 04:31:42 PM PDT 24 Jul 01 04:31:54 PM PDT 24 331219785 ps
T867 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3342312974 Jul 01 04:31:45 PM PDT 24 Jul 01 04:31:57 PM PDT 24 383381222 ps
T868 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2325061641 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:43 PM PDT 24 428163355 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1810691666 Jul 01 04:31:30 PM PDT 24 Jul 01 04:32:53 PM PDT 24 22390357829 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3928721690 Jul 01 04:31:17 PM PDT 24 Jul 01 04:33:05 PM PDT 24 26164896921 ps
T339 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1739320461 Jul 01 04:31:38 PM PDT 24 Jul 01 04:31:59 PM PDT 24 8309528306 ps
T870 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.279502694 Jul 01 04:31:47 PM PDT 24 Jul 01 04:32:00 PM PDT 24 489892840 ps
T871 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3308750173 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:48 PM PDT 24 400825020 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1349839891 Jul 01 04:31:49 PM PDT 24 Jul 01 04:32:04 PM PDT 24 552978112 ps
T873 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1294214734 Jul 01 04:31:53 PM PDT 24 Jul 01 04:32:08 PM PDT 24 627987976 ps
T874 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.672574867 Jul 01 04:31:26 PM PDT 24 Jul 01 04:31:39 PM PDT 24 363287363 ps
T875 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1180588428 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:47 PM PDT 24 7708597413 ps
T876 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4202434785 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:43 PM PDT 24 471090722 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1816521068 Jul 01 04:31:34 PM PDT 24 Jul 01 04:31:49 PM PDT 24 4421668747 ps
T878 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2912484240 Jul 01 04:31:49 PM PDT 24 Jul 01 04:32:03 PM PDT 24 2153034877 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.122735322 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:45 PM PDT 24 557208794 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1045248585 Jul 01 04:31:45 PM PDT 24 Jul 01 04:31:59 PM PDT 24 960770607 ps
T881 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4122893488 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:48 PM PDT 24 492800524 ps
T882 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1925729212 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:41 PM PDT 24 4261161349 ps
T883 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2151712250 Jul 01 04:31:40 PM PDT 24 Jul 01 04:31:55 PM PDT 24 4485626881 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3203895344 Jul 01 04:31:30 PM PDT 24 Jul 01 04:31:43 PM PDT 24 476807162 ps
T885 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.601147094 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:53 PM PDT 24 8985024769 ps
T886 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1125633677 Jul 01 04:31:29 PM PDT 24 Jul 01 04:31:41 PM PDT 24 632654241 ps
T887 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1865906946 Jul 01 04:31:30 PM PDT 24 Jul 01 04:31:44 PM PDT 24 1263365584 ps
T888 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2617452994 Jul 01 04:31:30 PM PDT 24 Jul 01 04:31:52 PM PDT 24 7944191559 ps
T889 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3313509210 Jul 01 04:31:59 PM PDT 24 Jul 01 04:32:15 PM PDT 24 5169395091 ps
T890 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1812554864 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:46 PM PDT 24 679396798 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1058769855 Jul 01 04:31:23 PM PDT 24 Jul 01 04:31:37 PM PDT 24 5350119329 ps
T892 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2747057781 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:45 PM PDT 24 2644441818 ps
T893 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3303543175 Jul 01 04:31:30 PM PDT 24 Jul 01 04:31:46 PM PDT 24 4264030955 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.665486380 Jul 01 04:31:36 PM PDT 24 Jul 01 04:31:49 PM PDT 24 486669856 ps
T895 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1815815117 Jul 01 04:31:32 PM PDT 24 Jul 01 04:31:47 PM PDT 24 4372228475 ps
T120 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2507002959 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:40 PM PDT 24 905536035 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1686471634 Jul 01 04:31:15 PM PDT 24 Jul 01 04:31:28 PM PDT 24 280326179 ps
T897 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.453555487 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:42 PM PDT 24 560372303 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.221142580 Jul 01 04:31:19 PM PDT 24 Jul 01 04:31:33 PM PDT 24 5186320980 ps
T899 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2771145347 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:46 PM PDT 24 468984869 ps
T900 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3509670008 Jul 01 04:31:17 PM PDT 24 Jul 01 04:31:28 PM PDT 24 372480867 ps
T901 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3805739838 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:54 PM PDT 24 3754178528 ps
T902 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2411395197 Jul 01 04:31:52 PM PDT 24 Jul 01 04:32:10 PM PDT 24 8198985543 ps
T903 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1244011412 Jul 01 04:31:48 PM PDT 24 Jul 01 04:32:05 PM PDT 24 560744430 ps
T904 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.717366216 Jul 01 04:31:25 PM PDT 24 Jul 01 04:31:38 PM PDT 24 468891819 ps
T905 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.254896169 Jul 01 04:31:49 PM PDT 24 Jul 01 04:32:02 PM PDT 24 392883030 ps
T906 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3689805361 Jul 01 04:31:28 PM PDT 24 Jul 01 04:31:42 PM PDT 24 543630576 ps
T907 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1229388142 Jul 01 04:31:45 PM PDT 24 Jul 01 04:31:57 PM PDT 24 287711646 ps
T908 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1174318 Jul 01 04:31:35 PM PDT 24 Jul 01 04:31:49 PM PDT 24 588614198 ps
T909 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.651190930 Jul 01 04:31:52 PM PDT 24 Jul 01 04:32:06 PM PDT 24 367370396 ps
T910 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1566924144 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:45 PM PDT 24 345159558 ps
T911 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.236092198 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:43 PM PDT 24 375178356 ps
T912 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3027696162 Jul 01 04:31:31 PM PDT 24 Jul 01 04:31:43 PM PDT 24 487842246 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1619580896 Jul 01 04:31:24 PM PDT 24 Jul 01 04:31:36 PM PDT 24 406552417 ps
T121 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3136724919 Jul 01 04:31:24 PM PDT 24 Jul 01 04:31:37 PM PDT 24 938678278 ps
T914 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3632236532 Jul 01 04:31:37 PM PDT 24 Jul 01 04:31:50 PM PDT 24 497431002 ps
T915 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2275134644 Jul 01 04:31:36 PM PDT 24 Jul 01 04:31:54 PM PDT 24 338401907 ps
T916 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.446152466 Jul 01 04:31:43 PM PDT 24 Jul 01 04:31:55 PM PDT 24 377825308 ps
T917 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2912488687 Jul 01 04:31:33 PM PDT 24 Jul 01 04:31:47 PM PDT 24 589070392 ps
T918 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1476821383 Jul 01 04:31:52 PM PDT 24 Jul 01 04:32:04 PM PDT 24 368812604 ps

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2442744180
Short name T10
Test name
Test status
Simulation time 204354371379 ps
CPU time 432.06 seconds
Started Jul 01 05:32:22 PM PDT 24
Finished Jul 01 05:39:35 PM PDT 24
Peak memory 202032 kb
Host smart-5900ae52-8f62-4c8c-8ac0-25298fa07959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442744180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2442744180
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4046875914
Short name T40
Test name
Test status
Simulation time 125344651248 ps
CPU time 421.21 seconds
Started Jul 01 05:30:14 PM PDT 24
Finished Jul 01 05:37:16 PM PDT 24
Peak memory 202192 kb
Host smart-2aa951b7-35da-484e-a453-5c0887cd00b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046875914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4046875914
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3504469071
Short name T13
Test name
Test status
Simulation time 506929775071 ps
CPU time 1157.71 seconds
Started Jul 01 05:30:45 PM PDT 24
Finished Jul 01 05:50:04 PM PDT 24
Peak memory 201860 kb
Host smart-e1d39c4b-ed0d-402c-b75c-1938be0071cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504469071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3504469071
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1761488951
Short name T140
Test name
Test status
Simulation time 502569216306 ps
CPU time 291.54 seconds
Started Jul 01 05:32:15 PM PDT 24
Finished Jul 01 05:37:08 PM PDT 24
Peak memory 201960 kb
Host smart-2bac3db7-5f0a-4390-a68f-3db0f6340987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761488951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1761488951
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.705276889
Short name T52
Test name
Test status
Simulation time 145036404167 ps
CPU time 114.56 seconds
Started Jul 01 05:33:30 PM PDT 24
Finished Jul 01 05:35:25 PM PDT 24
Peak memory 210328 kb
Host smart-d61d2201-4a60-4268-b2b6-889b67df3dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705276889 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.705276889
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1981992252
Short name T133
Test name
Test status
Simulation time 510163430816 ps
CPU time 1228.12 seconds
Started Jul 01 05:30:45 PM PDT 24
Finished Jul 01 05:51:15 PM PDT 24
Peak memory 201884 kb
Host smart-f31c2eb8-ad33-434e-b305-b70186066936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981992252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1981992252
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2532897720
Short name T220
Test name
Test status
Simulation time 552078594574 ps
CPU time 214.09 seconds
Started Jul 01 05:28:36 PM PDT 24
Finished Jul 01 05:32:11 PM PDT 24
Peak memory 201880 kb
Host smart-8de30c86-718d-479a-b992-c8441c83f523
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532897720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2532897720
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.352272534
Short name T16
Test name
Test status
Simulation time 282850012262 ps
CPU time 75.17 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:29:12 PM PDT 24
Peak memory 210264 kb
Host smart-449dd7f6-0df7-41c0-987b-104a0f3d08de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352272534 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.352272534
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2498531782
Short name T130
Test name
Test status
Simulation time 619709071754 ps
CPU time 785.12 seconds
Started Jul 01 05:32:58 PM PDT 24
Finished Jul 01 05:46:04 PM PDT 24
Peak memory 210596 kb
Host smart-245a1f1d-50ff-4e93-ba2c-ed6ebbff6f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498531782 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2498531782
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2240118033
Short name T11
Test name
Test status
Simulation time 339138425822 ps
CPU time 212.44 seconds
Started Jul 01 05:31:40 PM PDT 24
Finished Jul 01 05:35:14 PM PDT 24
Peak memory 201860 kb
Host smart-23bd0224-75a1-4fe7-8cfa-0787906f08fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240118033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2240118033
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.483970501
Short name T215
Test name
Test status
Simulation time 607609268721 ps
CPU time 1358.26 seconds
Started Jul 01 05:27:55 PM PDT 24
Finished Jul 01 05:50:34 PM PDT 24
Peak memory 201904 kb
Host smart-79afe632-2efa-4c5c-ab8e-8a5b880863e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483970501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.483970501
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1956545329
Short name T72
Test name
Test status
Simulation time 489572094 ps
CPU time 2.56 seconds
Started Jul 01 04:31:29 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 201804 kb
Host smart-4ad0382c-7c8f-45df-89a7-e7e76b43b82d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956545329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1956545329
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3393502051
Short name T163
Test name
Test status
Simulation time 493934793811 ps
CPU time 286.48 seconds
Started Jul 01 05:28:56 PM PDT 24
Finished Jul 01 05:33:44 PM PDT 24
Peak memory 201884 kb
Host smart-709f5f8b-751d-400a-bc6f-eec935647daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393502051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3393502051
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.819081821
Short name T137
Test name
Test status
Simulation time 372431251369 ps
CPU time 399.62 seconds
Started Jul 01 05:33:39 PM PDT 24
Finished Jul 01 05:40:20 PM PDT 24
Peak memory 201944 kb
Host smart-a133c4ac-c2c3-4ba8-9c21-e8c409d34c41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819081821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.819081821
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.583465086
Short name T155
Test name
Test status
Simulation time 361459419527 ps
CPU time 58.2 seconds
Started Jul 01 05:32:02 PM PDT 24
Finished Jul 01 05:33:01 PM PDT 24
Peak memory 201896 kb
Host smart-a5c0537e-eb17-4e9f-945f-70857132bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583465086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.583465086
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.276074886
Short name T144
Test name
Test status
Simulation time 496397718616 ps
CPU time 268.68 seconds
Started Jul 01 05:33:14 PM PDT 24
Finished Jul 01 05:37:44 PM PDT 24
Peak memory 201964 kb
Host smart-702de283-e39e-46f0-ac49-b70c4e1175ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276074886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.276074886
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1329654969
Short name T370
Test name
Test status
Simulation time 330263761 ps
CPU time 0.8 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:28:28 PM PDT 24
Peak memory 201624 kb
Host smart-79dd9771-c2e2-4b79-ab04-a248a06ea2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329654969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1329654969
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.940145743
Short name T63
Test name
Test status
Simulation time 26027041527 ps
CPU time 30.25 seconds
Started Jul 01 04:31:27 PM PDT 24
Finished Jul 01 04:32:08 PM PDT 24
Peak memory 201968 kb
Host smart-d7dfc361-3e2c-4bf1-acd8-2f8ae7ab6c13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940145743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.940145743
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2162430980
Short name T285
Test name
Test status
Simulation time 537162592108 ps
CPU time 642.25 seconds
Started Jul 01 05:28:13 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 202016 kb
Host smart-5c68fede-45fe-444d-9e90-776c041ab578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162430980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2162430980
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3049603278
Short name T73
Test name
Test status
Simulation time 7978260197 ps
CPU time 10.49 seconds
Started Jul 01 05:27:43 PM PDT 24
Finished Jul 01 05:27:55 PM PDT 24
Peak memory 218248 kb
Host smart-963f9a08-9d9b-489a-91b7-710be1aaf097
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049603278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3049603278
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.32049814
Short name T48
Test name
Test status
Simulation time 327893481470 ps
CPU time 118.35 seconds
Started Jul 01 05:31:24 PM PDT 24
Finished Jul 01 05:33:23 PM PDT 24
Peak memory 201892 kb
Host smart-45cfc5b5-f38a-42c0-93c8-03c944cbcea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32049814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.32049814
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.792921111
Short name T216
Test name
Test status
Simulation time 485801660065 ps
CPU time 311.16 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 201896 kb
Host smart-e266cba6-a2ad-47df-a498-2457f1602f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792921111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.792921111
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.670008252
Short name T12
Test name
Test status
Simulation time 512150421051 ps
CPU time 1100.34 seconds
Started Jul 01 05:31:24 PM PDT 24
Finished Jul 01 05:49:46 PM PDT 24
Peak memory 201964 kb
Host smart-d62d98a5-d0a9-4ed4-b2c1-bd122be47fe7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670008252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.670008252
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.641121324
Short name T309
Test name
Test status
Simulation time 327404450220 ps
CPU time 776.37 seconds
Started Jul 01 05:28:34 PM PDT 24
Finished Jul 01 05:41:32 PM PDT 24
Peak memory 201928 kb
Host smart-e96441c5-0e47-479a-9485-4a412a9261d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641121324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.641121324
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.833304219
Short name T200
Test name
Test status
Simulation time 1328090998092 ps
CPU time 1002.37 seconds
Started Jul 01 05:33:57 PM PDT 24
Finished Jul 01 05:50:40 PM PDT 24
Peak memory 210580 kb
Host smart-72b012c6-af9b-4b47-aeee-79c2f6adf251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833304219 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.833304219
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3085985746
Short name T229
Test name
Test status
Simulation time 509564835700 ps
CPU time 583.19 seconds
Started Jul 01 05:33:14 PM PDT 24
Finished Jul 01 05:42:59 PM PDT 24
Peak memory 201976 kb
Host smart-657e1995-d562-4cd0-ba2a-1b66e54f22bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085985746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3085985746
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4155083461
Short name T198
Test name
Test status
Simulation time 533298542358 ps
CPU time 252.64 seconds
Started Jul 01 05:28:42 PM PDT 24
Finished Jul 01 05:32:56 PM PDT 24
Peak memory 201900 kb
Host smart-110a3fc9-e8af-4f90-94d9-3da72838a6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155083461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4155083461
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2276572474
Short name T225
Test name
Test status
Simulation time 162079027958 ps
CPU time 189.46 seconds
Started Jul 01 05:32:09 PM PDT 24
Finished Jul 01 05:35:20 PM PDT 24
Peak memory 201920 kb
Host smart-66e3cf05-29a9-4cbc-9633-aeda9963166d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276572474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2276572474
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1792740903
Short name T53
Test name
Test status
Simulation time 157032524872 ps
CPU time 33.16 seconds
Started Jul 01 05:33:22 PM PDT 24
Finished Jul 01 05:33:56 PM PDT 24
Peak memory 201868 kb
Host smart-b7e97499-86ff-49b0-8365-6b7088c5a9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792740903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1792740903
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3554591972
Short name T66
Test name
Test status
Simulation time 330716663363 ps
CPU time 586.67 seconds
Started Jul 01 05:27:48 PM PDT 24
Finished Jul 01 05:37:36 PM PDT 24
Peak memory 201880 kb
Host smart-66bc2086-786a-435d-8762-91813c09df39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554591972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3554591972
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2742578454
Short name T258
Test name
Test status
Simulation time 529008596491 ps
CPU time 115.94 seconds
Started Jul 01 05:28:06 PM PDT 24
Finished Jul 01 05:30:03 PM PDT 24
Peak memory 201940 kb
Host smart-0a57f37d-2fd7-4a7e-b626-706803878efe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742578454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2742578454
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3283552930
Short name T341
Test name
Test status
Simulation time 4428567179 ps
CPU time 5.84 seconds
Started Jul 01 04:31:40 PM PDT 24
Finished Jul 01 04:31:58 PM PDT 24
Peak memory 201700 kb
Host smart-8e1034b0-aa9d-44fe-83ac-6705e0ae9a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283552930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3283552930
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2220096525
Short name T293
Test name
Test status
Simulation time 492943013210 ps
CPU time 288.14 seconds
Started Jul 01 05:27:42 PM PDT 24
Finished Jul 01 05:32:31 PM PDT 24
Peak memory 201948 kb
Host smart-fe3f27f8-d531-48b2-bda6-955a90391efd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220096525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2220096525
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3614192958
Short name T101
Test name
Test status
Simulation time 458676627023 ps
CPU time 1214.79 seconds
Started Jul 01 05:28:27 PM PDT 24
Finished Jul 01 05:48:43 PM PDT 24
Peak memory 218616 kb
Host smart-314c17d8-f9f6-4c9b-88cd-2bb8d59b0e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614192958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3614192958
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2154388198
Short name T88
Test name
Test status
Simulation time 250983758967 ps
CPU time 542.9 seconds
Started Jul 01 05:34:26 PM PDT 24
Finished Jul 01 05:43:30 PM PDT 24
Peak memory 201892 kb
Host smart-4f8592ce-aa8d-4ebb-854d-848890c00992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154388198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2154388198
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3273414651
Short name T312
Test name
Test status
Simulation time 327251199613 ps
CPU time 380.4 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:34:48 PM PDT 24
Peak memory 201888 kb
Host smart-1d0581ae-67c1-49df-9f95-51b941b58a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273414651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3273414651
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2714452305
Short name T49
Test name
Test status
Simulation time 43782567471 ps
CPU time 98.6 seconds
Started Jul 01 05:32:22 PM PDT 24
Finished Jul 01 05:34:01 PM PDT 24
Peak memory 210768 kb
Host smart-b64ffa22-a5ad-44a6-8a9f-c4d1e14500e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714452305 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2714452305
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1210355062
Short name T316
Test name
Test status
Simulation time 95856435032 ps
CPU time 51.89 seconds
Started Jul 01 05:30:20 PM PDT 24
Finished Jul 01 05:31:12 PM PDT 24
Peak memory 210596 kb
Host smart-599f4734-b641-4002-8070-6bfcc63f8da0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210355062 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1210355062
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.124031835
Short name T98
Test name
Test status
Simulation time 489342033065 ps
CPU time 572.66 seconds
Started Jul 01 05:29:12 PM PDT 24
Finished Jul 01 05:38:45 PM PDT 24
Peak memory 201928 kb
Host smart-a5426c97-0aad-4515-9b04-47384907ea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124031835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.124031835
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2031725470
Short name T237
Test name
Test status
Simulation time 499390653528 ps
CPU time 1105.35 seconds
Started Jul 01 05:31:27 PM PDT 24
Finished Jul 01 05:49:53 PM PDT 24
Peak memory 201880 kb
Host smart-62e0dffb-ce16-4abc-9495-a8c5bb336af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031725470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2031725470
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2429210395
Short name T278
Test name
Test status
Simulation time 327783092413 ps
CPU time 201.32 seconds
Started Jul 01 05:28:43 PM PDT 24
Finished Jul 01 05:32:05 PM PDT 24
Peak memory 201916 kb
Host smart-b41b4fb9-3051-4b64-b2fc-587480d3f12b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429210395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2429210395
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2150808750
Short name T195
Test name
Test status
Simulation time 448700558938 ps
CPU time 1336.09 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:50:31 PM PDT 24
Peak memory 213156 kb
Host smart-02600ff2-3049-4ea6-88d8-6623c8d72c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150808750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2150808750
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3374789035
Short name T308
Test name
Test status
Simulation time 499143622549 ps
CPU time 776.89 seconds
Started Jul 01 05:27:42 PM PDT 24
Finished Jul 01 05:40:41 PM PDT 24
Peak memory 201956 kb
Host smart-588acfc5-f970-4360-b815-57c838d934b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374789035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3374789035
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3663443847
Short name T136
Test name
Test status
Simulation time 328255042997 ps
CPU time 406.07 seconds
Started Jul 01 05:29:37 PM PDT 24
Finished Jul 01 05:36:24 PM PDT 24
Peak memory 201968 kb
Host smart-df2a3f08-ced1-445e-a2c6-92d68adddfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663443847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3663443847
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1125325287
Short name T24
Test name
Test status
Simulation time 548478048484 ps
CPU time 575.52 seconds
Started Jul 01 05:31:12 PM PDT 24
Finished Jul 01 05:40:48 PM PDT 24
Peak memory 201952 kb
Host smart-b4a4d581-1c05-4697-a452-f664e34092b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125325287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1125325287
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3811184845
Short name T233
Test name
Test status
Simulation time 329420591492 ps
CPU time 53.83 seconds
Started Jul 01 05:34:24 PM PDT 24
Finished Jul 01 05:35:18 PM PDT 24
Peak memory 201948 kb
Host smart-e39e50c8-0df6-46de-be6a-5d59829238c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811184845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3811184845
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.217256533
Short name T62
Test name
Test status
Simulation time 4580772824 ps
CPU time 2.98 seconds
Started Jul 01 04:31:49 PM PDT 24
Finished Jul 01 04:32:03 PM PDT 24
Peak memory 201688 kb
Host smart-f97ac486-6215-436d-8e02-4bd93c65bbb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217256533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.217256533
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1822531748
Short name T262
Test name
Test status
Simulation time 509094316670 ps
CPU time 550.45 seconds
Started Jul 01 05:29:17 PM PDT 24
Finished Jul 01 05:38:28 PM PDT 24
Peak memory 201860 kb
Host smart-a17ca308-e2a4-4a80-9286-90ef92037f6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822531748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1822531748
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2220703014
Short name T244
Test name
Test status
Simulation time 334825088675 ps
CPU time 547.32 seconds
Started Jul 01 05:28:33 PM PDT 24
Finished Jul 01 05:37:41 PM PDT 24
Peak memory 201876 kb
Host smart-70059e48-77f5-4ca0-adad-898b373f1165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220703014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2220703014
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3220013546
Short name T250
Test name
Test status
Simulation time 503050162466 ps
CPU time 298.93 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:34:06 PM PDT 24
Peak memory 201904 kb
Host smart-1642d787-adfd-49df-a59d-a880021bced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220013546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3220013546
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1962844688
Short name T272
Test name
Test status
Simulation time 559757367165 ps
CPU time 677.06 seconds
Started Jul 01 05:31:12 PM PDT 24
Finished Jul 01 05:42:29 PM PDT 24
Peak memory 201860 kb
Host smart-5dd3e4c4-3ec5-41de-a924-6055a4c06257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962844688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1962844688
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3099933638
Short name T20
Test name
Test status
Simulation time 131299553669 ps
CPU time 69.39 seconds
Started Jul 01 05:34:05 PM PDT 24
Finished Jul 01 05:35:16 PM PDT 24
Peak memory 202004 kb
Host smart-b1311025-68f3-450f-bca5-5eb27f01706b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099933638 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3099933638
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1811643471
Short name T841
Test name
Test status
Simulation time 431913846 ps
CPU time 1.98 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201620 kb
Host smart-60cf1f78-7d4b-4f5f-9990-4d0031fb1be5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811643471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1811643471
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1285117748
Short name T164
Test name
Test status
Simulation time 198262250329 ps
CPU time 131.38 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:30:32 PM PDT 24
Peak memory 201948 kb
Host smart-a3029719-4670-4dbe-8d3d-f85f049f942f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285117748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1285117748
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3027429064
Short name T284
Test name
Test status
Simulation time 165025332114 ps
CPU time 195.05 seconds
Started Jul 01 05:28:44 PM PDT 24
Finished Jul 01 05:31:59 PM PDT 24
Peak memory 201896 kb
Host smart-cf6626d0-2310-4cf1-9086-1f500a4f67aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027429064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3027429064
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.89668729
Short name T47
Test name
Test status
Simulation time 42384834535 ps
CPU time 89.86 seconds
Started Jul 01 05:28:50 PM PDT 24
Finished Jul 01 05:30:21 PM PDT 24
Peak memory 202148 kb
Host smart-c844a8fe-6efb-4479-85a7-9a26b6432ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89668729 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.89668729
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4137384504
Short name T271
Test name
Test status
Simulation time 394317611211 ps
CPU time 220.33 seconds
Started Jul 01 05:32:40 PM PDT 24
Finished Jul 01 05:36:21 PM PDT 24
Peak memory 202116 kb
Host smart-81374ee8-4627-4650-a1f8-bdddbea0708f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137384504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4137384504
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2774874046
Short name T304
Test name
Test status
Simulation time 501759584731 ps
CPU time 591.19 seconds
Started Jul 01 05:33:18 PM PDT 24
Finished Jul 01 05:43:10 PM PDT 24
Peak memory 202008 kb
Host smart-b2d7a66b-e861-4104-bf71-5844c94c18cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774874046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2774874046
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.574877886
Short name T303
Test name
Test status
Simulation time 350085309108 ps
CPU time 232.13 seconds
Started Jul 01 05:28:03 PM PDT 24
Finished Jul 01 05:31:56 PM PDT 24
Peak memory 202052 kb
Host smart-630af4ed-7f75-4099-ba48-143d111b309e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574877886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.574877886
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.610985042
Short name T219
Test name
Test status
Simulation time 538581776084 ps
CPU time 665.22 seconds
Started Jul 01 05:29:54 PM PDT 24
Finished Jul 01 05:41:00 PM PDT 24
Peak memory 202020 kb
Host smart-9ab11e06-edea-4e42-80d1-81d53e6974e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610985042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.610985042
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3893833402
Short name T8
Test name
Test status
Simulation time 487714677939 ps
CPU time 540.85 seconds
Started Jul 01 05:29:52 PM PDT 24
Finished Jul 01 05:38:54 PM PDT 24
Peak memory 201988 kb
Host smart-063f168f-5998-48ce-b3b8-e8e87641fb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893833402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3893833402
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.960947441
Short name T286
Test name
Test status
Simulation time 493238795646 ps
CPU time 1056.95 seconds
Started Jul 01 05:30:50 PM PDT 24
Finished Jul 01 05:48:28 PM PDT 24
Peak memory 201932 kb
Host smart-8d46b132-9c36-4b09-927e-d0ef5017326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960947441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.960947441
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2531447023
Short name T234
Test name
Test status
Simulation time 34889835489 ps
CPU time 101.67 seconds
Started Jul 01 05:31:13 PM PDT 24
Finished Jul 01 05:32:55 PM PDT 24
Peak memory 211536 kb
Host smart-4c07c9a1-eb02-4723-bacd-475d261f570a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531447023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2531447023
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3737710072
Short name T321
Test name
Test status
Simulation time 486503288919 ps
CPU time 313.65 seconds
Started Jul 01 05:31:18 PM PDT 24
Finished Jul 01 05:36:32 PM PDT 24
Peak memory 202024 kb
Host smart-02280dd7-b490-4ca0-8347-f5355029c38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737710072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3737710072
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3646698805
Short name T343
Test name
Test status
Simulation time 132505250801 ps
CPU time 697.34 seconds
Started Jul 01 05:31:30 PM PDT 24
Finished Jul 01 05:43:08 PM PDT 24
Peak memory 202268 kb
Host smart-eba4f52e-e85d-437d-abf8-bb7302e405be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646698805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3646698805
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.708101841
Short name T82
Test name
Test status
Simulation time 4230422312 ps
CPU time 12.26 seconds
Started Jul 01 04:31:26 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 202024 kb
Host smart-8ede90b6-1ac6-4aeb-a125-ec036ccae43f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708101841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.708101841
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.888574433
Short name T42
Test name
Test status
Simulation time 318181555098 ps
CPU time 531.19 seconds
Started Jul 01 05:28:19 PM PDT 24
Finished Jul 01 05:37:11 PM PDT 24
Peak memory 212116 kb
Host smart-1d68dd92-153b-4837-bf23-23ea3d7a2a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888574433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
888574433
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3453690284
Short name T261
Test name
Test status
Simulation time 25181653730 ps
CPU time 66.14 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:30:14 PM PDT 24
Peak memory 210564 kb
Host smart-aa1d4e3c-38e1-44d9-a626-680847a4cd54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453690284 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3453690284
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.408909278
Short name T283
Test name
Test status
Simulation time 323588118440 ps
CPU time 184.95 seconds
Started Jul 01 05:30:27 PM PDT 24
Finished Jul 01 05:33:33 PM PDT 24
Peak memory 201956 kb
Host smart-67dbbc7c-e6b1-4bf9-9ded-5fb4afa4620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408909278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.408909278
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.62004924
Short name T325
Test name
Test status
Simulation time 325828274408 ps
CPU time 295.24 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:36:21 PM PDT 24
Peak memory 201936 kb
Host smart-d30d85a5-3355-4e89-8fc1-4b8829ea1ed5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62004924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gatin
g.62004924
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.363774659
Short name T265
Test name
Test status
Simulation time 334643467241 ps
CPU time 741.71 seconds
Started Jul 01 05:31:52 PM PDT 24
Finished Jul 01 05:44:14 PM PDT 24
Peak memory 201924 kb
Host smart-1ec78db4-4001-4b83-a5a9-17f7b5d013e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363774659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.363774659
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.263985468
Short name T269
Test name
Test status
Simulation time 370064463518 ps
CPU time 390.32 seconds
Started Jul 01 05:32:51 PM PDT 24
Finished Jul 01 05:39:23 PM PDT 24
Peak memory 201964 kb
Host smart-d8c0667f-7b7a-4eac-a8f6-8fe399ae0f18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263985468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.263985468
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.134485709
Short name T209
Test name
Test status
Simulation time 75352070763 ps
CPU time 372.88 seconds
Started Jul 01 05:33:15 PM PDT 24
Finished Jul 01 05:39:29 PM PDT 24
Peak memory 202276 kb
Host smart-a605d439-83e0-422d-a7de-c7a1f6f43032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134485709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.134485709
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3032460861
Short name T90
Test name
Test status
Simulation time 333137328372 ps
CPU time 161.41 seconds
Started Jul 01 05:34:46 PM PDT 24
Finished Jul 01 05:37:28 PM PDT 24
Peak memory 201884 kb
Host smart-9c332373-8df0-4228-afe6-87e4f44f8ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032460861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3032460861
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1739320461
Short name T339
Test name
Test status
Simulation time 8309528306 ps
CPU time 9.81 seconds
Started Jul 01 04:31:38 PM PDT 24
Finished Jul 01 04:31:59 PM PDT 24
Peak memory 201704 kb
Host smart-10003131-ade6-4fa9-9ae8-88271791a78e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739320461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1739320461
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2962689657
Short name T311
Test name
Test status
Simulation time 596755007924 ps
CPU time 360.08 seconds
Started Jul 01 05:27:43 PM PDT 24
Finished Jul 01 05:33:45 PM PDT 24
Peak memory 201836 kb
Host smart-79b874e7-61b6-4fa9-be09-ab14cd3668e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962689657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2962689657
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3099347766
Short name T242
Test name
Test status
Simulation time 47899784677 ps
CPU time 136.67 seconds
Started Jul 01 05:28:23 PM PDT 24
Finished Jul 01 05:30:41 PM PDT 24
Peak memory 211604 kb
Host smart-2d0d1b51-d579-4543-9858-51834a63ea3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099347766 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3099347766
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.433964021
Short name T213
Test name
Test status
Simulation time 70090824151 ps
CPU time 233.44 seconds
Started Jul 01 05:28:32 PM PDT 24
Finished Jul 01 05:32:26 PM PDT 24
Peak memory 210624 kb
Host smart-a29e8baa-459b-410c-b305-2733a9b75823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433964021 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.433964021
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.579335602
Short name T238
Test name
Test status
Simulation time 507108243676 ps
CPU time 288.99 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:33:57 PM PDT 24
Peak memory 201884 kb
Host smart-1354a9cd-9ce2-463e-b84e-bc8066176337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579335602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.579335602
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2622015557
Short name T288
Test name
Test status
Simulation time 629528486218 ps
CPU time 1232.28 seconds
Started Jul 01 05:27:50 PM PDT 24
Finished Jul 01 05:48:24 PM PDT 24
Peak memory 201900 kb
Host smart-58cdef69-cfaa-44d0-bde0-3e3431186b54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622015557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2622015557
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1536980992
Short name T322
Test name
Test status
Simulation time 487056454222 ps
CPU time 272.25 seconds
Started Jul 01 05:29:36 PM PDT 24
Finished Jul 01 05:34:09 PM PDT 24
Peak memory 201936 kb
Host smart-d6a27001-ea53-4a67-89f1-9b97061ff3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536980992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1536980992
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.292839809
Short name T282
Test name
Test status
Simulation time 520364496541 ps
CPU time 108.5 seconds
Started Jul 01 05:30:51 PM PDT 24
Finished Jul 01 05:32:40 PM PDT 24
Peak memory 201956 kb
Host smart-5676fb2a-ea88-4e50-86c7-9aa3b5903f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292839809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.292839809
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3862598438
Short name T204
Test name
Test status
Simulation time 116867619799 ps
CPU time 630.36 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:38:29 PM PDT 24
Peak memory 202304 kb
Host smart-21c83a88-af1d-48b3-b394-76137407c520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862598438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3862598438
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.804758190
Short name T208
Test name
Test status
Simulation time 91620535871 ps
CPU time 368.42 seconds
Started Jul 01 05:32:51 PM PDT 24
Finished Jul 01 05:39:00 PM PDT 24
Peak memory 202264 kb
Host smart-8bfc4379-d0ac-4d6d-bf51-9dffa5cb4897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804758190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.804758190
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1545757527
Short name T292
Test name
Test status
Simulation time 557806268766 ps
CPU time 645.9 seconds
Started Jul 01 05:34:12 PM PDT 24
Finished Jul 01 05:44:59 PM PDT 24
Peak memory 201888 kb
Host smart-7155d7f0-9ed7-4673-9095-163e592120db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545757527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1545757527
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.625490150
Short name T331
Test name
Test status
Simulation time 412819115009 ps
CPU time 640.93 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:38:55 PM PDT 24
Peak memory 217904 kb
Host smart-d5cb4c01-d453-432b-a47c-306582839439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625490150 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.625490150
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1730401018
Short name T817
Test name
Test status
Simulation time 864560562 ps
CPU time 3.33 seconds
Started Jul 01 04:31:27 PM PDT 24
Finished Jul 01 04:31:47 PM PDT 24
Peak memory 201692 kb
Host smart-cad35164-259a-4167-b94e-998f42d8427e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730401018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1730401018
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3928721690
Short name T869
Test name
Test status
Simulation time 26164896921 ps
CPU time 97.34 seconds
Started Jul 01 04:31:17 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 201832 kb
Host smart-8a8dbbe6-3a9f-46ea-b9b6-60b21b99dcbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928721690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3928721690
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3136724919
Short name T121
Test name
Test status
Simulation time 938678278 ps
CPU time 1.64 seconds
Started Jul 01 04:31:24 PM PDT 24
Finished Jul 01 04:31:37 PM PDT 24
Peak memory 201376 kb
Host smart-02426321-7b45-4615-a775-2374897a04af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136724919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3136724919
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1411179377
Short name T844
Test name
Test status
Simulation time 371036683 ps
CPU time 1.72 seconds
Started Jul 01 04:31:22 PM PDT 24
Finished Jul 01 04:31:34 PM PDT 24
Peak memory 201476 kb
Host smart-ac64e57d-2e0a-4297-bcd4-1b1e754e78fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411179377 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1411179377
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.376167326
Short name T115
Test name
Test status
Simulation time 481442463 ps
CPU time 1.4 seconds
Started Jul 01 04:31:16 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 201580 kb
Host smart-2fdaa4e7-87a0-4dd2-a601-f1f27e623667
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376167326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.376167326
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1686471634
Short name T896
Test name
Test status
Simulation time 280326179 ps
CPU time 1.35 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 201416 kb
Host smart-a539fdb6-648b-4f40-ba02-528154db8711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686471634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1686471634
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.221142580
Short name T898
Test name
Test status
Simulation time 5186320980 ps
CPU time 3.5 seconds
Started Jul 01 04:31:19 PM PDT 24
Finished Jul 01 04:31:33 PM PDT 24
Peak memory 201764 kb
Host smart-12ddc2d8-fb9f-49d8-8da2-145f2ec34f0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221142580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.221142580
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.672574867
Short name T874
Test name
Test status
Simulation time 363287363 ps
CPU time 2.06 seconds
Started Jul 01 04:31:26 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 201644 kb
Host smart-b5a1b166-5538-4bae-88e1-9cd04639051f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672574867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.672574867
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3457012665
Short name T847
Test name
Test status
Simulation time 8943534567 ps
CPU time 11.56 seconds
Started Jul 01 04:31:16 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 201816 kb
Host smart-183d0a7b-5e2b-40bf-8844-2da33a305dac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457012665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3457012665
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4218857449
Short name T858
Test name
Test status
Simulation time 1061878404 ps
CPU time 4.37 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 201684 kb
Host smart-fc42402b-b1df-4072-b3a4-2d0ddcc53713
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218857449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4218857449
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1659556493
Short name T117
Test name
Test status
Simulation time 26128420956 ps
CPU time 25.17 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:32:01 PM PDT 24
Peak memory 201740 kb
Host smart-ac75863c-906e-414c-b900-e8f98bc2abe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659556493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1659556493
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2389780607
Short name T106
Test name
Test status
Simulation time 1045030352 ps
CPU time 3.17 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 201584 kb
Host smart-c6c0ec39-4a21-4038-850b-9138f8b9b1c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389780607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2389780607
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1619580896
Short name T913
Test name
Test status
Simulation time 406552417 ps
CPU time 0.99 seconds
Started Jul 01 04:31:24 PM PDT 24
Finished Jul 01 04:31:36 PM PDT 24
Peak memory 201620 kb
Host smart-d30b4214-dcb7-4c51-ba7b-c850d2b53742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619580896 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1619580896
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3547638855
Short name T865
Test name
Test status
Simulation time 384124151 ps
CPU time 1.26 seconds
Started Jul 01 04:31:15 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 201348 kb
Host smart-cedfe1ef-6eda-4606-b6d3-d2c1cbdcc4b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547638855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3547638855
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3077039125
Short name T820
Test name
Test status
Simulation time 488851934 ps
CPU time 1.69 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 201328 kb
Host smart-5fed52cf-4175-4905-bccb-ab8ed670dc49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077039125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3077039125
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1925729212
Short name T882
Test name
Test status
Simulation time 4261161349 ps
CPU time 4.89 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:41 PM PDT 24
Peak memory 201776 kb
Host smart-6951ee7f-6bee-452f-8480-23cda9b25c07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925729212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1925729212
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1316017762
Short name T851
Test name
Test status
Simulation time 572063516 ps
CPU time 1.34 seconds
Started Jul 01 04:31:26 PM PDT 24
Finished Jul 01 04:31:38 PM PDT 24
Peak memory 201640 kb
Host smart-693f2529-ecf2-4d0b-83c3-6d49fa156625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316017762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1316017762
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1180588428
Short name T875
Test name
Test status
Simulation time 7708597413 ps
CPU time 11.17 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:47 PM PDT 24
Peak memory 201720 kb
Host smart-33fdc84e-db1b-4218-8595-c078b7dfd855
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180588428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1180588428
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3429925059
Short name T826
Test name
Test status
Simulation time 462275196 ps
CPU time 2.09 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:47 PM PDT 24
Peak memory 201556 kb
Host smart-80b4d9e2-f927-4f51-833d-c34dfc3d488a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429925059 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3429925059
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3308750173
Short name T871
Test name
Test status
Simulation time 400825020 ps
CPU time 1.23 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:48 PM PDT 24
Peak memory 201404 kb
Host smart-c2757dce-5b98-4a01-bef6-56579aee78b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308750173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3308750173
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.250271954
Short name T810
Test name
Test status
Simulation time 379026979 ps
CPU time 1.43 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:37 PM PDT 24
Peak memory 201296 kb
Host smart-6486741a-8325-4059-9697-6d823d8c6074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250271954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.250271954
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2747057781
Short name T892
Test name
Test status
Simulation time 2644441818 ps
CPU time 3.03 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:45 PM PDT 24
Peak memory 201600 kb
Host smart-fdbb249e-6660-49a8-a959-447c42c639b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747057781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2747057781
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.490442064
Short name T77
Test name
Test status
Simulation time 365833886 ps
CPU time 2.05 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 201760 kb
Host smart-9640911f-57f2-4343-bb92-a26544decf93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490442064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.490442064
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1815815117
Short name T895
Test name
Test status
Simulation time 4372228475 ps
CPU time 2.97 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:47 PM PDT 24
Peak memory 201832 kb
Host smart-c47013b1-4b43-4559-8705-c24af9f98a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815815117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1815815117
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.236092198
Short name T911
Test name
Test status
Simulation time 375178356 ps
CPU time 1.72 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201600 kb
Host smart-802f106e-f72f-4028-b4bf-ffeee2a6ef3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236092198 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.236092198
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1244011412
Short name T903
Test name
Test status
Simulation time 560744430 ps
CPU time 1.05 seconds
Started Jul 01 04:31:48 PM PDT 24
Finished Jul 01 04:32:05 PM PDT 24
Peak memory 201400 kb
Host smart-4d7ee41b-17a4-425a-8e47-6a142bfc69e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244011412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1244011412
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.213771934
Short name T829
Test name
Test status
Simulation time 468812549 ps
CPU time 1.71 seconds
Started Jul 01 04:31:47 PM PDT 24
Finished Jul 01 04:31:59 PM PDT 24
Peak memory 201436 kb
Host smart-aeb7c4cd-4259-44dc-8702-1f2291de01eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213771934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.213771934
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1294214734
Short name T873
Test name
Test status
Simulation time 627987976 ps
CPU time 4.19 seconds
Started Jul 01 04:31:53 PM PDT 24
Finished Jul 01 04:32:08 PM PDT 24
Peak memory 201700 kb
Host smart-1cb3f78e-726a-46c3-b45f-df5866d72ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294214734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1294214734
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2984525374
Short name T823
Test name
Test status
Simulation time 4858373402 ps
CPU time 3.35 seconds
Started Jul 01 04:31:40 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 201788 kb
Host smart-4a9afa52-c786-409e-a430-dff44314e859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984525374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2984525374
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.129037641
Short name T837
Test name
Test status
Simulation time 641866832 ps
CPU time 1.3 seconds
Started Jul 01 04:31:34 PM PDT 24
Finished Jul 01 04:31:47 PM PDT 24
Peak memory 201552 kb
Host smart-5d9fa7f1-92af-456d-9f46-36128b1c5702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129037641 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.129037641
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2914810778
Short name T112
Test name
Test status
Simulation time 352412063 ps
CPU time 1.71 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:31:59 PM PDT 24
Peak memory 201420 kb
Host smart-14c48ce7-a0a9-4c16-aabb-020d10bd944e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914810778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2914810778
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1335969229
Short name T809
Test name
Test status
Simulation time 410718623 ps
CPU time 1.7 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201328 kb
Host smart-42c2c4b4-e3ba-465f-a983-37ac411c268d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335969229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1335969229
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1168198820
Short name T64
Test name
Test status
Simulation time 4589597132 ps
CPU time 16.57 seconds
Started Jul 01 04:31:44 PM PDT 24
Finished Jul 01 04:32:11 PM PDT 24
Peak memory 201712 kb
Host smart-e15b155c-4620-40bf-92d1-d8f742bdbf74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168198820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1168198820
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1045248585
Short name T880
Test name
Test status
Simulation time 960770607 ps
CPU time 2.85 seconds
Started Jul 01 04:31:45 PM PDT 24
Finished Jul 01 04:31:59 PM PDT 24
Peak memory 210936 kb
Host smart-8e5fc101-e780-445f-8f06-c79c8e5cfbef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045248585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1045248585
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3109994793
Short name T69
Test name
Test status
Simulation time 4656509208 ps
CPU time 4.58 seconds
Started Jul 01 04:31:45 PM PDT 24
Finished Jul 01 04:32:00 PM PDT 24
Peak memory 201880 kb
Host smart-318a6d94-519a-4a85-bcac-2b9089063730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109994793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3109994793
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1812554864
Short name T890
Test name
Test status
Simulation time 679396798 ps
CPU time 2.67 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 201564 kb
Host smart-8773ce70-5202-4754-b09c-03270a60832b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812554864 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1812554864
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3476482879
Short name T116
Test name
Test status
Simulation time 348733870 ps
CPU time 1.45 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201492 kb
Host smart-aef6d5fb-79eb-4c86-9e96-8bc88a3715a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476482879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3476482879
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.660150579
Short name T848
Test name
Test status
Simulation time 551904442 ps
CPU time 0.94 seconds
Started Jul 01 04:31:48 PM PDT 24
Finished Jul 01 04:32:01 PM PDT 24
Peak memory 201488 kb
Host smart-68e94297-97cd-4270-908a-662e9b65956d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660150579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.660150579
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3313509210
Short name T889
Test name
Test status
Simulation time 5169395091 ps
CPU time 6.54 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:32:15 PM PDT 24
Peak memory 201832 kb
Host smart-d97e4aa4-d6ee-4ffd-b04f-336c57baab3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313509210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3313509210
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2912488687
Short name T917
Test name
Test status
Simulation time 589070392 ps
CPU time 2.8 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:47 PM PDT 24
Peak memory 217680 kb
Host smart-2c5f2f55-5e9a-488e-9b04-1bae4b7c58a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912488687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2912488687
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1590841167
Short name T340
Test name
Test status
Simulation time 4624567218 ps
CPU time 11.95 seconds
Started Jul 01 04:31:34 PM PDT 24
Finished Jul 01 04:31:57 PM PDT 24
Peak memory 201796 kb
Host smart-d2528f72-7606-4835-814e-ba3e2cc34f30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590841167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1590841167
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2541651588
Short name T852
Test name
Test status
Simulation time 655327434 ps
CPU time 2.41 seconds
Started Jul 01 04:31:38 PM PDT 24
Finished Jul 01 04:31:52 PM PDT 24
Peak memory 201460 kb
Host smart-c2b60853-ba24-466d-a780-9857cea11b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541651588 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2541651588
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2644873185
Short name T127
Test name
Test status
Simulation time 387082022 ps
CPU time 1.3 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 201468 kb
Host smart-22ad8217-5c64-4232-bba0-69ceca081276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644873185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2644873185
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2325061641
Short name T868
Test name
Test status
Simulation time 428163355 ps
CPU time 0.9 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201420 kb
Host smart-a5af481d-8216-4101-a6f8-3c9de7273633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325061641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2325061641
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2151712250
Short name T883
Test name
Test status
Simulation time 4485626881 ps
CPU time 3.69 seconds
Started Jul 01 04:31:40 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 201724 kb
Host smart-78a2c431-d302-4660-ad6e-4b917612ced4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151712250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2151712250
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.601147094
Short name T885
Test name
Test status
Simulation time 8985024769 ps
CPU time 7.35 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 201720 kb
Host smart-4709f075-0594-495f-a147-43b5fd173a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601147094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.601147094
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.828632059
Short name T845
Test name
Test status
Simulation time 638537366 ps
CPU time 1.32 seconds
Started Jul 01 04:31:49 PM PDT 24
Finished Jul 01 04:32:01 PM PDT 24
Peak memory 209880 kb
Host smart-8b29d872-7fe8-4718-8ef9-c9279d661dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828632059 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.828632059
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.665486380
Short name T894
Test name
Test status
Simulation time 486669856 ps
CPU time 1.7 seconds
Started Jul 01 04:31:36 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201492 kb
Host smart-928a8fc4-88ed-409d-8dbc-c6a2bc4d94e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665486380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.665486380
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1566924144
Short name T910
Test name
Test status
Simulation time 345159558 ps
CPU time 0.87 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:45 PM PDT 24
Peak memory 201416 kb
Host smart-8bda2a40-58d5-411d-966f-941485e0e59d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566924144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1566924144
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3805739838
Short name T901
Test name
Test status
Simulation time 3754178528 ps
CPU time 8.93 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:54 PM PDT 24
Peak memory 201848 kb
Host smart-621b31c0-e56b-489d-ba1c-0692c604ee48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805739838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3805739838
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1349839891
Short name T872
Test name
Test status
Simulation time 552978112 ps
CPU time 3.34 seconds
Started Jul 01 04:31:49 PM PDT 24
Finished Jul 01 04:32:04 PM PDT 24
Peak memory 201744 kb
Host smart-2372de3d-ef36-4825-a6d7-651f391d041a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349839891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1349839891
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2771145347
Short name T899
Test name
Test status
Simulation time 468984869 ps
CPU time 1.89 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 201552 kb
Host smart-6b4902c7-1ef4-4c2d-a167-a57dd186a366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771145347 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2771145347
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.698594891
Short name T842
Test name
Test status
Simulation time 474369311 ps
CPU time 1.29 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:45 PM PDT 24
Peak memory 201384 kb
Host smart-62e38a5b-2aab-42bc-90cc-bde753e12de4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698594891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.698594891
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.279502694
Short name T870
Test name
Test status
Simulation time 489892840 ps
CPU time 1.74 seconds
Started Jul 01 04:31:47 PM PDT 24
Finished Jul 01 04:32:00 PM PDT 24
Peak memory 201292 kb
Host smart-96555899-1224-4e02-aee5-2ce0c357f2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279502694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.279502694
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.672657782
Short name T124
Test name
Test status
Simulation time 3953520301 ps
CPU time 9.65 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:13 PM PDT 24
Peak memory 201744 kb
Host smart-0b843d29-d8e2-46fe-b204-fff6337cf6cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672657782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.672657782
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1613406781
Short name T862
Test name
Test status
Simulation time 320571623 ps
CPU time 2.13 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201620 kb
Host smart-6bf3d768-7557-42d1-8696-83d1faacafbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613406781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1613406781
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3895284594
Short name T833
Test name
Test status
Simulation time 9601818269 ps
CPU time 5.42 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:10 PM PDT 24
Peak memory 201728 kb
Host smart-46d554cf-bb10-45fb-bc6a-af569df4130d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895284594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3895284594
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3932802069
Short name T821
Test name
Test status
Simulation time 549570375 ps
CPU time 1.93 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 201552 kb
Host smart-93e8ae3f-927d-4dda-a237-548d833428eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932802069 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3932802069
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2024018482
Short name T109
Test name
Test status
Simulation time 437118455 ps
CPU time 1.04 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:48 PM PDT 24
Peak memory 201348 kb
Host smart-d9c56ec7-28d2-4852-bb39-4f2e4a3aa7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024018482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2024018482
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1229388142
Short name T907
Test name
Test status
Simulation time 287711646 ps
CPU time 0.94 seconds
Started Jul 01 04:31:45 PM PDT 24
Finished Jul 01 04:31:57 PM PDT 24
Peak memory 201344 kb
Host smart-e9ac9c25-2460-41b8-ad9e-6e423ea174af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229388142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1229388142
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2734632146
Short name T859
Test name
Test status
Simulation time 4685898942 ps
CPU time 3.75 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 201692 kb
Host smart-a0d11706-d9b2-42ce-82b7-58f50d92dc2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734632146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2734632146
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.64267562
Short name T83
Test name
Test status
Simulation time 767998428 ps
CPU time 1.68 seconds
Started Jul 01 04:31:47 PM PDT 24
Finished Jul 01 04:32:00 PM PDT 24
Peak memory 201716 kb
Host smart-96703c96-bee3-4c60-9dc6-940faa465a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64267562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.64267562
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2436885103
Short name T856
Test name
Test status
Simulation time 596696970 ps
CPU time 1.27 seconds
Started Jul 01 04:31:47 PM PDT 24
Finished Jul 01 04:32:00 PM PDT 24
Peak memory 201476 kb
Host smart-f3fe815f-0690-42f3-99a8-6e5161db7518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436885103 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2436885103
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3214766073
Short name T111
Test name
Test status
Simulation time 391010969 ps
CPU time 1.24 seconds
Started Jul 01 04:31:43 PM PDT 24
Finished Jul 01 04:31:56 PM PDT 24
Peak memory 201416 kb
Host smart-faf3746c-b886-4137-a71b-a8fb419a322a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214766073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3214766073
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1436022302
Short name T813
Test name
Test status
Simulation time 374064522 ps
CPU time 1.22 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:31:54 PM PDT 24
Peak memory 201396 kb
Host smart-21b2b318-ee33-4f83-9419-cf56360cfc8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436022302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1436022302
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2912484240
Short name T878
Test name
Test status
Simulation time 2153034877 ps
CPU time 2.63 seconds
Started Jul 01 04:31:49 PM PDT 24
Finished Jul 01 04:32:03 PM PDT 24
Peak memory 201616 kb
Host smart-98afacea-6ce3-47e6-8b6b-915b9ea60ca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912484240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2912484240
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.651190930
Short name T909
Test name
Test status
Simulation time 367370396 ps
CPU time 3.25 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:06 PM PDT 24
Peak memory 201656 kb
Host smart-7d988ea0-daa0-4efb-89f0-62be0c82bd65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651190930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.651190930
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3048132056
Short name T342
Test name
Test status
Simulation time 8382881475 ps
CPU time 20.7 seconds
Started Jul 01 04:31:48 PM PDT 24
Finished Jul 01 04:32:20 PM PDT 24
Peak memory 201776 kb
Host smart-acbd38e9-5817-416e-8bd2-2c354b87d302
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048132056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3048132056
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3252262126
Short name T71
Test name
Test status
Simulation time 607936443 ps
CPU time 1.34 seconds
Started Jul 01 04:31:53 PM PDT 24
Finished Jul 01 04:32:04 PM PDT 24
Peak memory 201444 kb
Host smart-5924057f-66f5-470c-8f2a-93f4ed2072e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252262126 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3252262126
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.735902639
Short name T126
Test name
Test status
Simulation time 486597761 ps
CPU time 0.91 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:31:58 PM PDT 24
Peak memory 201364 kb
Host smart-a6eadd90-2fac-41f6-9bd5-6ce4def316e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735902639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.735902639
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3055059173
Short name T861
Test name
Test status
Simulation time 383860759 ps
CPU time 1.6 seconds
Started Jul 01 04:31:44 PM PDT 24
Finished Jul 01 04:31:56 PM PDT 24
Peak memory 201260 kb
Host smart-346c3024-3ee0-454a-af8b-5f81f3b1c9d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055059173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3055059173
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2637728591
Short name T864
Test name
Test status
Simulation time 2334162151 ps
CPU time 8.1 seconds
Started Jul 01 04:31:50 PM PDT 24
Finished Jul 01 04:32:09 PM PDT 24
Peak memory 201508 kb
Host smart-0e5eb9d6-7c4c-4197-b432-8a36818ff15e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637728591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2637728591
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3609278549
Short name T76
Test name
Test status
Simulation time 361298636 ps
CPU time 2.29 seconds
Started Jul 01 04:31:38 PM PDT 24
Finished Jul 01 04:31:52 PM PDT 24
Peak memory 201768 kb
Host smart-eeca8646-1a52-4b73-8268-0b135b22edfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609278549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3609278549
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2411395197
Short name T902
Test name
Test status
Simulation time 8198985543 ps
CPU time 7.04 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:10 PM PDT 24
Peak memory 201724 kb
Host smart-50c292a5-ada6-45ab-908c-304ae379f0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411395197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2411395197
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2507002959
Short name T120
Test name
Test status
Simulation time 905536035 ps
CPU time 3.09 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 201588 kb
Host smart-62416a6c-f7e3-4684-84af-92a29570cab7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507002959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2507002959
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3811534116
Short name T129
Test name
Test status
Simulation time 26274959845 ps
CPU time 59.74 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:32:36 PM PDT 24
Peak memory 201744 kb
Host smart-fa88d8c6-977b-4927-82e8-cfdb2307114d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811534116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3811534116
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3246554892
Short name T830
Test name
Test status
Simulation time 1031179232 ps
CPU time 3.08 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 201368 kb
Host smart-98f28688-10dc-4538-9607-2068a57d5fda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246554892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3246554892
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.122735322
Short name T879
Test name
Test status
Simulation time 557208794 ps
CPU time 2.11 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:45 PM PDT 24
Peak memory 201616 kb
Host smart-525bf0d5-5ce6-4824-ae1c-306aacf5167b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122735322 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.122735322
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2159960417
Short name T860
Test name
Test status
Simulation time 403746561 ps
CPU time 0.84 seconds
Started Jul 01 04:31:23 PM PDT 24
Finished Jul 01 04:31:36 PM PDT 24
Peak memory 201492 kb
Host smart-69308b7c-7321-4e81-8c1f-2e60195da833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159960417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2159960417
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3151558446
Short name T807
Test name
Test status
Simulation time 411771550 ps
CPU time 0.85 seconds
Started Jul 01 04:31:17 PM PDT 24
Finished Jul 01 04:31:29 PM PDT 24
Peak memory 201332 kb
Host smart-93b4e576-a4e3-4e2c-84c6-95743a8ecb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151558446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3151558446
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3628482592
Short name T835
Test name
Test status
Simulation time 1635508045 ps
CPU time 2.18 seconds
Started Jul 01 04:31:16 PM PDT 24
Finished Jul 01 04:31:30 PM PDT 24
Peak memory 201488 kb
Host smart-7d1b537d-7ccb-4d64-b65a-34aa56b89a01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628482592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3628482592
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3689805361
Short name T906
Test name
Test status
Simulation time 543630576 ps
CPU time 3.71 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 211096 kb
Host smart-68d6d885-960d-4c3d-a7ac-cf793d57aaa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689805361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3689805361
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3176579166
Short name T854
Test name
Test status
Simulation time 4598195962 ps
CPU time 12.15 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 201796 kb
Host smart-48cd9ea8-80b2-4075-8adc-94f6e6b4fba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176579166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3176579166
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2275134644
Short name T915
Test name
Test status
Simulation time 338401907 ps
CPU time 1.07 seconds
Started Jul 01 04:31:36 PM PDT 24
Finished Jul 01 04:31:54 PM PDT 24
Peak memory 201324 kb
Host smart-7fe21b96-3ee2-49d5-8b59-859dd3aa1b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275134644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2275134644
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1476821383
Short name T918
Test name
Test status
Simulation time 368812604 ps
CPU time 1.54 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:04 PM PDT 24
Peak memory 201340 kb
Host smart-692a83f5-5ce4-4f9d-a3df-ead3177d5d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476821383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1476821383
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.953651984
Short name T827
Test name
Test status
Simulation time 465756681 ps
CPU time 0.94 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 201344 kb
Host smart-f402ebc4-a084-4985-a9c2-9046eaa6752e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953651984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.953651984
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.594926812
Short name T806
Test name
Test status
Simulation time 491085762 ps
CPU time 0.9 seconds
Started Jul 01 04:31:38 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201328 kb
Host smart-c422e794-27eb-466f-b7b4-7a07a742e83e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594926812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.594926812
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.279019967
Short name T849
Test name
Test status
Simulation time 449841393 ps
CPU time 0.83 seconds
Started Jul 01 04:31:38 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201316 kb
Host smart-75ae723e-2c43-497c-9aed-c080f9a4b975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279019967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.279019967
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4198010985
Short name T801
Test name
Test status
Simulation time 442335376 ps
CPU time 1.63 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:31:59 PM PDT 24
Peak memory 201388 kb
Host smart-bc0434b6-94ac-411c-b8b5-3bc4cbe5cdf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198010985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4198010985
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.224994175
Short name T846
Test name
Test status
Simulation time 363101601 ps
CPU time 0.85 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:05 PM PDT 24
Peak memory 201400 kb
Host smart-69dbb05e-0cdd-44b2-b133-5bf385a717c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224994175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.224994175
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2231958440
Short name T834
Test name
Test status
Simulation time 468497807 ps
CPU time 0.79 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 201340 kb
Host smart-62f78fe1-1734-44b1-b467-1ab18a15dc07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231958440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2231958440
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3342312974
Short name T867
Test name
Test status
Simulation time 383381222 ps
CPU time 1.11 seconds
Started Jul 01 04:31:45 PM PDT 24
Finished Jul 01 04:31:57 PM PDT 24
Peak memory 201604 kb
Host smart-8826940a-5601-44a6-8b42-d8a2a5b332f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342312974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3342312974
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4025950805
Short name T838
Test name
Test status
Simulation time 343965935 ps
CPU time 0.7 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 201416 kb
Host smart-6ef62b8b-f6b1-4013-9462-fb74a2bf37f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025950805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4025950805
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3856652623
Short name T113
Test name
Test status
Simulation time 778412046 ps
CPU time 1.95 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:41 PM PDT 24
Peak memory 201648 kb
Host smart-6c04cbdd-21b2-40ba-a7aa-fdefab8d5d19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856652623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3856652623
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3185669161
Short name T128
Test name
Test status
Simulation time 1130889704 ps
CPU time 3.52 seconds
Started Jul 01 04:31:29 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201492 kb
Host smart-64b74bd6-69b3-4508-b674-28dc32e6a92d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185669161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3185669161
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1174318
Short name T908
Test name
Test status
Simulation time 588614198 ps
CPU time 1.53 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201388 kb
Host smart-30cd415a-09f6-4c06-b6bd-82f6f486e62a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174318 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1174318
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2965347095
Short name T114
Test name
Test status
Simulation time 359326113 ps
CPU time 1.57 seconds
Started Jul 01 04:31:22 PM PDT 24
Finished Jul 01 04:31:35 PM PDT 24
Peak memory 201708 kb
Host smart-e58a915c-3c77-43f6-ba7f-bdd819ece4a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965347095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2965347095
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3509670008
Short name T900
Test name
Test status
Simulation time 372480867 ps
CPU time 0.9 seconds
Started Jul 01 04:31:17 PM PDT 24
Finished Jul 01 04:31:28 PM PDT 24
Peak memory 201340 kb
Host smart-648d6f06-517a-433e-b24e-26565808b3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509670008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3509670008
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1816521068
Short name T877
Test name
Test status
Simulation time 4421668747 ps
CPU time 3.76 seconds
Started Jul 01 04:31:34 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201932 kb
Host smart-fc443e80-08d0-4418-b969-4bd3e8a82357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816521068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1816521068
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3906925541
Short name T824
Test name
Test status
Simulation time 632807832 ps
CPU time 1.36 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 201652 kb
Host smart-816d24ee-c82b-40a7-a11e-12c4585994d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906925541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3906925541
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1058769855
Short name T891
Test name
Test status
Simulation time 5350119329 ps
CPU time 2.47 seconds
Started Jul 01 04:31:23 PM PDT 24
Finished Jul 01 04:31:37 PM PDT 24
Peak memory 201884 kb
Host smart-3ac8c3f7-2d09-4fe9-9eef-008c5207f923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058769855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1058769855
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3632236532
Short name T914
Test name
Test status
Simulation time 497431002 ps
CPU time 0.75 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201324 kb
Host smart-68dfa254-1c1d-447c-a48f-57a20fed53f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632236532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3632236532
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1662373170
Short name T802
Test name
Test status
Simulation time 502628403 ps
CPU time 0.97 seconds
Started Jul 01 04:31:40 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 201340 kb
Host smart-4207d5bf-82d2-462f-8627-5f53834617d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662373170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1662373170
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1746551294
Short name T857
Test name
Test status
Simulation time 467559710 ps
CPU time 1.19 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:31:59 PM PDT 24
Peak memory 201428 kb
Host smart-0a49a146-572f-4ae1-b3a4-eb2c2ca18708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746551294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1746551294
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4152788730
Short name T811
Test name
Test status
Simulation time 346084637 ps
CPU time 1.07 seconds
Started Jul 01 04:31:48 PM PDT 24
Finished Jul 01 04:31:59 PM PDT 24
Peak memory 201328 kb
Host smart-7dbab188-5f20-4604-9ef0-2d4962575c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152788730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4152788730
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3933532425
Short name T812
Test name
Test status
Simulation time 599788011 ps
CPU time 0.79 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201416 kb
Host smart-0bed1317-7046-4064-be4e-d8d8bc03baf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933532425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3933532425
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.407762433
Short name T832
Test name
Test status
Simulation time 332425613 ps
CPU time 0.8 seconds
Started Jul 01 04:31:39 PM PDT 24
Finished Jul 01 04:31:52 PM PDT 24
Peak memory 201420 kb
Host smart-6af32274-081e-4bbe-8df9-d41bde8718d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407762433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.407762433
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2407392910
Short name T815
Test name
Test status
Simulation time 515940408 ps
CPU time 0.99 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:48 PM PDT 24
Peak memory 201516 kb
Host smart-a98329f3-d8b0-4b62-8e34-e7a2455c3d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407392910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2407392910
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1164655550
Short name T843
Test name
Test status
Simulation time 337509645 ps
CPU time 0.88 seconds
Started Jul 01 04:31:36 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201316 kb
Host smart-90f40092-53c8-4de5-9dd1-890e57562510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164655550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1164655550
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3398521226
Short name T822
Test name
Test status
Simulation time 325606635 ps
CPU time 0.75 seconds
Started Jul 01 04:31:38 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201320 kb
Host smart-0dfdbd3a-4933-498c-876c-ebf7bb415ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398521226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3398521226
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.105280762
Short name T825
Test name
Test status
Simulation time 420307427 ps
CPU time 0.87 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201324 kb
Host smart-76b21f45-36d1-426c-b450-2bdd11d23998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105280762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.105280762
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1865906946
Short name T887
Test name
Test status
Simulation time 1263365584 ps
CPU time 3.06 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 201704 kb
Host smart-d3773be5-bdf8-4443-a9f1-8c66da5ea358
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865906946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1865906946
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1810691666
Short name T119
Test name
Test status
Simulation time 22390357829 ps
CPU time 72.63 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 201716 kb
Host smart-2e461953-11fd-480c-885a-9082ebb90f1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810691666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1810691666
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1716504803
Short name T863
Test name
Test status
Simulation time 1233415114 ps
CPU time 2.58 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:48 PM PDT 24
Peak memory 201508 kb
Host smart-222cf6cb-f4e0-4b17-aca9-17f62fdefc84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716504803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1716504803
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.817440103
Short name T70
Test name
Test status
Simulation time 533414574 ps
CPU time 1.47 seconds
Started Jul 01 04:31:34 PM PDT 24
Finished Jul 01 04:31:47 PM PDT 24
Peak memory 201552 kb
Host smart-aeb7c405-57cc-497c-b1b5-4b7f2b9b811b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817440103 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.817440103
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3203895344
Short name T884
Test name
Test status
Simulation time 476807162 ps
CPU time 1.3 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201584 kb
Host smart-2c25c471-5250-4416-9d03-c5c5872348ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203895344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3203895344
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.214673825
Short name T803
Test name
Test status
Simulation time 470363420 ps
CPU time 1.17 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:38 PM PDT 24
Peak memory 201348 kb
Host smart-3a3bf79d-1ef1-4af4-a374-468ca24eb73f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214673825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.214673825
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3766413136
Short name T125
Test name
Test status
Simulation time 2203520614 ps
CPU time 2.98 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:41 PM PDT 24
Peak memory 201620 kb
Host smart-1d01d15b-e7eb-487e-90e7-aeb778991527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766413136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3766413136
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2413322270
Short name T819
Test name
Test status
Simulation time 411337310 ps
CPU time 2.6 seconds
Started Jul 01 04:31:26 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 201768 kb
Host smart-a2fedbb6-ee44-4cfb-92e3-93d024f18588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413322270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2413322270
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1168732487
Short name T338
Test name
Test status
Simulation time 4803685529 ps
CPU time 7.17 seconds
Started Jul 01 04:31:34 PM PDT 24
Finished Jul 01 04:31:53 PM PDT 24
Peak memory 201860 kb
Host smart-b41472b8-4dbd-45e5-bc9c-9f1ba4fa8ade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168732487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1168732487
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.254896169
Short name T905
Test name
Test status
Simulation time 392883030 ps
CPU time 1.57 seconds
Started Jul 01 04:31:49 PM PDT 24
Finished Jul 01 04:32:02 PM PDT 24
Peak memory 201412 kb
Host smart-5b322f78-13cb-4d37-ba0f-e1a1375928d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254896169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.254896169
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1896627468
Short name T831
Test name
Test status
Simulation time 333442982 ps
CPU time 0.81 seconds
Started Jul 01 04:31:40 PM PDT 24
Finished Jul 01 04:31:52 PM PDT 24
Peak memory 201336 kb
Host smart-9ec4123d-66a6-4f20-a4bb-775449653905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896627468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1896627468
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1003533723
Short name T805
Test name
Test status
Simulation time 422243756 ps
CPU time 1.12 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:31:50 PM PDT 24
Peak memory 201292 kb
Host smart-45afcf03-5a30-46e4-956a-46db9341a623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003533723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1003533723
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1568740050
Short name T828
Test name
Test status
Simulation time 466391606 ps
CPU time 0.91 seconds
Started Jul 01 04:31:43 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 201416 kb
Host smart-56c91c94-8a0f-43c4-b721-11d4c0b55160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568740050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1568740050
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1891192299
Short name T839
Test name
Test status
Simulation time 363331578 ps
CPU time 1.51 seconds
Started Jul 01 04:31:48 PM PDT 24
Finished Jul 01 04:32:00 PM PDT 24
Peak memory 201340 kb
Host smart-090770f8-2ccf-4572-9b49-9e347ad18b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891192299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1891192299
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1207598135
Short name T836
Test name
Test status
Simulation time 357284431 ps
CPU time 0.81 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:31:58 PM PDT 24
Peak memory 201392 kb
Host smart-a1f7d942-d36e-4c92-95d6-fbe9af91bacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207598135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1207598135
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2406374199
Short name T814
Test name
Test status
Simulation time 370326325 ps
CPU time 1.37 seconds
Started Jul 01 04:31:36 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201296 kb
Host smart-c7d58f2d-814d-4dad-8329-567000300859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406374199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2406374199
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1251536474
Short name T866
Test name
Test status
Simulation time 331219785 ps
CPU time 0.84 seconds
Started Jul 01 04:31:42 PM PDT 24
Finished Jul 01 04:31:54 PM PDT 24
Peak memory 201416 kb
Host smart-3b40850d-6cd6-4430-8c38-2ee8af6cb09d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251536474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1251536474
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.297656289
Short name T808
Test name
Test status
Simulation time 463813302 ps
CPU time 0.88 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:32:10 PM PDT 24
Peak memory 201396 kb
Host smart-3791ae4f-9d00-45cb-a95b-9fdeb4734f5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297656289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.297656289
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.446152466
Short name T916
Test name
Test status
Simulation time 377825308 ps
CPU time 0.85 seconds
Started Jul 01 04:31:43 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 201340 kb
Host smart-26e1ea85-95a8-4e9d-8d9d-25cb1dfa2b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446152466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.446152466
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1125633677
Short name T886
Test name
Test status
Simulation time 632654241 ps
CPU time 1.6 seconds
Started Jul 01 04:31:29 PM PDT 24
Finished Jul 01 04:31:41 PM PDT 24
Peak memory 217988 kb
Host smart-20b41262-87bc-47d6-813f-58b7ae4d41cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125633677 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1125633677
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.511557225
Short name T107
Test name
Test status
Simulation time 483114665 ps
CPU time 2.02 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 201592 kb
Host smart-a03653df-4dd4-409e-91b1-219c008f555e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511557225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.511557225
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3027696162
Short name T912
Test name
Test status
Simulation time 487842246 ps
CPU time 0.96 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201608 kb
Host smart-828868bf-58ae-414a-80f0-1afcd6078802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027696162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3027696162
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3303543175
Short name T893
Test name
Test status
Simulation time 4264030955 ps
CPU time 5.28 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 201740 kb
Host smart-f4792c05-e2fb-4f44-9a69-fab617c697ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303543175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3303543175
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3996758546
Short name T68
Test name
Test status
Simulation time 8656497985 ps
CPU time 23.78 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:32:06 PM PDT 24
Peak memory 201704 kb
Host smart-65427296-1339-40f3-94f6-9112b578da5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996758546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3996758546
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4113942077
Short name T816
Test name
Test status
Simulation time 426695930 ps
CPU time 1.09 seconds
Started Jul 01 04:31:27 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 201464 kb
Host smart-c48c2377-35ba-475d-9bbc-5ad054c32d76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113942077 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4113942077
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.517362602
Short name T108
Test name
Test status
Simulation time 592383305 ps
CPU time 1.17 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:46 PM PDT 24
Peak memory 201416 kb
Host smart-f0d95368-3593-412c-af72-15b3e80425eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517362602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.517362602
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4122893488
Short name T881
Test name
Test status
Simulation time 492800524 ps
CPU time 1.76 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:31:48 PM PDT 24
Peak memory 201332 kb
Host smart-485d67a3-508d-4f0c-8a1e-0b383cb09f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122893488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4122893488
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2573422291
Short name T122
Test name
Test status
Simulation time 1900263601 ps
CPU time 1.89 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 201492 kb
Host smart-d2c3837f-3cba-469f-b2d1-f27dcd5ec96a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573422291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2573422291
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2893989381
Short name T81
Test name
Test status
Simulation time 416089904 ps
CPU time 1.75 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 201792 kb
Host smart-02870e6e-6a70-4f2f-accd-32cbf9d10075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893989381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2893989381
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1182070123
Short name T818
Test name
Test status
Simulation time 8286627099 ps
CPU time 23.28 seconds
Started Jul 01 04:31:29 PM PDT 24
Finished Jul 01 04:32:03 PM PDT 24
Peak memory 201716 kb
Host smart-d59ba3b9-071f-43bd-9f9e-b96590129a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182070123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1182070123
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.717366216
Short name T904
Test name
Test status
Simulation time 468891819 ps
CPU time 1.11 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:38 PM PDT 24
Peak memory 201552 kb
Host smart-3f81ae05-42c8-410c-b019-682121ff3879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717366216 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.717366216
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.603182289
Short name T840
Test name
Test status
Simulation time 386095186 ps
CPU time 1.58 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:40 PM PDT 24
Peak memory 201496 kb
Host smart-95deb689-d070-4777-a4cf-1721cbcbbf17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603182289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.603182289
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2643614213
Short name T804
Test name
Test status
Simulation time 398666915 ps
CPU time 1.05 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:49 PM PDT 24
Peak memory 201332 kb
Host smart-8b020a7f-1259-423f-92f7-73235e864d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643614213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2643614213
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3005187934
Short name T123
Test name
Test status
Simulation time 2372004966 ps
CPU time 6.07 seconds
Started Jul 01 04:31:26 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201720 kb
Host smart-fe05a1a0-2bc9-422f-a341-fb90fcaec397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005187934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3005187934
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1060762394
Short name T80
Test name
Test status
Simulation time 519946720 ps
CPU time 3.61 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 217952 kb
Host smart-ebc780e0-8f1e-4018-b35d-0c8952620c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060762394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1060762394
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2617452994
Short name T888
Test name
Test status
Simulation time 7944191559 ps
CPU time 11.67 seconds
Started Jul 01 04:31:30 PM PDT 24
Finished Jul 01 04:31:52 PM PDT 24
Peak memory 201756 kb
Host smart-bfb24692-c112-4f7f-825c-99d1bed59d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617452994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2617452994
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2401018792
Short name T95
Test name
Test status
Simulation time 553065481 ps
CPU time 1.75 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:45 PM PDT 24
Peak memory 201552 kb
Host smart-03226849-d933-4ac0-a40b-8761ec0a6542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401018792 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2401018792
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.872586665
Short name T118
Test name
Test status
Simulation time 468478036 ps
CPU time 1.95 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:38 PM PDT 24
Peak memory 201416 kb
Host smart-572f5055-3861-4f34-8e31-f43bea62c4f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872586665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.872586665
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1773181249
Short name T850
Test name
Test status
Simulation time 385917768 ps
CPU time 0.87 seconds
Started Jul 01 04:31:48 PM PDT 24
Finished Jul 01 04:32:00 PM PDT 24
Peak memory 201324 kb
Host smart-37dda226-f66b-4965-9b8f-56af845515bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773181249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1773181249
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1587583595
Short name T853
Test name
Test status
Simulation time 4071934737 ps
CPU time 18.81 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:32:03 PM PDT 24
Peak memory 201720 kb
Host smart-973fae0d-1f70-4b06-a02c-cbfa96d71e53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587583595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1587583595
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1557476846
Short name T78
Test name
Test status
Simulation time 617463289 ps
CPU time 1.78 seconds
Started Jul 01 04:31:25 PM PDT 24
Finished Jul 01 04:31:39 PM PDT 24
Peak memory 201712 kb
Host smart-491e30e0-56aa-4b8f-90f7-0dd8db46f0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557476846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1557476846
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.383751598
Short name T67
Test name
Test status
Simulation time 4056310038 ps
CPU time 9.93 seconds
Started Jul 01 04:31:33 PM PDT 24
Finished Jul 01 04:31:55 PM PDT 24
Peak memory 201852 kb
Host smart-478a8549-d618-4dfb-852a-594bc16fe4bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383751598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.383751598
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1257502632
Short name T84
Test name
Test status
Simulation time 530283937 ps
CPU time 1.3 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201464 kb
Host smart-5d7b8b69-d7c9-433e-9518-88fcb771a80b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257502632 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1257502632
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4156756003
Short name T110
Test name
Test status
Simulation time 335243882 ps
CPU time 1.18 seconds
Started Jul 01 04:31:32 PM PDT 24
Finished Jul 01 04:31:44 PM PDT 24
Peak memory 201348 kb
Host smart-42f335d5-a82f-4ae1-90b0-b626811e8b19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156756003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4156756003
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4202434785
Short name T876
Test name
Test status
Simulation time 471090722 ps
CPU time 0.93 seconds
Started Jul 01 04:31:31 PM PDT 24
Finished Jul 01 04:31:43 PM PDT 24
Peak memory 201348 kb
Host smart-8ed6d110-e4a3-4988-99b9-03ffe13add3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202434785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4202434785
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1510640496
Short name T855
Test name
Test status
Simulation time 4655464467 ps
CPU time 5.4 seconds
Started Jul 01 04:31:26 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 201896 kb
Host smart-ceb64779-24b2-4596-a3d0-cbbd52077a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510640496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1510640496
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.453555487
Short name T897
Test name
Test status
Simulation time 560372303 ps
CPU time 3.6 seconds
Started Jul 01 04:31:28 PM PDT 24
Finished Jul 01 04:31:42 PM PDT 24
Peak memory 217548 kb
Host smart-72f6e959-a34b-447b-95f4-3f6d8e2ac5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453555487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.453555487
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.4109786545
Short name T718
Test name
Test status
Simulation time 532254539 ps
CPU time 0.97 seconds
Started Jul 01 05:27:44 PM PDT 24
Finished Jul 01 05:27:46 PM PDT 24
Peak memory 201620 kb
Host smart-ffaec091-43e1-421a-a623-a8ed10d35880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109786545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.4109786545
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4096441430
Short name T243
Test name
Test status
Simulation time 169245589113 ps
CPU time 75.48 seconds
Started Jul 01 05:27:42 PM PDT 24
Finished Jul 01 05:28:59 PM PDT 24
Peak memory 201972 kb
Host smart-5eb92478-21bb-4145-b9f3-dc51f363df9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096441430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4096441430
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4134320765
Short name T440
Test name
Test status
Simulation time 495731295488 ps
CPU time 296.3 seconds
Started Jul 01 05:27:38 PM PDT 24
Finished Jul 01 05:32:36 PM PDT 24
Peak memory 201948 kb
Host smart-04f5974e-e079-4f8c-96c9-30113295044b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134320765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4134320765
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1810516719
Short name T296
Test name
Test status
Simulation time 484024163505 ps
CPU time 595.47 seconds
Started Jul 01 05:27:41 PM PDT 24
Finished Jul 01 05:37:38 PM PDT 24
Peak memory 201916 kb
Host smart-757e7703-51e8-45b6-9721-f78d1fb35a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810516719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1810516719
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2587093062
Short name T706
Test name
Test status
Simulation time 158688961054 ps
CPU time 47.02 seconds
Started Jul 01 05:27:38 PM PDT 24
Finished Jul 01 05:28:27 PM PDT 24
Peak memory 201936 kb
Host smart-64c71559-9dec-4a19-ac6b-7deb696fcc54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587093062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2587093062
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2803376872
Short name T267
Test name
Test status
Simulation time 462586545375 ps
CPU time 333.91 seconds
Started Jul 01 05:27:41 PM PDT 24
Finished Jul 01 05:33:16 PM PDT 24
Peak memory 201964 kb
Host smart-eae2799c-5b4f-43fc-971c-38aa2b1cad12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803376872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2803376872
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1609578609
Short name T799
Test name
Test status
Simulation time 412689621513 ps
CPU time 326.73 seconds
Started Jul 01 05:27:39 PM PDT 24
Finished Jul 01 05:33:07 PM PDT 24
Peak memory 201932 kb
Host smart-768491b0-ef3e-43d4-9f59-00681087b6ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609578609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1609578609
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3232162196
Short name T205
Test name
Test status
Simulation time 86473828467 ps
CPU time 274.48 seconds
Started Jul 01 05:27:43 PM PDT 24
Finished Jul 01 05:32:18 PM PDT 24
Peak memory 202260 kb
Host smart-b62e11d4-b840-475f-98b6-0eef59d82b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232162196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3232162196
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3974564263
Short name T452
Test name
Test status
Simulation time 28031860965 ps
CPU time 64.36 seconds
Started Jul 01 05:27:44 PM PDT 24
Finished Jul 01 05:28:50 PM PDT 24
Peak memory 201660 kb
Host smart-e5524046-ccb2-492f-b6e6-90a03c81469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974564263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3974564263
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.710631127
Short name T162
Test name
Test status
Simulation time 3345597622 ps
CPU time 8.1 seconds
Started Jul 01 05:27:41 PM PDT 24
Finished Jul 01 05:27:51 PM PDT 24
Peak memory 201680 kb
Host smart-30be129b-4789-4365-86e2-d4e320acd190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710631127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.710631127
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3811378326
Short name T698
Test name
Test status
Simulation time 5812398852 ps
CPU time 4.37 seconds
Started Jul 01 05:27:41 PM PDT 24
Finished Jul 01 05:27:47 PM PDT 24
Peak memory 201684 kb
Host smart-a22bdea3-fb52-4f1c-916e-3136f5558cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811378326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3811378326
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4153662182
Short name T351
Test name
Test status
Simulation time 78904370925 ps
CPU time 39.34 seconds
Started Jul 01 05:27:43 PM PDT 24
Finished Jul 01 05:28:23 PM PDT 24
Peak memory 201856 kb
Host smart-5d80d3ad-1813-4147-9d30-28a41b3b2851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153662182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4153662182
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1078708001
Short name T510
Test name
Test status
Simulation time 109484417585 ps
CPU time 152.09 seconds
Started Jul 01 05:27:43 PM PDT 24
Finished Jul 01 05:30:16 PM PDT 24
Peak memory 210568 kb
Host smart-77842bd5-9975-49e7-a2f3-cb2e080ef17e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078708001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1078708001
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2394379310
Short name T459
Test name
Test status
Simulation time 358015779 ps
CPU time 1.41 seconds
Started Jul 01 05:27:52 PM PDT 24
Finished Jul 01 05:27:55 PM PDT 24
Peak memory 201708 kb
Host smart-844eb4ca-9d65-4355-9dae-32baffeca24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394379310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2394379310
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1534704980
Short name T724
Test name
Test status
Simulation time 172176281514 ps
CPU time 324.16 seconds
Started Jul 01 05:27:45 PM PDT 24
Finished Jul 01 05:33:11 PM PDT 24
Peak memory 201940 kb
Host smart-a6fb371c-291a-4c8f-ab3f-a087dc56b723
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534704980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1534704980
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.385953554
Short name T638
Test name
Test status
Simulation time 404191349627 ps
CPU time 864.45 seconds
Started Jul 01 05:27:44 PM PDT 24
Finished Jul 01 05:42:10 PM PDT 24
Peak memory 201904 kb
Host smart-dcb82fd3-248a-4457-b16e-9ab1f27ac467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385953554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.385953554
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1489605198
Short name T294
Test name
Test status
Simulation time 495575548229 ps
CPU time 1098.72 seconds
Started Jul 01 05:27:46 PM PDT 24
Finished Jul 01 05:46:06 PM PDT 24
Peak memory 201940 kb
Host smart-1cea2f61-41c1-412f-9d42-32cf6ee144ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489605198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1489605198
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2554121542
Short name T99
Test name
Test status
Simulation time 161637826564 ps
CPU time 356.42 seconds
Started Jul 01 05:27:44 PM PDT 24
Finished Jul 01 05:33:42 PM PDT 24
Peak memory 201784 kb
Host smart-ecfbe505-24df-4575-a7d0-e9e490dd3515
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554121542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2554121542
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1510785162
Short name T196
Test name
Test status
Simulation time 331135451332 ps
CPU time 54.52 seconds
Started Jul 01 05:27:45 PM PDT 24
Finished Jul 01 05:28:41 PM PDT 24
Peak memory 201924 kb
Host smart-dabb7244-f13b-4edb-9825-f05e307444a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510785162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1510785162
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2384419636
Short name T398
Test name
Test status
Simulation time 485439978291 ps
CPU time 177.91 seconds
Started Jul 01 05:27:44 PM PDT 24
Finished Jul 01 05:30:44 PM PDT 24
Peak memory 201868 kb
Host smart-4e57dfe7-97e2-4281-a4c8-2889624b8113
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384419636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2384419636
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1631120904
Short name T604
Test name
Test status
Simulation time 401050852257 ps
CPU time 912.04 seconds
Started Jul 01 05:27:46 PM PDT 24
Finished Jul 01 05:42:59 PM PDT 24
Peak memory 201856 kb
Host smart-db101ab3-19b8-4c22-9f03-e2cc48d5005b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631120904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1631120904
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.110603071
Short name T442
Test name
Test status
Simulation time 118419501213 ps
CPU time 450.18 seconds
Started Jul 01 05:27:44 PM PDT 24
Finished Jul 01 05:35:16 PM PDT 24
Peak memory 202292 kb
Host smart-e3da8af4-8dca-4a2a-9c63-edd60907929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110603071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.110603071
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2772472580
Short name T631
Test name
Test status
Simulation time 22448995200 ps
CPU time 14.03 seconds
Started Jul 01 05:27:46 PM PDT 24
Finished Jul 01 05:28:01 PM PDT 24
Peak memory 201724 kb
Host smart-65ef39a6-dca6-4ecb-a9e0-21b06bf3e9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772472580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2772472580
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2882831305
Short name T485
Test name
Test status
Simulation time 4841511590 ps
CPU time 6.38 seconds
Started Jul 01 05:27:45 PM PDT 24
Finished Jul 01 05:27:53 PM PDT 24
Peak memory 201700 kb
Host smart-083cc4c5-ca26-4148-90d6-75109ef2e187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882831305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2882831305
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.909406558
Short name T86
Test name
Test status
Simulation time 3910116500 ps
CPU time 2.86 seconds
Started Jul 01 05:27:52 PM PDT 24
Finished Jul 01 05:27:56 PM PDT 24
Peak memory 217016 kb
Host smart-b6bb3c54-936f-49f9-be2e-6fb84dc289d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909406558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.909406558
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3858223194
Short name T583
Test name
Test status
Simulation time 5876523189 ps
CPU time 4.23 seconds
Started Jul 01 05:27:43 PM PDT 24
Finished Jul 01 05:27:49 PM PDT 24
Peak memory 201732 kb
Host smart-f3815d3f-5662-4085-ab0d-fceabd15e305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858223194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3858223194
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3055474029
Short name T734
Test name
Test status
Simulation time 325864587801 ps
CPU time 1014.04 seconds
Started Jul 01 05:27:51 PM PDT 24
Finished Jul 01 05:44:46 PM PDT 24
Peak memory 202248 kb
Host smart-1a9ceef0-28c9-4c67-95a2-ea32f8f08f32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055474029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3055474029
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3161298609
Short name T46
Test name
Test status
Simulation time 32354149469 ps
CPU time 46.96 seconds
Started Jul 01 05:27:52 PM PDT 24
Finished Jul 01 05:28:40 PM PDT 24
Peak memory 210588 kb
Host smart-7cf75e03-ca82-4f51-bcf5-a963702647c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161298609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3161298609
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.128659714
Short name T651
Test name
Test status
Simulation time 428676331 ps
CPU time 0.8 seconds
Started Jul 01 05:28:19 PM PDT 24
Finished Jul 01 05:28:21 PM PDT 24
Peak memory 201700 kb
Host smart-636601f3-09cb-4892-9ff3-1ad51e78d601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128659714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.128659714
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2840325058
Short name T138
Test name
Test status
Simulation time 328070825557 ps
CPU time 404.41 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:35:06 PM PDT 24
Peak memory 201864 kb
Host smart-658dd63a-105a-498f-a665-2f5bce25db44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840325058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2840325058
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1216299079
Short name T184
Test name
Test status
Simulation time 520339578737 ps
CPU time 318.9 seconds
Started Jul 01 05:28:21 PM PDT 24
Finished Jul 01 05:33:41 PM PDT 24
Peak memory 201908 kb
Host smart-462115ab-f6c1-4358-80b9-4279136875a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216299079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1216299079
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.4074350609
Short name T132
Test name
Test status
Simulation time 326718219993 ps
CPU time 752.14 seconds
Started Jul 01 05:28:16 PM PDT 24
Finished Jul 01 05:40:49 PM PDT 24
Peak memory 201964 kb
Host smart-492db915-d04f-4366-9968-f48980cb79ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074350609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.4074350609
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3450279040
Short name T501
Test name
Test status
Simulation time 488768558513 ps
CPU time 1156.34 seconds
Started Jul 01 05:28:15 PM PDT 24
Finished Jul 01 05:47:33 PM PDT 24
Peak memory 201992 kb
Host smart-36a60d25-544d-4b39-9270-e6dcba3b6db9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450279040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3450279040
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1697428978
Short name T576
Test name
Test status
Simulation time 494103674109 ps
CPU time 1039.58 seconds
Started Jul 01 05:28:13 PM PDT 24
Finished Jul 01 05:45:35 PM PDT 24
Peak memory 201792 kb
Host smart-f4467ab3-91b6-4684-b6b1-b589a35cf275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697428978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1697428978
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.133874941
Short name T602
Test name
Test status
Simulation time 324608661236 ps
CPU time 392.73 seconds
Started Jul 01 05:28:22 PM PDT 24
Finished Jul 01 05:34:56 PM PDT 24
Peak memory 201880 kb
Host smart-027bcbe7-5a45-40f1-a13a-0dea678f06af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=133874941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.133874941
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.832912855
Short name T186
Test name
Test status
Simulation time 584711927817 ps
CPU time 238.8 seconds
Started Jul 01 05:28:11 PM PDT 24
Finished Jul 01 05:32:12 PM PDT 24
Peak memory 201888 kb
Host smart-b6c2127e-6402-4fd2-9979-7430a2fc936f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832912855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.832912855
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3564451312
Short name T785
Test name
Test status
Simulation time 419002097039 ps
CPU time 368.85 seconds
Started Jul 01 05:28:18 PM PDT 24
Finished Jul 01 05:34:28 PM PDT 24
Peak memory 201872 kb
Host smart-06d62bcf-6eaa-4210-a84b-a03d0c1d19be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564451312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3564451312
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2578827562
Short name T410
Test name
Test status
Simulation time 130357634231 ps
CPU time 687.66 seconds
Started Jul 01 05:28:18 PM PDT 24
Finished Jul 01 05:39:46 PM PDT 24
Peak memory 202200 kb
Host smart-d454e83f-20bf-4b59-97cb-b293a96be721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578827562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2578827562
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2559699658
Short name T782
Test name
Test status
Simulation time 29392177607 ps
CPU time 9.42 seconds
Started Jul 01 05:28:21 PM PDT 24
Finished Jul 01 05:28:32 PM PDT 24
Peak memory 201672 kb
Host smart-ffce9b52-ecb8-46d2-8c89-8e3270bc06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559699658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2559699658
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.791339747
Short name T179
Test name
Test status
Simulation time 3100881331 ps
CPU time 2.16 seconds
Started Jul 01 05:28:19 PM PDT 24
Finished Jul 01 05:28:22 PM PDT 24
Peak memory 201668 kb
Host smart-d3f27ba5-1400-4e01-968c-2ed4d23e7980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791339747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.791339747
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1617627197
Short name T513
Test name
Test status
Simulation time 5738261873 ps
CPU time 7.43 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:28:22 PM PDT 24
Peak memory 201748 kb
Host smart-d0bcf102-1aaf-4f54-b210-ef1609d4dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617627197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1617627197
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.282187006
Short name T680
Test name
Test status
Simulation time 350867809901 ps
CPU time 197.64 seconds
Started Jul 01 05:28:18 PM PDT 24
Finished Jul 01 05:31:37 PM PDT 24
Peak memory 201944 kb
Host smart-e36bbbd0-41f2-4e92-9e0d-72581fe97998
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282187006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.282187006
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1963608928
Short name T632
Test name
Test status
Simulation time 167733478437 ps
CPU time 394.07 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:34:55 PM PDT 24
Peak memory 201900 kb
Host smart-62237066-445e-498c-b081-c7c88c6c09f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963608928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1963608928
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1122991074
Short name T228
Test name
Test status
Simulation time 327181016351 ps
CPU time 362.49 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:34:23 PM PDT 24
Peak memory 201852 kb
Host smart-347b7c47-3ba7-43db-99f2-2678172d2d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122991074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1122991074
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1302639584
Short name T493
Test name
Test status
Simulation time 327129116997 ps
CPU time 236.61 seconds
Started Jul 01 05:28:21 PM PDT 24
Finished Jul 01 05:32:19 PM PDT 24
Peak memory 201860 kb
Host smart-a3b28436-104f-486e-b104-97b56d6882a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302639584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1302639584
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1052354291
Short name T607
Test name
Test status
Simulation time 165266216484 ps
CPU time 345.25 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:34:07 PM PDT 24
Peak memory 201888 kb
Host smart-bbcdcb1b-5db0-487e-b9a6-d76a05f030c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052354291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1052354291
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2569137735
Short name T780
Test name
Test status
Simulation time 328271613968 ps
CPU time 691.47 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:39:52 PM PDT 24
Peak memory 201796 kb
Host smart-c843ec77-ca82-4a62-91f7-6fab04e9b0fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569137735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2569137735
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1797712015
Short name T792
Test name
Test status
Simulation time 535857074759 ps
CPU time 318.17 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:33:40 PM PDT 24
Peak memory 201880 kb
Host smart-ed5737a6-9113-4f5f-b81a-cd8b5d5ad858
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797712015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1797712015
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1027590479
Short name T707
Test name
Test status
Simulation time 95541737718 ps
CPU time 362.12 seconds
Started Jul 01 05:28:24 PM PDT 24
Finished Jul 01 05:34:27 PM PDT 24
Peak memory 202144 kb
Host smart-03f7ee07-1213-4c8a-92ca-90dd80dbe35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027590479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1027590479
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.691658098
Short name T628
Test name
Test status
Simulation time 34992123308 ps
CPU time 77.56 seconds
Started Jul 01 05:28:19 PM PDT 24
Finished Jul 01 05:29:37 PM PDT 24
Peak memory 201676 kb
Host smart-c2d5a746-7d39-4497-819b-fc68f9934a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691658098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.691658098
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2608679982
Short name T550
Test name
Test status
Simulation time 5235344903 ps
CPU time 3.72 seconds
Started Jul 01 05:28:20 PM PDT 24
Finished Jul 01 05:28:25 PM PDT 24
Peak memory 201856 kb
Host smart-07fac4d1-6dc4-43f0-a5d5-56e3f2a385d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608679982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2608679982
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.919700344
Short name T496
Test name
Test status
Simulation time 5506563291 ps
CPU time 6.98 seconds
Started Jul 01 05:28:18 PM PDT 24
Finished Jul 01 05:28:26 PM PDT 24
Peak memory 201660 kb
Host smart-5fc0f939-d9a5-46fd-8159-9ef01138914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919700344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.919700344
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3999379630
Short name T708
Test name
Test status
Simulation time 181470133869 ps
CPU time 155.22 seconds
Started Jul 01 05:28:19 PM PDT 24
Finished Jul 01 05:30:55 PM PDT 24
Peak memory 210212 kb
Host smart-10bffbdb-0723-47e8-baf5-80d18c2a3bbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999379630 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3999379630
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1103106093
Short name T444
Test name
Test status
Simulation time 316701601 ps
CPU time 1.36 seconds
Started Jul 01 05:28:27 PM PDT 24
Finished Jul 01 05:28:30 PM PDT 24
Peak memory 201632 kb
Host smart-42dce1d8-468a-4f3d-8624-9d07d2f1b43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103106093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1103106093
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.772784351
Short name T147
Test name
Test status
Simulation time 631334063524 ps
CPU time 1291.6 seconds
Started Jul 01 05:28:25 PM PDT 24
Finished Jul 01 05:49:58 PM PDT 24
Peak memory 201880 kb
Host smart-6001481f-b964-4fa6-8032-c2cd4d153278
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772784351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.772784351
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2558971089
Short name T542
Test name
Test status
Simulation time 486767297927 ps
CPU time 1167.36 seconds
Started Jul 01 05:28:25 PM PDT 24
Finished Jul 01 05:47:54 PM PDT 24
Peak memory 201952 kb
Host smart-d4494ad5-6b07-4d01-8da3-ed00a24c9591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558971089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2558971089
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1582177450
Short name T301
Test name
Test status
Simulation time 493885886957 ps
CPU time 1106.76 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:46:54 PM PDT 24
Peak memory 201904 kb
Host smart-ddc5a1fd-81f4-41a4-9fd0-259149d326da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582177450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1582177450
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2115055719
Short name T3
Test name
Test status
Simulation time 164222679668 ps
CPU time 175.25 seconds
Started Jul 01 05:28:25 PM PDT 24
Finished Jul 01 05:31:22 PM PDT 24
Peak memory 201888 kb
Host smart-31821f76-c1cd-4eed-b50d-7116ac5649b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115055719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2115055719
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2397743272
Short name T388
Test name
Test status
Simulation time 494354270071 ps
CPU time 1181.5 seconds
Started Jul 01 05:28:25 PM PDT 24
Finished Jul 01 05:48:07 PM PDT 24
Peak memory 201856 kb
Host smart-4a322b60-25eb-4dd6-8c33-05b3aa990976
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397743272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2397743272
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.725902085
Short name T268
Test name
Test status
Simulation time 539287956799 ps
CPU time 587.67 seconds
Started Jul 01 05:28:27 PM PDT 24
Finished Jul 01 05:38:16 PM PDT 24
Peak memory 202020 kb
Host smart-38dce785-ba54-404a-81b9-4e45fb9ab67c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725902085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.725902085
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1209278676
Short name T713
Test name
Test status
Simulation time 197031389764 ps
CPU time 437.13 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:35:45 PM PDT 24
Peak memory 201972 kb
Host smart-ec7e36de-40ad-4da4-a17d-445d2805a186
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209278676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1209278676
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4080502757
Short name T60
Test name
Test status
Simulation time 87319630682 ps
CPU time 353.18 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:34:21 PM PDT 24
Peak memory 202124 kb
Host smart-ce29d852-c3e4-473f-b63d-428dc3826ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080502757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4080502757
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3559908386
Short name T356
Test name
Test status
Simulation time 36142436228 ps
CPU time 81.82 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:29:49 PM PDT 24
Peak memory 201744 kb
Host smart-628be68d-b71c-49a5-b1b1-b93cb11304eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559908386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3559908386
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.568202321
Short name T54
Test name
Test status
Simulation time 4564326914 ps
CPU time 5.53 seconds
Started Jul 01 05:28:25 PM PDT 24
Finished Jul 01 05:28:32 PM PDT 24
Peak memory 201656 kb
Host smart-34902cf7-8972-496c-b05f-ff71f7e0c763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568202321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.568202321
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1594276928
Short name T527
Test name
Test status
Simulation time 5885223472 ps
CPU time 6.9 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:28:34 PM PDT 24
Peak memory 201680 kb
Host smart-1b0c53df-7edf-42a3-a59f-772697c709a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594276928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1594276928
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.350658018
Short name T697
Test name
Test status
Simulation time 686906930225 ps
CPU time 607.59 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:38:36 PM PDT 24
Peak memory 201820 kb
Host smart-2fd7b1dd-54d9-472f-bb76-19ed652ab2b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350658018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
350658018
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.333303659
Short name T51
Test name
Test status
Simulation time 50584593484 ps
CPU time 103.94 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:30:12 PM PDT 24
Peak memory 210424 kb
Host smart-f0c56a93-8382-4ad4-ab19-93bc645c885b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333303659 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.333303659
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.873164338
Short name T479
Test name
Test status
Simulation time 402036476 ps
CPU time 0.83 seconds
Started Jul 01 05:28:32 PM PDT 24
Finished Jul 01 05:28:33 PM PDT 24
Peak memory 201708 kb
Host smart-a55b3877-7a09-4534-a782-9d13e8f523d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873164338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.873164338
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3224355803
Short name T153
Test name
Test status
Simulation time 333183895790 ps
CPU time 796.1 seconds
Started Jul 01 05:28:34 PM PDT 24
Finished Jul 01 05:41:51 PM PDT 24
Peak memory 201904 kb
Host smart-f8934fa8-9d25-460e-b00f-9da3ea45e32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224355803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3224355803
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1774522532
Short name T492
Test name
Test status
Simulation time 163617015549 ps
CPU time 363.3 seconds
Started Jul 01 05:28:35 PM PDT 24
Finished Jul 01 05:34:39 PM PDT 24
Peak memory 201952 kb
Host smart-b334b9b0-392a-46f4-a865-b9ad813060d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774522532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1774522532
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.4138284501
Short name T603
Test name
Test status
Simulation time 163170683961 ps
CPU time 104.28 seconds
Started Jul 01 05:28:37 PM PDT 24
Finished Jul 01 05:30:23 PM PDT 24
Peak memory 201856 kb
Host smart-64485a6c-13ca-465e-9d90-8b80cb39135d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138284501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.4138284501
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2559976993
Short name T43
Test name
Test status
Simulation time 164672633489 ps
CPU time 364.83 seconds
Started Jul 01 05:28:28 PM PDT 24
Finished Jul 01 05:34:34 PM PDT 24
Peak memory 201916 kb
Host smart-dfa98edb-fd2a-4b1b-be20-ad90a192573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559976993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2559976993
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3113495153
Short name T358
Test name
Test status
Simulation time 489419357576 ps
CPU time 280.09 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:33:08 PM PDT 24
Peak memory 201916 kb
Host smart-57f3e654-de7d-4183-b4de-ba23b4f1b3cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113495153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3113495153
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3360178879
Short name T314
Test name
Test status
Simulation time 183430237884 ps
CPU time 111.63 seconds
Started Jul 01 05:28:35 PM PDT 24
Finished Jul 01 05:30:27 PM PDT 24
Peak memory 201892 kb
Host smart-befb98e1-8853-4558-bae7-e93576940b79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360178879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3360178879
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.692228431
Short name T376
Test name
Test status
Simulation time 416644621311 ps
CPU time 1006.22 seconds
Started Jul 01 05:28:31 PM PDT 24
Finished Jul 01 05:45:19 PM PDT 24
Peak memory 201924 kb
Host smart-1e74dedc-c3b9-4aad-a1fd-fb59107cf136
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692228431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.692228431
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4019549337
Short name T601
Test name
Test status
Simulation time 115495790868 ps
CPU time 635.2 seconds
Started Jul 01 05:28:30 PM PDT 24
Finished Jul 01 05:39:06 PM PDT 24
Peak memory 202356 kb
Host smart-4c30e768-94a6-4159-b550-b65e5783dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019549337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4019549337
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.804155614
Short name T394
Test name
Test status
Simulation time 41234025382 ps
CPU time 16.78 seconds
Started Jul 01 05:28:31 PM PDT 24
Finished Jul 01 05:28:49 PM PDT 24
Peak memory 201688 kb
Host smart-be6769fd-637e-463b-a043-4df19847ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804155614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.804155614
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1616657546
Short name T559
Test name
Test status
Simulation time 3351406417 ps
CPU time 2.46 seconds
Started Jul 01 05:28:34 PM PDT 24
Finished Jul 01 05:28:38 PM PDT 24
Peak memory 201672 kb
Host smart-3961f792-918a-4d31-b050-f03aa8896a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616657546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1616657546
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1811242028
Short name T530
Test name
Test status
Simulation time 5966179725 ps
CPU time 4.4 seconds
Started Jul 01 05:28:26 PM PDT 24
Finished Jul 01 05:28:32 PM PDT 24
Peak memory 201748 kb
Host smart-d7402344-3c4e-43c2-95cf-a99a7e79cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811242028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1811242028
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1698582065
Short name T93
Test name
Test status
Simulation time 325356512683 ps
CPU time 740.22 seconds
Started Jul 01 05:28:32 PM PDT 24
Finished Jul 01 05:40:54 PM PDT 24
Peak memory 212360 kb
Host smart-7de06dac-547a-49d3-a0a6-ff8ae579b719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698582065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1698582065
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3622863401
Short name T529
Test name
Test status
Simulation time 310454762 ps
CPU time 0.99 seconds
Started Jul 01 05:28:41 PM PDT 24
Finished Jul 01 05:28:42 PM PDT 24
Peak memory 201548 kb
Host smart-c3e94959-e313-4855-aaf9-6c063394d5e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622863401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3622863401
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1823145322
Short name T280
Test name
Test status
Simulation time 184883843972 ps
CPU time 455.99 seconds
Started Jul 01 05:28:36 PM PDT 24
Finished Jul 01 05:36:13 PM PDT 24
Peak memory 201860 kb
Host smart-4d7ff0cf-ee01-417a-98ae-50d0cdb96c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823145322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1823145322
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3286128926
Short name T589
Test name
Test status
Simulation time 501943845989 ps
CPU time 605.91 seconds
Started Jul 01 05:28:32 PM PDT 24
Finished Jul 01 05:38:40 PM PDT 24
Peak memory 201824 kb
Host smart-16ce26f7-b744-4bbe-82ea-fa05a5c25640
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286128926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3286128926
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.118499773
Short name T745
Test name
Test status
Simulation time 324995723445 ps
CPU time 755.05 seconds
Started Jul 01 05:28:32 PM PDT 24
Finished Jul 01 05:41:08 PM PDT 24
Peak memory 201916 kb
Host smart-5a525c44-b3b3-49b6-b923-b4072e6dac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118499773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.118499773
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.236647775
Short name T764
Test name
Test status
Simulation time 477669598300 ps
CPU time 1023.48 seconds
Started Jul 01 05:28:31 PM PDT 24
Finished Jul 01 05:45:36 PM PDT 24
Peak memory 201948 kb
Host smart-9961dca3-b933-401a-b50a-d5c24ad7b53c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=236647775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.236647775
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1627732964
Short name T145
Test name
Test status
Simulation time 384148047324 ps
CPU time 231.69 seconds
Started Jul 01 05:28:32 PM PDT 24
Finished Jul 01 05:32:25 PM PDT 24
Peak memory 201944 kb
Host smart-b6a5c902-39de-45f5-844a-07831c3c97a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627732964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1627732964
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.749143989
Short name T471
Test name
Test status
Simulation time 598245546325 ps
CPU time 1251.04 seconds
Started Jul 01 05:28:37 PM PDT 24
Finished Jul 01 05:49:29 PM PDT 24
Peak memory 201932 kb
Host smart-8c4b3949-a1b3-4dcb-8a7b-da7a9c155f53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749143989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.749143989
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1702334912
Short name T613
Test name
Test status
Simulation time 134696949532 ps
CPU time 517.64 seconds
Started Jul 01 05:28:46 PM PDT 24
Finished Jul 01 05:37:24 PM PDT 24
Peak memory 202184 kb
Host smart-a244a136-2065-41b8-a237-d0d8e92dba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702334912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1702334912
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2079840325
Short name T427
Test name
Test status
Simulation time 36580271759 ps
CPU time 81.52 seconds
Started Jul 01 05:28:40 PM PDT 24
Finished Jul 01 05:30:02 PM PDT 24
Peak memory 201604 kb
Host smart-60dd9ef1-b0b7-4d81-a55c-e57edda7bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079840325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2079840325
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1812895053
Short name T616
Test name
Test status
Simulation time 4109406431 ps
CPU time 11.09 seconds
Started Jul 01 05:28:37 PM PDT 24
Finished Jul 01 05:28:49 PM PDT 24
Peak memory 201720 kb
Host smart-d613c775-709a-4221-9666-7bb4d8129018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812895053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1812895053
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.181312361
Short name T561
Test name
Test status
Simulation time 6021526573 ps
CPU time 14.92 seconds
Started Jul 01 05:28:34 PM PDT 24
Finished Jul 01 05:28:50 PM PDT 24
Peak memory 201676 kb
Host smart-0a824654-16c7-401f-b97c-b014990cee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181312361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.181312361
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2843655538
Short name T159
Test name
Test status
Simulation time 385656555319 ps
CPU time 776.87 seconds
Started Jul 01 05:28:46 PM PDT 24
Finished Jul 01 05:41:43 PM PDT 24
Peak memory 201920 kb
Host smart-9a3dd80d-4ec6-4263-b3bf-243013a21609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843655538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2843655538
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3276216992
Short name T23
Test name
Test status
Simulation time 18769176128 ps
CPU time 46.56 seconds
Started Jul 01 05:28:37 PM PDT 24
Finished Jul 01 05:29:25 PM PDT 24
Peak memory 202368 kb
Host smart-0e22616d-ab10-4f38-be49-28040f382366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276216992 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3276216992
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.4226417908
Short name T359
Test name
Test status
Simulation time 329159801 ps
CPU time 1.4 seconds
Started Jul 01 05:28:49 PM PDT 24
Finished Jul 01 05:28:52 PM PDT 24
Peak memory 201708 kb
Host smart-38129bba-c445-4f8b-bbb5-383907e06865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226417908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4226417908
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2555061383
Short name T655
Test name
Test status
Simulation time 323508038902 ps
CPU time 372.26 seconds
Started Jul 01 05:28:42 PM PDT 24
Finished Jul 01 05:34:55 PM PDT 24
Peak memory 201988 kb
Host smart-28b9ec7e-ea59-43d5-a14d-50ad36b94a8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555061383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2555061383
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.559668338
Short name T525
Test name
Test status
Simulation time 331295652411 ps
CPU time 188.59 seconds
Started Jul 01 05:28:41 PM PDT 24
Finished Jul 01 05:31:50 PM PDT 24
Peak memory 201804 kb
Host smart-525af028-435f-4745-8514-1577f4de0ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559668338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.559668338
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3418029753
Short name T441
Test name
Test status
Simulation time 491713976791 ps
CPU time 1150.84 seconds
Started Jul 01 05:28:43 PM PDT 24
Finished Jul 01 05:47:55 PM PDT 24
Peak memory 201924 kb
Host smart-577c1be0-218a-49a5-bb19-0bf4439cfc7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418029753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3418029753
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.351419068
Short name T661
Test name
Test status
Simulation time 519490885722 ps
CPU time 609.48 seconds
Started Jul 01 05:28:44 PM PDT 24
Finished Jul 01 05:38:54 PM PDT 24
Peak memory 201952 kb
Host smart-1563f778-8bc9-46fe-ad7f-7eceb0974a9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351419068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.351419068
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2187356653
Short name T489
Test name
Test status
Simulation time 620764701817 ps
CPU time 160.84 seconds
Started Jul 01 05:28:42 PM PDT 24
Finished Jul 01 05:31:24 PM PDT 24
Peak memory 201820 kb
Host smart-4172d6c0-ebf9-418c-8cfc-3235ee7b4a28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187356653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2187356653
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3525377502
Short name T532
Test name
Test status
Simulation time 118207131346 ps
CPU time 456.78 seconds
Started Jul 01 05:28:52 PM PDT 24
Finished Jul 01 05:36:30 PM PDT 24
Peak memory 202216 kb
Host smart-623b188d-9d62-47ec-8e24-aa5b0a158a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525377502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3525377502
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2669275935
Short name T97
Test name
Test status
Simulation time 22730228061 ps
CPU time 49.37 seconds
Started Jul 01 05:28:48 PM PDT 24
Finished Jul 01 05:29:39 PM PDT 24
Peak memory 201756 kb
Host smart-ee523871-2753-4693-9406-56a483fe474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669275935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2669275935
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1731360254
Short name T538
Test name
Test status
Simulation time 4703834450 ps
CPU time 10.29 seconds
Started Jul 01 05:28:49 PM PDT 24
Finished Jul 01 05:29:00 PM PDT 24
Peak memory 201696 kb
Host smart-5babc08b-64b3-4631-a0ad-1fcfda9fa60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731360254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1731360254
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.568453390
Short name T701
Test name
Test status
Simulation time 5880673039 ps
CPU time 3.05 seconds
Started Jul 01 05:28:41 PM PDT 24
Finished Jul 01 05:28:44 PM PDT 24
Peak memory 201600 kb
Host smart-088d7971-ef13-4ada-adbc-4ebcd7a4434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568453390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.568453390
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3477466243
Short name T206
Test name
Test status
Simulation time 308669118602 ps
CPU time 691.98 seconds
Started Jul 01 05:28:50 PM PDT 24
Finished Jul 01 05:40:24 PM PDT 24
Peak memory 212844 kb
Host smart-a12b2f51-8efd-4077-a779-fb265c1eaa27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477466243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3477466243
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2459479496
Short name T715
Test name
Test status
Simulation time 351329916 ps
CPU time 0.99 seconds
Started Jul 01 05:28:54 PM PDT 24
Finished Jul 01 05:28:56 PM PDT 24
Peak memory 201624 kb
Host smart-9655c38c-40c6-40ed-b1d4-a79f13c56c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459479496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2459479496
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4270344811
Short name T502
Test name
Test status
Simulation time 156744034813 ps
CPU time 71.75 seconds
Started Jul 01 05:28:51 PM PDT 24
Finished Jul 01 05:30:03 PM PDT 24
Peak memory 202068 kb
Host smart-9067d505-98bd-4767-91c4-0a93c2d7b42f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270344811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4270344811
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2691098946
Short name T270
Test name
Test status
Simulation time 160054648771 ps
CPU time 169.9 seconds
Started Jul 01 05:28:49 PM PDT 24
Finished Jul 01 05:31:40 PM PDT 24
Peak memory 201900 kb
Host smart-8c54813c-7f32-472c-87b6-2553bda43d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691098946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2691098946
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1565842900
Short name T143
Test name
Test status
Simulation time 165375747302 ps
CPU time 164.07 seconds
Started Jul 01 05:28:49 PM PDT 24
Finished Jul 01 05:31:35 PM PDT 24
Peak memory 201884 kb
Host smart-a2375d6a-3e8a-495f-8d35-90df7276acc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565842900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1565842900
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1636104988
Short name T160
Test name
Test status
Simulation time 326074725083 ps
CPU time 213.71 seconds
Started Jul 01 05:28:50 PM PDT 24
Finished Jul 01 05:32:25 PM PDT 24
Peak memory 201904 kb
Host smart-60c19f23-aa99-4892-93c4-ac3739db37b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636104988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1636104988
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1632649301
Short name T420
Test name
Test status
Simulation time 329445416279 ps
CPU time 369.06 seconds
Started Jul 01 05:28:51 PM PDT 24
Finished Jul 01 05:35:01 PM PDT 24
Peak memory 201844 kb
Host smart-4fb22e13-4357-4c39-b40b-dc70292d5808
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632649301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1632649301
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.862550800
Short name T334
Test name
Test status
Simulation time 361263483930 ps
CPU time 795.92 seconds
Started Jul 01 05:28:49 PM PDT 24
Finished Jul 01 05:42:07 PM PDT 24
Peak memory 201896 kb
Host smart-9a76e4b4-4733-4867-922b-f1a233dbfd9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862550800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.862550800
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1661630975
Short name T797
Test name
Test status
Simulation time 203162569980 ps
CPU time 473.44 seconds
Started Jul 01 05:28:51 PM PDT 24
Finished Jul 01 05:36:45 PM PDT 24
Peak memory 201852 kb
Host smart-b4f2d6f9-6d50-4e88-8f21-50fbbd056e48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661630975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1661630975
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1765060940
Short name T791
Test name
Test status
Simulation time 123132457037 ps
CPU time 602.69 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 202268 kb
Host smart-fdb83ab8-bdec-43e0-830f-602e84c9fe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765060940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1765060940
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.295035437
Short name T728
Test name
Test status
Simulation time 30490542194 ps
CPU time 32.53 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:29:41 PM PDT 24
Peak memory 201680 kb
Host smart-e96cbea9-3d57-4c1b-92ef-f3ddde707bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295035437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.295035437
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.106758532
Short name T429
Test name
Test status
Simulation time 5116110980 ps
CPU time 6.05 seconds
Started Jul 01 05:28:55 PM PDT 24
Finished Jul 01 05:29:02 PM PDT 24
Peak memory 201636 kb
Host smart-cb68f86b-7db0-488d-84d6-d5acfed948fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106758532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.106758532
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2663696283
Short name T732
Test name
Test status
Simulation time 5838468884 ps
CPU time 7.81 seconds
Started Jul 01 05:28:50 PM PDT 24
Finished Jul 01 05:28:59 PM PDT 24
Peak memory 201756 kb
Host smart-425c54c6-ec6b-4c93-977c-d0dea0b4b518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663696283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2663696283
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3571206019
Short name T650
Test name
Test status
Simulation time 841328607388 ps
CPU time 716.72 seconds
Started Jul 01 05:28:56 PM PDT 24
Finished Jul 01 05:40:54 PM PDT 24
Peak memory 202152 kb
Host smart-4c163108-209b-4daa-b740-efc98f6719de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571206019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3571206019
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.631079141
Short name T599
Test name
Test status
Simulation time 467789094 ps
CPU time 1.59 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:29:10 PM PDT 24
Peak memory 201616 kb
Host smart-0ecc2152-a571-4bfa-96e6-ce60702a08ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631079141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.631079141
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.646280172
Short name T240
Test name
Test status
Simulation time 325742357908 ps
CPU time 369.45 seconds
Started Jul 01 05:28:53 PM PDT 24
Finished Jul 01 05:35:03 PM PDT 24
Peak memory 201804 kb
Host smart-cf4d5eed-2c42-4637-9b9d-6bc41c7dad70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646280172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.646280172
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1630196504
Short name T552
Test name
Test status
Simulation time 487983839357 ps
CPU time 1215.04 seconds
Started Jul 01 05:28:55 PM PDT 24
Finished Jul 01 05:49:12 PM PDT 24
Peak memory 201948 kb
Host smart-f554ff33-7527-4d19-a297-7b343e8c570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630196504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1630196504
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.170409989
Short name T522
Test name
Test status
Simulation time 497498552151 ps
CPU time 1130.33 seconds
Started Jul 01 05:28:56 PM PDT 24
Finished Jul 01 05:47:48 PM PDT 24
Peak memory 201880 kb
Host smart-3686a6e7-c925-4f8f-950c-dbb623df5aea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=170409989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.170409989
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3335345105
Short name T664
Test name
Test status
Simulation time 330794172611 ps
CPU time 620.06 seconds
Started Jul 01 05:28:57 PM PDT 24
Finished Jul 01 05:39:18 PM PDT 24
Peak memory 201720 kb
Host smart-dd9b8e88-cb18-48c5-b090-4ec2b1982603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335345105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3335345105
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3670004913
Short name T630
Test name
Test status
Simulation time 328930660829 ps
CPU time 182.78 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:32:10 PM PDT 24
Peak memory 201848 kb
Host smart-918f72ee-9dd0-4578-a214-52eaac985783
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670004913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3670004913
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2686534736
Short name T749
Test name
Test status
Simulation time 184224717170 ps
CPU time 450.38 seconds
Started Jul 01 05:28:55 PM PDT 24
Finished Jul 01 05:36:27 PM PDT 24
Peak memory 201884 kb
Host smart-38aa91f1-a254-4268-a543-af548593c73d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686534736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2686534736
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.219583539
Short name T592
Test name
Test status
Simulation time 392133853260 ps
CPU time 240.53 seconds
Started Jul 01 05:28:55 PM PDT 24
Finished Jul 01 05:32:57 PM PDT 24
Peak memory 201924 kb
Host smart-2e227daf-b5c6-4df3-afa4-a7fc18d7e492
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219583539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.219583539
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2642910473
Short name T679
Test name
Test status
Simulation time 96271999002 ps
CPU time 324.26 seconds
Started Jul 01 05:28:55 PM PDT 24
Finished Jul 01 05:34:21 PM PDT 24
Peak memory 202284 kb
Host smart-114510e3-76d2-4579-98df-8831dfde9854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642910473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2642910473
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3880672327
Short name T467
Test name
Test status
Simulation time 36820776546 ps
CPU time 23.69 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:29:31 PM PDT 24
Peak memory 201680 kb
Host smart-a8afdff6-7d09-4d7b-815d-51ccd18e91ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880672327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3880672327
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3850045788
Short name T743
Test name
Test status
Simulation time 4496040629 ps
CPU time 5.45 seconds
Started Jul 01 05:28:55 PM PDT 24
Finished Jul 01 05:29:01 PM PDT 24
Peak memory 201684 kb
Host smart-99977750-b338-4edc-91bb-06ac8294e41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850045788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3850045788
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1683835660
Short name T476
Test name
Test status
Simulation time 5935299156 ps
CPU time 3.47 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:29:11 PM PDT 24
Peak memory 201676 kb
Host smart-92ac036f-aa03-459b-bd96-2691173d3970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683835660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1683835660
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2486702499
Short name T348
Test name
Test status
Simulation time 15128574082 ps
CPU time 22.77 seconds
Started Jul 01 05:29:00 PM PDT 24
Finished Jul 01 05:29:24 PM PDT 24
Peak memory 201536 kb
Host smart-90e1d1a1-ee96-4964-8615-b6f7961a089a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486702499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2486702499
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2550871114
Short name T719
Test name
Test status
Simulation time 105471160476 ps
CPU time 95.32 seconds
Started Jul 01 05:28:56 PM PDT 24
Finished Jul 01 05:30:32 PM PDT 24
Peak memory 210584 kb
Host smart-f780845f-f6e4-4451-8e72-d35b78fa98db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550871114 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2550871114
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3567017344
Short name T477
Test name
Test status
Simulation time 392371281 ps
CPU time 1.53 seconds
Started Jul 01 05:29:05 PM PDT 24
Finished Jul 01 05:29:07 PM PDT 24
Peak memory 201644 kb
Host smart-ddf64ade-c878-41dc-b9a1-f7ae9a719fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567017344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3567017344
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2224109453
Short name T588
Test name
Test status
Simulation time 170033435246 ps
CPU time 115.95 seconds
Started Jul 01 05:29:01 PM PDT 24
Finished Jul 01 05:30:58 PM PDT 24
Peak memory 201912 kb
Host smart-732d90cc-fe8a-4ed2-aa10-30da440b6fb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224109453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2224109453
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2340377630
Short name T257
Test name
Test status
Simulation time 154699307833 ps
CPU time 185.98 seconds
Started Jul 01 05:28:59 PM PDT 24
Finished Jul 01 05:32:06 PM PDT 24
Peak memory 201892 kb
Host smart-476f80b9-102c-4078-8040-81bf042f5aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340377630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2340377630
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.303336790
Short name T231
Test name
Test status
Simulation time 163773383542 ps
CPU time 25.68 seconds
Started Jul 01 05:28:58 PM PDT 24
Finished Jul 01 05:29:26 PM PDT 24
Peak memory 201948 kb
Host smart-b343bd1c-e00b-4c00-837a-b28f34061f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303336790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.303336790
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3072582932
Short name T570
Test name
Test status
Simulation time 494067668449 ps
CPU time 266.48 seconds
Started Jul 01 05:28:59 PM PDT 24
Finished Jul 01 05:33:27 PM PDT 24
Peak memory 201848 kb
Host smart-8f5d1d78-9a00-471f-8ac6-9197ce0a1004
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072582932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3072582932
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1658084172
Short name T594
Test name
Test status
Simulation time 311245847192 ps
CPU time 709.64 seconds
Started Jul 01 05:28:54 PM PDT 24
Finished Jul 01 05:40:44 PM PDT 24
Peak memory 201968 kb
Host smart-e6471dfd-599d-4a2c-8eea-fe93d07e9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658084172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1658084172
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.161211059
Short name T676
Test name
Test status
Simulation time 326023703747 ps
CPU time 788.71 seconds
Started Jul 01 05:29:01 PM PDT 24
Finished Jul 01 05:42:11 PM PDT 24
Peak memory 201880 kb
Host smart-f5626aae-c2cf-4b9c-8e1a-8ce983e40452
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=161211059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.161211059
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3355429838
Short name T600
Test name
Test status
Simulation time 175493597917 ps
CPU time 96.51 seconds
Started Jul 01 05:28:59 PM PDT 24
Finished Jul 01 05:30:37 PM PDT 24
Peak memory 202020 kb
Host smart-1c890ef5-37ed-4ee3-a1e1-2639fbf42bb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355429838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3355429838
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1017038587
Short name T533
Test name
Test status
Simulation time 212442601785 ps
CPU time 119.98 seconds
Started Jul 01 05:29:00 PM PDT 24
Finished Jul 01 05:31:01 PM PDT 24
Peak memory 201864 kb
Host smart-7c4e31d4-7ee7-48ca-8375-b3f284e99be2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017038587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1017038587
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1522978698
Short name T203
Test name
Test status
Simulation time 113764505232 ps
CPU time 408.63 seconds
Started Jul 01 05:29:00 PM PDT 24
Finished Jul 01 05:35:50 PM PDT 24
Peak memory 202228 kb
Host smart-c176cc92-3e79-4a32-bc76-f8ceeb00af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522978698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1522978698
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3135177262
Short name T689
Test name
Test status
Simulation time 41054644986 ps
CPU time 24.55 seconds
Started Jul 01 05:28:58 PM PDT 24
Finished Jul 01 05:29:23 PM PDT 24
Peak memory 201756 kb
Host smart-285eda56-9c7a-43d2-b56d-dc46e6c70cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135177262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3135177262
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1176794449
Short name T731
Test name
Test status
Simulation time 3180506945 ps
CPU time 7.87 seconds
Started Jul 01 05:29:01 PM PDT 24
Finished Jul 01 05:29:10 PM PDT 24
Peak memory 201816 kb
Host smart-60bd1091-9e86-4be7-82ea-938be4e980e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176794449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1176794449
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.461660597
Short name T640
Test name
Test status
Simulation time 5906339257 ps
CPU time 2.62 seconds
Started Jul 01 05:28:56 PM PDT 24
Finished Jul 01 05:29:00 PM PDT 24
Peak memory 201756 kb
Host smart-eff5da4c-22e6-42f9-8066-ec62d6b5dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461660597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.461660597
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1237009715
Short name T230
Test name
Test status
Simulation time 166988966135 ps
CPU time 374.12 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:35:22 PM PDT 24
Peak memory 201880 kb
Host smart-178c5088-07be-4751-ae3a-6d94d9530ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237009715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1237009715
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3173656655
Short name T514
Test name
Test status
Simulation time 64891722510 ps
CPU time 50.65 seconds
Started Jul 01 05:29:00 PM PDT 24
Finished Jul 01 05:29:52 PM PDT 24
Peak memory 210208 kb
Host smart-a90f2c39-fed3-4324-a9fd-f0aef669279c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173656655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3173656655
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3925730380
Short name T484
Test name
Test status
Simulation time 439729319 ps
CPU time 1.14 seconds
Started Jul 01 05:29:11 PM PDT 24
Finished Jul 01 05:29:13 PM PDT 24
Peak memory 201660 kb
Host smart-8b71615e-de2a-4fe4-a93b-06771ad97591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925730380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3925730380
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2996549780
Short name T470
Test name
Test status
Simulation time 158060504907 ps
CPU time 2.79 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:29:11 PM PDT 24
Peak memory 201872 kb
Host smart-2ad04d0b-b299-4848-987d-41d317462a5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996549780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2996549780
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.17308522
Short name T798
Test name
Test status
Simulation time 157217885414 ps
CPU time 186.45 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:32:14 PM PDT 24
Peak memory 202052 kb
Host smart-8b612e23-803b-40eb-944d-0d19fbba319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17308522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.17308522
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.968101903
Short name T637
Test name
Test status
Simulation time 488663498042 ps
CPU time 1135.9 seconds
Started Jul 01 05:29:05 PM PDT 24
Finished Jul 01 05:48:02 PM PDT 24
Peak memory 201924 kb
Host smart-78cee753-7fa8-4aaa-9047-58fb4ca741f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=968101903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.968101903
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2511472379
Short name T32
Test name
Test status
Simulation time 493353802698 ps
CPU time 304.18 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:34:12 PM PDT 24
Peak memory 201924 kb
Host smart-4a4705e4-13c9-45ad-8eb1-16252412490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511472379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2511472379
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1019814730
Short name T405
Test name
Test status
Simulation time 333505236807 ps
CPU time 201.72 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:32:29 PM PDT 24
Peak memory 201832 kb
Host smart-44c6b751-7467-41c7-8000-29384ab763a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019814730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1019814730
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.226128831
Short name T310
Test name
Test status
Simulation time 523067353691 ps
CPU time 1247.11 seconds
Started Jul 01 05:29:05 PM PDT 24
Finished Jul 01 05:49:53 PM PDT 24
Peak memory 201984 kb
Host smart-cdf72211-886b-46b6-b4ef-95d2982199a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226128831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.226128831
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1866935221
Short name T29
Test name
Test status
Simulation time 407445410425 ps
CPU time 119.33 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:31:07 PM PDT 24
Peak memory 201936 kb
Host smart-57daad24-c595-4be6-bc42-2599e4128e25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866935221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1866935221
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1240096238
Short name T681
Test name
Test status
Simulation time 89374630880 ps
CPU time 481 seconds
Started Jul 01 05:29:13 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 202240 kb
Host smart-1651244a-576e-4695-808c-73c1f777ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240096238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1240096238
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2340649208
Short name T783
Test name
Test status
Simulation time 23964507445 ps
CPU time 11.8 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:29:20 PM PDT 24
Peak memory 201688 kb
Host smart-dc0b9428-8d6e-4e98-a5eb-0ffa4b7979c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340649208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2340649208
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.425550692
Short name T735
Test name
Test status
Simulation time 3843541263 ps
CPU time 5.07 seconds
Started Jul 01 05:29:06 PM PDT 24
Finished Jul 01 05:29:13 PM PDT 24
Peak memory 201684 kb
Host smart-07e3db3f-597f-4b8a-b8fe-76594794c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425550692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.425550692
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4158936740
Short name T733
Test name
Test status
Simulation time 6131586995 ps
CPU time 13.22 seconds
Started Jul 01 05:29:07 PM PDT 24
Finished Jul 01 05:29:21 PM PDT 24
Peak memory 201664 kb
Host smart-62833043-4c23-4749-9aa2-77fafa3fda6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158936740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4158936740
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3055387192
Short name T36
Test name
Test status
Simulation time 7940106392 ps
CPU time 18.8 seconds
Started Jul 01 05:29:11 PM PDT 24
Finished Jul 01 05:29:31 PM PDT 24
Peak memory 201680 kb
Host smart-5720c40f-f77f-4e66-8b31-388eb6fe4de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055387192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3055387192
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1555896159
Short name T332
Test name
Test status
Simulation time 105692630495 ps
CPU time 92.95 seconds
Started Jul 01 05:29:11 PM PDT 24
Finished Jul 01 05:30:45 PM PDT 24
Peak memory 218112 kb
Host smart-9183fc41-9fb3-43ae-9ecc-52434ca23dd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555896159 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1555896159
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3854847181
Short name T739
Test name
Test status
Simulation time 450129718 ps
CPU time 1.64 seconds
Started Jul 01 05:27:51 PM PDT 24
Finished Jul 01 05:27:54 PM PDT 24
Peak memory 201628 kb
Host smart-00b90fc1-03aa-4815-9f8d-4d3f6209351e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854847181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3854847181
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3644309876
Short name T700
Test name
Test status
Simulation time 488522584229 ps
CPU time 1107.23 seconds
Started Jul 01 05:27:50 PM PDT 24
Finished Jul 01 05:46:18 PM PDT 24
Peak memory 201956 kb
Host smart-041aa367-a747-4a4a-83f6-2acf0e34339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644309876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3644309876
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2527382915
Short name T432
Test name
Test status
Simulation time 164320426334 ps
CPU time 183.83 seconds
Started Jul 01 05:27:53 PM PDT 24
Finished Jul 01 05:30:58 PM PDT 24
Peak memory 201896 kb
Host smart-127c66cc-6d80-450a-b6ad-e6cdeb655c18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527382915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2527382915
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2845358551
Short name T387
Test name
Test status
Simulation time 165993335732 ps
CPU time 98.26 seconds
Started Jul 01 05:27:50 PM PDT 24
Finished Jul 01 05:29:29 PM PDT 24
Peak memory 201992 kb
Host smart-20021bc8-f167-4953-a6af-45a196b641a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845358551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2845358551
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3869931402
Short name T28
Test name
Test status
Simulation time 162392090630 ps
CPU time 177.73 seconds
Started Jul 01 05:27:51 PM PDT 24
Finished Jul 01 05:30:50 PM PDT 24
Peak memory 201856 kb
Host smart-e367d124-1071-492b-8ed0-821cd5e47802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869931402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3869931402
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3218910294
Short name T354
Test name
Test status
Simulation time 597317772232 ps
CPU time 362.47 seconds
Started Jul 01 05:27:51 PM PDT 24
Finished Jul 01 05:33:55 PM PDT 24
Peak memory 201940 kb
Host smart-9b9eec74-a999-4d13-8027-128c7ce99787
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218910294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3218910294
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3393712586
Short name T212
Test name
Test status
Simulation time 101320426411 ps
CPU time 359.35 seconds
Started Jul 01 05:27:51 PM PDT 24
Finished Jul 01 05:33:52 PM PDT 24
Peak memory 202184 kb
Host smart-f500bb75-9869-4e98-9e57-734563111890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393712586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3393712586
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2164259097
Short name T424
Test name
Test status
Simulation time 25716231496 ps
CPU time 15.71 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:28:13 PM PDT 24
Peak memory 201692 kb
Host smart-e918007b-48da-4e04-948f-c75c60b29ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164259097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2164259097
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.353809881
Short name T693
Test name
Test status
Simulation time 4884717264 ps
CPU time 10.48 seconds
Started Jul 01 05:27:53 PM PDT 24
Finished Jul 01 05:28:05 PM PDT 24
Peak memory 201716 kb
Host smart-f21e9ad1-09a1-494b-8359-800adb2a1ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353809881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.353809881
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1791643637
Short name T74
Test name
Test status
Simulation time 7915084636 ps
CPU time 2.88 seconds
Started Jul 01 05:27:51 PM PDT 24
Finished Jul 01 05:27:55 PM PDT 24
Peak memory 218216 kb
Host smart-e7acaa61-a320-48ba-97cc-07be8fdcfeb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791643637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1791643637
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2462298173
Short name T627
Test name
Test status
Simulation time 5975209248 ps
CPU time 1.62 seconds
Started Jul 01 05:27:50 PM PDT 24
Finished Jul 01 05:27:53 PM PDT 24
Peak memory 201680 kb
Host smart-d77f0f1d-88ce-4b2a-bfec-91ed438f74e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462298173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2462298173
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3563845460
Short name T273
Test name
Test status
Simulation time 336705589544 ps
CPU time 100.75 seconds
Started Jul 01 05:27:51 PM PDT 24
Finished Jul 01 05:29:32 PM PDT 24
Peak memory 201992 kb
Host smart-9ee456f3-281f-4646-84b3-2c2cd2aade85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563845460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3563845460
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1183786874
Short name T253
Test name
Test status
Simulation time 18643120083 ps
CPU time 39.15 seconds
Started Jul 01 05:27:50 PM PDT 24
Finished Jul 01 05:28:29 PM PDT 24
Peak memory 210248 kb
Host smart-44f3d296-5a99-4867-a218-413d71e5d484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183786874 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1183786874
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1509186219
Short name T406
Test name
Test status
Simulation time 311331368 ps
CPU time 0.78 seconds
Started Jul 01 05:29:29 PM PDT 24
Finished Jul 01 05:29:31 PM PDT 24
Peak memory 201624 kb
Host smart-a072baed-c280-487f-951d-cdd42735300c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509186219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1509186219
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1107491931
Short name T795
Test name
Test status
Simulation time 166757243615 ps
CPU time 96.61 seconds
Started Jul 01 05:29:18 PM PDT 24
Finished Jul 01 05:30:55 PM PDT 24
Peak memory 201944 kb
Host smart-a4b6cfeb-ad9c-4405-a564-06e43d5f9911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107491931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1107491931
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1041822555
Short name T368
Test name
Test status
Simulation time 326867689303 ps
CPU time 471.68 seconds
Started Jul 01 05:29:18 PM PDT 24
Finished Jul 01 05:37:10 PM PDT 24
Peak memory 201932 kb
Host smart-c80e5453-df3a-4951-8281-1dedad5ed7d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041822555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1041822555
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.870014122
Short name T255
Test name
Test status
Simulation time 494780733537 ps
CPU time 271.94 seconds
Started Jul 01 05:29:13 PM PDT 24
Finished Jul 01 05:33:46 PM PDT 24
Peak memory 201944 kb
Host smart-aeae8e92-be9e-4703-a5d8-1c5a18981223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870014122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.870014122
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1910518605
Short name T504
Test name
Test status
Simulation time 323199773967 ps
CPU time 736.06 seconds
Started Jul 01 05:29:11 PM PDT 24
Finished Jul 01 05:41:29 PM PDT 24
Peak memory 201852 kb
Host smart-315e254b-f03e-476c-bedc-33e37bfb04cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910518605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1910518605
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3129193951
Short name T618
Test name
Test status
Simulation time 171126578343 ps
CPU time 204.52 seconds
Started Jul 01 05:29:17 PM PDT 24
Finished Jul 01 05:32:42 PM PDT 24
Peak memory 201856 kb
Host smart-06c887a0-7d28-4fcb-a866-951bbce99c90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129193951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3129193951
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1323338309
Short name T170
Test name
Test status
Simulation time 393973080902 ps
CPU time 238.93 seconds
Started Jul 01 05:29:19 PM PDT 24
Finished Jul 01 05:33:19 PM PDT 24
Peak memory 201924 kb
Host smart-c5588783-fe45-4e97-b3f4-b845acdebf30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323338309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1323338309
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.4000867569
Short name T94
Test name
Test status
Simulation time 122044258852 ps
CPU time 617.73 seconds
Started Jul 01 05:29:23 PM PDT 24
Finished Jul 01 05:39:41 PM PDT 24
Peak memory 202112 kb
Host smart-1ad9cfce-dcb4-4878-be54-e7028a321e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000867569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.4000867569
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1960564559
Short name T669
Test name
Test status
Simulation time 28087958096 ps
CPU time 15.94 seconds
Started Jul 01 05:29:21 PM PDT 24
Finished Jul 01 05:29:38 PM PDT 24
Peak memory 201684 kb
Host smart-68bde75c-62ec-450b-8857-88bb01f6c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960564559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1960564559
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2197829651
Short name T369
Test name
Test status
Simulation time 4689095812 ps
CPU time 3.2 seconds
Started Jul 01 05:29:22 PM PDT 24
Finished Jul 01 05:29:26 PM PDT 24
Peak memory 201636 kb
Host smart-2b4c8159-0d23-4d5a-be6d-819308f3185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197829651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2197829651
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3711814795
Short name T449
Test name
Test status
Simulation time 5729619485 ps
CPU time 7.57 seconds
Started Jul 01 05:29:12 PM PDT 24
Finished Jul 01 05:29:20 PM PDT 24
Peak memory 201664 kb
Host smart-669ea7d7-9dd5-4df3-ab83-5e675292fe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711814795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3711814795
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3986543296
Short name T318
Test name
Test status
Simulation time 330006345468 ps
CPU time 190.3 seconds
Started Jul 01 05:29:28 PM PDT 24
Finished Jul 01 05:32:40 PM PDT 24
Peak memory 201964 kb
Host smart-950f99cf-8bea-42fd-a27b-2d4f5d938bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986543296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3986543296
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2289647714
Short name T573
Test name
Test status
Simulation time 32228833228 ps
CPU time 78.5 seconds
Started Jul 01 05:29:22 PM PDT 24
Finished Jul 01 05:30:41 PM PDT 24
Peak memory 210428 kb
Host smart-6f62e87e-1ee6-4246-b959-f9727d16f925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289647714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2289647714
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3527797472
Short name T4
Test name
Test status
Simulation time 437392501 ps
CPU time 0.86 seconds
Started Jul 01 05:29:42 PM PDT 24
Finished Jul 01 05:29:44 PM PDT 24
Peak memory 201636 kb
Host smart-be0e43da-13ef-4427-8cfa-23165a7b3071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527797472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3527797472
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3000272686
Short name T232
Test name
Test status
Simulation time 515811720892 ps
CPU time 1099.52 seconds
Started Jul 01 05:29:35 PM PDT 24
Finished Jul 01 05:47:56 PM PDT 24
Peak memory 201920 kb
Host smart-e6eadf1e-cad7-4fc1-b3d4-6dcf12ed243f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000272686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3000272686
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1378658669
Short name T355
Test name
Test status
Simulation time 325869412948 ps
CPU time 202.62 seconds
Started Jul 01 05:29:34 PM PDT 24
Finished Jul 01 05:32:58 PM PDT 24
Peak memory 201856 kb
Host smart-3ae3fb51-086f-422e-b2dc-bc69a58a9533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378658669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1378658669
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.728187375
Short name T490
Test name
Test status
Simulation time 163339817320 ps
CPU time 93.09 seconds
Started Jul 01 05:29:29 PM PDT 24
Finished Jul 01 05:31:03 PM PDT 24
Peak memory 201916 kb
Host smart-789e1d5e-29a6-406f-9751-d35d8fa75a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728187375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.728187375
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.978497047
Short name T668
Test name
Test status
Simulation time 159125506159 ps
CPU time 84.19 seconds
Started Jul 01 05:29:28 PM PDT 24
Finished Jul 01 05:30:54 PM PDT 24
Peak memory 201868 kb
Host smart-45eedd9b-7f69-471c-b7e7-cef56a5ea323
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=978497047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.978497047
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2143166528
Short name T135
Test name
Test status
Simulation time 555875654137 ps
CPU time 1276.45 seconds
Started Jul 01 05:29:35 PM PDT 24
Finished Jul 01 05:50:52 PM PDT 24
Peak memory 201948 kb
Host smart-b0760184-701a-4a49-88ca-6b6a6499db3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143166528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2143166528
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2338016192
Short name T357
Test name
Test status
Simulation time 202161314479 ps
CPU time 467.06 seconds
Started Jul 01 05:29:36 PM PDT 24
Finished Jul 01 05:37:24 PM PDT 24
Peak memory 201856 kb
Host smart-b20c89bb-59f6-434b-af1f-bbb5be160de5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338016192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2338016192
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1578122608
Short name T539
Test name
Test status
Simulation time 111745844715 ps
CPU time 481.57 seconds
Started Jul 01 05:29:35 PM PDT 24
Finished Jul 01 05:37:37 PM PDT 24
Peak memory 202300 kb
Host smart-d25bb654-3c79-4fbe-9ac6-1e5584b0ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578122608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1578122608
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1667705791
Short name T403
Test name
Test status
Simulation time 37786935285 ps
CPU time 79.85 seconds
Started Jul 01 05:29:37 PM PDT 24
Finished Jul 01 05:30:58 PM PDT 24
Peak memory 201652 kb
Host smart-1ac8bd76-ca9e-492e-9f47-9d24784ed782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667705791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1667705791
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2439172040
Short name T498
Test name
Test status
Simulation time 4904548482 ps
CPU time 12 seconds
Started Jul 01 05:29:34 PM PDT 24
Finished Jul 01 05:29:47 PM PDT 24
Peak memory 201680 kb
Host smart-74b5202b-9f96-445f-a92b-b756de812f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439172040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2439172040
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3630370604
Short name T694
Test name
Test status
Simulation time 5752153577 ps
CPU time 14.75 seconds
Started Jul 01 05:29:29 PM PDT 24
Finished Jul 01 05:29:45 PM PDT 24
Peak memory 201680 kb
Host smart-1c4e0262-5ee3-43f5-ba77-e4c6d137c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630370604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3630370604
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.437866803
Short name T786
Test name
Test status
Simulation time 208828131729 ps
CPU time 128.57 seconds
Started Jul 01 05:29:35 PM PDT 24
Finished Jul 01 05:31:45 PM PDT 24
Peak memory 201916 kb
Host smart-66e0a868-a6f8-4891-bd9c-c5da52a2adcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437866803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
437866803
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.893048681
Short name T18
Test name
Test status
Simulation time 84172131306 ps
CPU time 118.43 seconds
Started Jul 01 05:29:36 PM PDT 24
Finished Jul 01 05:31:36 PM PDT 24
Peak memory 210588 kb
Host smart-69df77e5-76c0-499b-bcd7-30b967826d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893048681 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.893048681
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4220498426
Short name T670
Test name
Test status
Simulation time 537895621 ps
CPU time 0.95 seconds
Started Jul 01 05:29:46 PM PDT 24
Finished Jul 01 05:29:49 PM PDT 24
Peak memory 201692 kb
Host smart-7c225d04-865c-4335-850b-e2f76dc0bf5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220498426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4220498426
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3346274982
Short name T252
Test name
Test status
Simulation time 536280292247 ps
CPU time 197.21 seconds
Started Jul 01 05:29:40 PM PDT 24
Finished Jul 01 05:32:59 PM PDT 24
Peak memory 201848 kb
Host smart-43b9a050-2fcb-4620-8498-07ee49c36f6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346274982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3346274982
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1093641162
Short name T750
Test name
Test status
Simulation time 322744482397 ps
CPU time 691.16 seconds
Started Jul 01 05:29:42 PM PDT 24
Finished Jul 01 05:41:15 PM PDT 24
Peak memory 201956 kb
Host smart-94e2bdb1-377c-49df-9f12-375744a0aa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093641162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1093641162
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1683372103
Short name T275
Test name
Test status
Simulation time 325663815547 ps
CPU time 374.83 seconds
Started Jul 01 05:29:39 PM PDT 24
Finished Jul 01 05:35:56 PM PDT 24
Peak memory 201884 kb
Host smart-33daf789-b45f-4a6b-8442-8bc83040b96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683372103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1683372103
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2604975177
Short name T226
Test name
Test status
Simulation time 163685796297 ps
CPU time 369.65 seconds
Started Jul 01 05:29:40 PM PDT 24
Finished Jul 01 05:35:52 PM PDT 24
Peak memory 201804 kb
Host smart-04025142-b7d0-473f-9c7b-21841532fd70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604975177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2604975177
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1385915743
Short name T768
Test name
Test status
Simulation time 484384308320 ps
CPU time 593.29 seconds
Started Jul 01 05:29:41 PM PDT 24
Finished Jul 01 05:39:36 PM PDT 24
Peak memory 201920 kb
Host smart-afec019c-6652-43db-95e8-4a24290cbb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385915743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1385915743
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.384678972
Short name T380
Test name
Test status
Simulation time 487504756196 ps
CPU time 504.11 seconds
Started Jul 01 05:29:39 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 201952 kb
Host smart-055fb265-17e0-46fd-9abf-02b17c9ee598
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=384678972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.384678972
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1679403252
Short name T290
Test name
Test status
Simulation time 438218337116 ps
CPU time 916.61 seconds
Started Jul 01 05:29:40 PM PDT 24
Finished Jul 01 05:44:58 PM PDT 24
Peak memory 201972 kb
Host smart-668280dc-591f-4c52-affa-9e426baf4691
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679403252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1679403252
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1120875269
Short name T443
Test name
Test status
Simulation time 601861780084 ps
CPU time 1228.82 seconds
Started Jul 01 05:29:40 PM PDT 24
Finished Jul 01 05:50:11 PM PDT 24
Peak memory 201860 kb
Host smart-b53b9141-2466-4437-89e8-815a91223d9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120875269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1120875269
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3528704644
Short name T207
Test name
Test status
Simulation time 99111135601 ps
CPU time 379.04 seconds
Started Jul 01 05:29:46 PM PDT 24
Finished Jul 01 05:36:07 PM PDT 24
Peak memory 202276 kb
Host smart-a8245d3f-bb7d-4235-aaf6-100e95d82926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528704644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3528704644
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3435827676
Short name T610
Test name
Test status
Simulation time 27996531924 ps
CPU time 61.18 seconds
Started Jul 01 05:29:41 PM PDT 24
Finished Jul 01 05:30:44 PM PDT 24
Peak memory 201860 kb
Host smart-bfb310dc-68d2-4015-b759-440d93cf8db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435827676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3435827676
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.647809343
Short name T347
Test name
Test status
Simulation time 5246590188 ps
CPU time 13.92 seconds
Started Jul 01 05:29:39 PM PDT 24
Finished Jul 01 05:29:55 PM PDT 24
Peak memory 201688 kb
Host smart-103d9f46-754d-42e4-afe6-c75b9fa43fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647809343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.647809343
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3833334457
Short name T544
Test name
Test status
Simulation time 5790580960 ps
CPU time 14.23 seconds
Started Jul 01 05:29:41 PM PDT 24
Finished Jul 01 05:29:57 PM PDT 24
Peak memory 201632 kb
Host smart-70a8b3fb-cf5e-472b-b25b-369318b3d82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833334457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3833334457
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3997122076
Short name T784
Test name
Test status
Simulation time 9088631650 ps
CPU time 23.54 seconds
Started Jul 01 05:29:48 PM PDT 24
Finished Jul 01 05:30:14 PM PDT 24
Peak memory 201760 kb
Host smart-b948689f-8f96-48d9-b73a-32c776466d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997122076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3997122076
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.4015570314
Short name T175
Test name
Test status
Simulation time 184064665158 ps
CPU time 229.05 seconds
Started Jul 01 05:29:46 PM PDT 24
Finished Jul 01 05:33:38 PM PDT 24
Peak memory 210504 kb
Host smart-b723d972-68d6-4edf-9053-cd59859da2f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015570314 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.4015570314
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.743412328
Short name T517
Test name
Test status
Simulation time 490186493 ps
CPU time 1.2 seconds
Started Jul 01 05:29:53 PM PDT 24
Finished Jul 01 05:29:55 PM PDT 24
Peak memory 201672 kb
Host smart-e77531e2-db5e-4707-890f-67f46e0affe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743412328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.743412328
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3481451378
Short name T158
Test name
Test status
Simulation time 418815016430 ps
CPU time 105.28 seconds
Started Jul 01 05:29:47 PM PDT 24
Finished Jul 01 05:31:35 PM PDT 24
Peak memory 201940 kb
Host smart-35036ff8-cc2b-487d-8efb-c57b46640118
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481451378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3481451378
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.698795901
Short name T289
Test name
Test status
Simulation time 167142676500 ps
CPU time 50.59 seconds
Started Jul 01 05:29:46 PM PDT 24
Finished Jul 01 05:30:38 PM PDT 24
Peak memory 202048 kb
Host smart-b55937e6-5e62-441d-9165-0074f4314566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698795901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.698795901
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1913501662
Short name T569
Test name
Test status
Simulation time 169614861806 ps
CPU time 361.04 seconds
Started Jul 01 05:29:48 PM PDT 24
Finished Jul 01 05:35:51 PM PDT 24
Peak memory 201960 kb
Host smart-02a1cd36-feb1-4a42-ac55-75c7d01fe1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913501662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1913501662
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2389626671
Short name T688
Test name
Test status
Simulation time 489408906184 ps
CPU time 1124.4 seconds
Started Jul 01 05:29:48 PM PDT 24
Finished Jul 01 05:48:34 PM PDT 24
Peak memory 201924 kb
Host smart-12f59252-3e8e-4640-88eb-da6a260c8963
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389626671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2389626671
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.179178603
Short name T323
Test name
Test status
Simulation time 329386399165 ps
CPU time 689.85 seconds
Started Jul 01 05:29:47 PM PDT 24
Finished Jul 01 05:41:19 PM PDT 24
Peak memory 201964 kb
Host smart-edb8fb3a-0a80-4cd0-bd7c-7d766cca64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179178603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.179178603
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.657483189
Short name T761
Test name
Test status
Simulation time 166662900622 ps
CPU time 371.4 seconds
Started Jul 01 05:29:47 PM PDT 24
Finished Jul 01 05:36:00 PM PDT 24
Peak memory 201864 kb
Host smart-4a05f258-750a-4f63-b1ea-2b674fae1011
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=657483189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.657483189
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3496371680
Short name T418
Test name
Test status
Simulation time 404725196213 ps
CPU time 463.75 seconds
Started Jul 01 05:29:53 PM PDT 24
Finished Jul 01 05:37:38 PM PDT 24
Peak memory 201932 kb
Host smart-092ea0ab-7cdf-4669-b0d4-e9371d76e623
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496371680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3496371680
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4176357941
Short name T473
Test name
Test status
Simulation time 88116516051 ps
CPU time 498.83 seconds
Started Jul 01 05:29:53 PM PDT 24
Finished Jul 01 05:38:13 PM PDT 24
Peak memory 202204 kb
Host smart-ecb02251-ab16-42cf-85b8-7e2bd3a8a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176357941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4176357941
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3693811216
Short name T416
Test name
Test status
Simulation time 23619946708 ps
CPU time 47.3 seconds
Started Jul 01 05:29:45 PM PDT 24
Finished Jul 01 05:30:35 PM PDT 24
Peak memory 201764 kb
Host smart-331627a0-9db7-4b10-9d69-798b557cd19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693811216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3693811216
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3416088564
Short name T411
Test name
Test status
Simulation time 3464793226 ps
CPU time 9.02 seconds
Started Jul 01 05:29:47 PM PDT 24
Finished Jul 01 05:29:58 PM PDT 24
Peak memory 201648 kb
Host smart-e60ea07d-03f2-49b9-b71d-bb85b97cd9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416088564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3416088564
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1996793171
Short name T696
Test name
Test status
Simulation time 5775107006 ps
CPU time 3.63 seconds
Started Jul 01 05:29:48 PM PDT 24
Finished Jul 01 05:29:53 PM PDT 24
Peak memory 201752 kb
Host smart-c36db3bd-c71b-4e09-b26e-8bc9bdb3feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996793171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1996793171
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3786554485
Short name T202
Test name
Test status
Simulation time 404287357274 ps
CPU time 1567.94 seconds
Started Jul 01 05:29:53 PM PDT 24
Finished Jul 01 05:56:02 PM PDT 24
Peak memory 218604 kb
Host smart-154b7428-f1b2-4c77-929a-e1ff8d4417c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786554485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3786554485
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.8443423
Short name T753
Test name
Test status
Simulation time 146722582820 ps
CPU time 212.33 seconds
Started Jul 01 05:29:52 PM PDT 24
Finished Jul 01 05:33:25 PM PDT 24
Peak memory 210524 kb
Host smart-48b15efe-06ce-4852-8db8-9da02ed381b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8443423 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.8443423
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.754996482
Short name T435
Test name
Test status
Simulation time 290587405 ps
CPU time 1.29 seconds
Started Jul 01 05:30:02 PM PDT 24
Finished Jul 01 05:30:04 PM PDT 24
Peak memory 201584 kb
Host smart-81ef19a7-8527-4929-9971-a36d48f93dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754996482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.754996482
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.140032992
Short name T313
Test name
Test status
Simulation time 375205843543 ps
CPU time 133.77 seconds
Started Jul 01 05:29:57 PM PDT 24
Finished Jul 01 05:32:12 PM PDT 24
Peak memory 201952 kb
Host smart-8ee802c7-82cd-43a6-8ed2-871ecd0a1194
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140032992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.140032992
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2246462745
Short name T188
Test name
Test status
Simulation time 327928283514 ps
CPU time 205 seconds
Started Jul 01 05:29:56 PM PDT 24
Finished Jul 01 05:33:22 PM PDT 24
Peak memory 201892 kb
Host smart-b3601fed-44fc-45a2-baca-0d9ec626b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246462745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2246462745
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4180827835
Short name T251
Test name
Test status
Simulation time 490882125196 ps
CPU time 533.64 seconds
Started Jul 01 05:30:01 PM PDT 24
Finished Jul 01 05:38:55 PM PDT 24
Peak memory 201988 kb
Host smart-b6a89d36-8f46-41fb-a69b-c7696b0ee184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180827835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4180827835
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3789459299
Short name T772
Test name
Test status
Simulation time 161419905792 ps
CPU time 66.41 seconds
Started Jul 01 05:29:57 PM PDT 24
Finished Jul 01 05:31:04 PM PDT 24
Peak memory 201856 kb
Host smart-f5735707-6c71-4508-9f37-5d6bc155b0cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789459299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3789459299
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1008770194
Short name T464
Test name
Test status
Simulation time 329027520989 ps
CPU time 457.72 seconds
Started Jul 01 05:29:57 PM PDT 24
Finished Jul 01 05:37:36 PM PDT 24
Peak memory 201996 kb
Host smart-fbce13fa-57c9-4b88-bd76-302919e23578
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008770194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1008770194
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2057439756
Short name T134
Test name
Test status
Simulation time 609312226431 ps
CPU time 486.44 seconds
Started Jul 01 05:30:01 PM PDT 24
Finished Jul 01 05:38:08 PM PDT 24
Peak memory 201992 kb
Host smart-1309cfcd-2bcc-4214-bbdc-c6bc21607d55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057439756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2057439756
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3488496805
Short name T725
Test name
Test status
Simulation time 206409021120 ps
CPU time 83.28 seconds
Started Jul 01 05:29:58 PM PDT 24
Finished Jul 01 05:31:22 PM PDT 24
Peak memory 201832 kb
Host smart-8524242d-c545-427c-91d2-33bb4476e5d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488496805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3488496805
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.275071574
Short name T6
Test name
Test status
Simulation time 124723585962 ps
CPU time 461.93 seconds
Started Jul 01 05:29:59 PM PDT 24
Finished Jul 01 05:37:42 PM PDT 24
Peak memory 202200 kb
Host smart-e8d100e5-48c7-4e78-8024-2f20dcf21907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275071574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.275071574
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1895860927
Short name T608
Test name
Test status
Simulation time 28294498941 ps
CPU time 30.84 seconds
Started Jul 01 05:29:59 PM PDT 24
Finished Jul 01 05:30:30 PM PDT 24
Peak memory 201680 kb
Host smart-92e8b87f-8187-4561-b8db-dd21a6f83ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895860927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1895860927
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2466424147
Short name T189
Test name
Test status
Simulation time 4569906606 ps
CPU time 5.27 seconds
Started Jul 01 05:30:01 PM PDT 24
Finished Jul 01 05:30:07 PM PDT 24
Peak memory 201772 kb
Host smart-194a4644-9cc0-4932-81fc-53c21dfcf50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466424147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2466424147
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2196991750
Short name T465
Test name
Test status
Simulation time 6018086106 ps
CPU time 2.08 seconds
Started Jul 01 05:29:52 PM PDT 24
Finished Jul 01 05:29:55 PM PDT 24
Peak memory 201608 kb
Host smart-ccf50ac4-acdf-42ea-bc5f-dfca0b686258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196991750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2196991750
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1862587006
Short name T223
Test name
Test status
Simulation time 438908158506 ps
CPU time 231.27 seconds
Started Jul 01 05:30:03 PM PDT 24
Finished Jul 01 05:33:55 PM PDT 24
Peak memory 201888 kb
Host smart-aae73d13-4e97-4904-8fc8-78a10d688849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862587006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1862587006
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3889478740
Short name T726
Test name
Test status
Simulation time 37884328769 ps
CPU time 41.66 seconds
Started Jul 01 05:30:02 PM PDT 24
Finished Jul 01 05:30:44 PM PDT 24
Peak memory 210172 kb
Host smart-3652db8d-eca1-4619-aea2-5b9a3544468f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889478740 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3889478740
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.4023976939
Short name T386
Test name
Test status
Simulation time 402331208 ps
CPU time 0.85 seconds
Started Jul 01 05:30:14 PM PDT 24
Finished Jul 01 05:30:16 PM PDT 24
Peak memory 201700 kb
Host smart-fc046cd3-70ec-49a9-bf7d-ddb57f50fc46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023976939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.4023976939
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.358404443
Short name T769
Test name
Test status
Simulation time 169966360796 ps
CPU time 100.43 seconds
Started Jul 01 05:30:09 PM PDT 24
Finished Jul 01 05:31:50 PM PDT 24
Peak memory 202000 kb
Host smart-9bd40369-8b13-4a04-8544-44b562787235
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358404443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.358404443
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2061406523
Short name T702
Test name
Test status
Simulation time 499865991576 ps
CPU time 607.14 seconds
Started Jul 01 05:30:12 PM PDT 24
Finished Jul 01 05:40:21 PM PDT 24
Peak memory 201932 kb
Host smart-7b46f37a-8519-43dc-a2e8-240a6dda82c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061406523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2061406523
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1744659398
Short name T666
Test name
Test status
Simulation time 493572838539 ps
CPU time 524.66 seconds
Started Jul 01 05:30:09 PM PDT 24
Finished Jul 01 05:38:54 PM PDT 24
Peak memory 201932 kb
Host smart-afdf413e-24b9-4922-9490-5302d9d1276a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744659398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1744659398
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.573779874
Short name T754
Test name
Test status
Simulation time 163361506838 ps
CPU time 38.77 seconds
Started Jul 01 05:30:10 PM PDT 24
Finished Jul 01 05:30:49 PM PDT 24
Peak memory 201864 kb
Host smart-0c05572c-905f-482b-8028-5865656d7c5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=573779874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.573779874
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1440570916
Short name T176
Test name
Test status
Simulation time 486307369355 ps
CPU time 299.5 seconds
Started Jul 01 05:30:03 PM PDT 24
Finished Jul 01 05:35:03 PM PDT 24
Peak memory 202012 kb
Host smart-dbf386c9-9454-4e38-ae1f-af0891873149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440570916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1440570916
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3745960099
Short name T729
Test name
Test status
Simulation time 489042215396 ps
CPU time 352.78 seconds
Started Jul 01 05:30:09 PM PDT 24
Finished Jul 01 05:36:03 PM PDT 24
Peak memory 201852 kb
Host smart-bd617dd2-b0ab-429d-bff7-c9060751f1e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745960099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3745960099
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4256476403
Short name T505
Test name
Test status
Simulation time 188836744574 ps
CPU time 216.61 seconds
Started Jul 01 05:30:12 PM PDT 24
Finished Jul 01 05:33:50 PM PDT 24
Peak memory 202004 kb
Host smart-a251940b-5ceb-4732-b83e-072fd0091ff8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256476403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4256476403
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.344615556
Short name T645
Test name
Test status
Simulation time 201658165370 ps
CPU time 402.12 seconds
Started Jul 01 05:30:08 PM PDT 24
Finished Jul 01 05:36:51 PM PDT 24
Peak memory 201872 kb
Host smart-2e4c1bd5-1aa3-4539-b8e5-7f47484fb0f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344615556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.344615556
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1667064320
Short name T759
Test name
Test status
Simulation time 30637196778 ps
CPU time 15.51 seconds
Started Jul 01 05:30:10 PM PDT 24
Finished Jul 01 05:30:26 PM PDT 24
Peak memory 201744 kb
Host smart-39d35aa6-96b5-42a3-8e4a-f9baaa847675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667064320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1667064320
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1603566993
Short name T377
Test name
Test status
Simulation time 4441368339 ps
CPU time 5.57 seconds
Started Jul 01 05:30:08 PM PDT 24
Finished Jul 01 05:30:15 PM PDT 24
Peak memory 201736 kb
Host smart-6331a35e-e26b-4345-acb1-4a0eac4515a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603566993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1603566993
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.888729111
Short name T738
Test name
Test status
Simulation time 5780607684 ps
CPU time 4.29 seconds
Started Jul 01 05:30:03 PM PDT 24
Finished Jul 01 05:30:08 PM PDT 24
Peak memory 201700 kb
Host smart-b0a7796a-7cfd-4189-984b-5e1bdad7ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888729111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.888729111
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4129039125
Short name T336
Test name
Test status
Simulation time 564385612050 ps
CPU time 1374.86 seconds
Started Jul 01 05:30:14 PM PDT 24
Finished Jul 01 05:53:10 PM PDT 24
Peak memory 201952 kb
Host smart-1ffc076d-4e23-4396-92e7-b65fd3557d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129039125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4129039125
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1453553156
Short name T199
Test name
Test status
Simulation time 286620460750 ps
CPU time 129.35 seconds
Started Jul 01 05:30:13 PM PDT 24
Finished Jul 01 05:32:24 PM PDT 24
Peak memory 210208 kb
Host smart-6c91eac8-3a1b-4017-bed0-97fbd812af26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453553156 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1453553156
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.282301410
Short name T523
Test name
Test status
Simulation time 514368902 ps
CPU time 0.91 seconds
Started Jul 01 05:30:29 PM PDT 24
Finished Jul 01 05:30:30 PM PDT 24
Peak memory 201632 kb
Host smart-a47c0fb9-185f-4643-bf21-fccda507a3d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282301410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.282301410
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.644408342
Short name T306
Test name
Test status
Simulation time 156119173389 ps
CPU time 71.3 seconds
Started Jul 01 05:30:20 PM PDT 24
Finished Jul 01 05:31:32 PM PDT 24
Peak memory 201872 kb
Host smart-10822eb2-a9c7-44d3-836a-7cf5afb8955e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644408342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.644408342
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3840103292
Short name T657
Test name
Test status
Simulation time 341280757387 ps
CPU time 727.95 seconds
Started Jul 01 05:30:20 PM PDT 24
Finished Jul 01 05:42:29 PM PDT 24
Peak memory 201876 kb
Host smart-aade8896-8922-4f56-b28d-6babb603300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840103292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3840103292
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2423465100
Short name T302
Test name
Test status
Simulation time 319465934892 ps
CPU time 787.63 seconds
Started Jul 01 05:30:14 PM PDT 24
Finished Jul 01 05:43:23 PM PDT 24
Peak memory 201884 kb
Host smart-e8a82371-ede0-4fa8-b1e9-1c593d992c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423465100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2423465100
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.173972991
Short name T647
Test name
Test status
Simulation time 160411197577 ps
CPU time 92.26 seconds
Started Jul 01 05:30:21 PM PDT 24
Finished Jul 01 05:31:54 PM PDT 24
Peak memory 201956 kb
Host smart-4b807dbf-e813-4c81-8cdd-0b04d7607bad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=173972991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.173972991
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3083387280
Short name T742
Test name
Test status
Simulation time 493398574912 ps
CPU time 555.59 seconds
Started Jul 01 05:30:12 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 201888 kb
Host smart-ba18c8ae-beed-4c44-b447-6c2a9af0fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083387280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3083387280
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1972694039
Short name T536
Test name
Test status
Simulation time 337166302644 ps
CPU time 203.1 seconds
Started Jul 01 05:30:14 PM PDT 24
Finished Jul 01 05:33:39 PM PDT 24
Peak memory 201940 kb
Host smart-b98f79a2-982d-464c-9235-c7c34b938ca0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972694039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1972694039
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1880583741
Short name T315
Test name
Test status
Simulation time 564700421669 ps
CPU time 649.7 seconds
Started Jul 01 05:30:21 PM PDT 24
Finished Jul 01 05:41:12 PM PDT 24
Peak memory 201932 kb
Host smart-a597b407-311c-4a36-9f08-0f54c42b52d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880583741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1880583741
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3377026091
Short name T686
Test name
Test status
Simulation time 398390287829 ps
CPU time 106.81 seconds
Started Jul 01 05:30:20 PM PDT 24
Finished Jul 01 05:32:07 PM PDT 24
Peak memory 201928 kb
Host smart-b52df791-456a-4259-9f63-1d2f8e3dd876
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377026091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3377026091
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2764638671
Short name T214
Test name
Test status
Simulation time 121211072247 ps
CPU time 577.58 seconds
Started Jul 01 05:30:20 PM PDT 24
Finished Jul 01 05:39:59 PM PDT 24
Peak memory 202188 kb
Host smart-803bbeba-3474-4626-8950-417dc42d5532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764638671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2764638671
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1193282077
Short name T537
Test name
Test status
Simulation time 26361655842 ps
CPU time 17.16 seconds
Started Jul 01 05:30:20 PM PDT 24
Finished Jul 01 05:30:38 PM PDT 24
Peak memory 201680 kb
Host smart-a4f12324-6f6c-4bfc-b003-1739a3ad1e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193282077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1193282077
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3622949029
Short name T534
Test name
Test status
Simulation time 4081451358 ps
CPU time 3.09 seconds
Started Jul 01 05:30:23 PM PDT 24
Finished Jul 01 05:30:27 PM PDT 24
Peak memory 201688 kb
Host smart-a7a65a2d-1901-4074-b10b-09e62bfe2214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622949029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3622949029
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2829257477
Short name T105
Test name
Test status
Simulation time 5990897095 ps
CPU time 13.63 seconds
Started Jul 01 05:30:15 PM PDT 24
Finished Jul 01 05:30:29 PM PDT 24
Peak memory 201748 kb
Host smart-df1d3674-df79-43f9-baab-4714f6c1304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829257477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2829257477
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.85838882
Short name T433
Test name
Test status
Simulation time 170158261773 ps
CPU time 104.31 seconds
Started Jul 01 05:30:25 PM PDT 24
Finished Jul 01 05:32:10 PM PDT 24
Peak memory 201940 kb
Host smart-4d78ecaf-541d-4f37-8f61-2f3527398800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85838882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.85838882
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3115344129
Short name T767
Test name
Test status
Simulation time 502912860 ps
CPU time 0.91 seconds
Started Jul 01 05:30:34 PM PDT 24
Finished Jul 01 05:30:36 PM PDT 24
Peak memory 201640 kb
Host smart-cee1734c-8fcd-4f05-8cfb-b074092b5fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115344129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3115344129
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.430707288
Short name T324
Test name
Test status
Simulation time 161390998524 ps
CPU time 29.99 seconds
Started Jul 01 05:30:25 PM PDT 24
Finished Jul 01 05:30:56 PM PDT 24
Peak memory 201944 kb
Host smart-34d39c23-6931-4bd7-89c7-2a71a410bf5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430707288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.430707288
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1548006679
Short name T295
Test name
Test status
Simulation time 163076015438 ps
CPU time 361.4 seconds
Started Jul 01 05:30:28 PM PDT 24
Finished Jul 01 05:36:31 PM PDT 24
Peak memory 201892 kb
Host smart-d15000e3-dfc1-49c3-a855-16f3b8c1359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548006679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1548006679
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.398707972
Short name T703
Test name
Test status
Simulation time 161840053516 ps
CPU time 197.51 seconds
Started Jul 01 05:30:26 PM PDT 24
Finished Jul 01 05:33:44 PM PDT 24
Peak memory 201876 kb
Host smart-80d1fa4f-0302-435c-9a3a-a74b4e3b426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398707972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.398707972
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3574613417
Short name T363
Test name
Test status
Simulation time 492415320384 ps
CPU time 583.92 seconds
Started Jul 01 05:30:26 PM PDT 24
Finished Jul 01 05:40:11 PM PDT 24
Peak memory 201860 kb
Host smart-9922576e-d246-4467-9354-80b62377c676
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574613417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3574613417
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1414249398
Short name T193
Test name
Test status
Simulation time 163208237223 ps
CPU time 60.26 seconds
Started Jul 01 05:30:27 PM PDT 24
Finished Jul 01 05:31:28 PM PDT 24
Peak memory 201908 kb
Host smart-d1f2cde9-f090-42ba-9eca-2e21ea2054dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414249398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1414249398
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4155201688
Short name T511
Test name
Test status
Simulation time 577569894736 ps
CPU time 1308.59 seconds
Started Jul 01 05:30:26 PM PDT 24
Finished Jul 01 05:52:16 PM PDT 24
Peak memory 201912 kb
Host smart-7e74a4b3-3007-4d7e-840b-488ea354d348
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155201688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4155201688
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1173694358
Short name T362
Test name
Test status
Simulation time 387493775779 ps
CPU time 890.64 seconds
Started Jul 01 05:30:26 PM PDT 24
Finished Jul 01 05:45:18 PM PDT 24
Peak memory 201932 kb
Host smart-5ee2f6bc-59b6-40d3-a1bd-bcc0c0ea9513
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173694358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1173694358
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2377426193
Short name T345
Test name
Test status
Simulation time 117712644598 ps
CPU time 627.11 seconds
Started Jul 01 05:30:35 PM PDT 24
Finished Jul 01 05:41:03 PM PDT 24
Peak memory 202280 kb
Host smart-bc32bf2e-7372-4aa6-a2a2-546ec6668797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377426193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2377426193
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.341930821
Short name T629
Test name
Test status
Simulation time 31873872194 ps
CPU time 75.01 seconds
Started Jul 01 05:30:35 PM PDT 24
Finished Jul 01 05:31:51 PM PDT 24
Peak memory 201748 kb
Host smart-5c782b28-531a-43f0-a839-a958b3bb558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341930821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.341930821
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3470596144
Short name T378
Test name
Test status
Simulation time 5260058845 ps
CPU time 13.09 seconds
Started Jul 01 05:30:30 PM PDT 24
Finished Jul 01 05:30:43 PM PDT 24
Peak memory 201688 kb
Host smart-de0133af-6e9b-4571-bec6-39282aae51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470596144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3470596144
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1963829554
Short name T7
Test name
Test status
Simulation time 5723925364 ps
CPU time 7.74 seconds
Started Jul 01 05:30:26 PM PDT 24
Finished Jul 01 05:30:34 PM PDT 24
Peak memory 201680 kb
Host smart-f7e775cd-4582-4970-9aeb-8399f0c37b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963829554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1963829554
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1164595442
Short name T558
Test name
Test status
Simulation time 205723591188 ps
CPU time 476 seconds
Started Jul 01 05:30:35 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 201928 kb
Host smart-ad848ea2-ce57-43ec-a40e-654774076460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164595442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1164595442
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1883154108
Short name T39
Test name
Test status
Simulation time 12948817716 ps
CPU time 29.17 seconds
Started Jul 01 05:30:35 PM PDT 24
Finished Jul 01 05:31:06 PM PDT 24
Peak memory 202080 kb
Host smart-e7f0520f-7e76-4f14-b99e-8342a22f2030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883154108 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1883154108
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2478824263
Short name T383
Test name
Test status
Simulation time 450003049 ps
CPU time 0.9 seconds
Started Jul 01 05:30:46 PM PDT 24
Finished Jul 01 05:30:48 PM PDT 24
Peak memory 201632 kb
Host smart-06df3276-eb3b-416f-b5ed-06cef0acc951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478824263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2478824263
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4191584388
Short name T182
Test name
Test status
Simulation time 493311417242 ps
CPU time 74.23 seconds
Started Jul 01 05:30:33 PM PDT 24
Finished Jul 01 05:31:48 PM PDT 24
Peak memory 201924 kb
Host smart-7985ab51-cb3b-4bde-94ab-95c236283785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191584388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4191584388
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1102495489
Short name T712
Test name
Test status
Simulation time 482837930483 ps
CPU time 1172.52 seconds
Started Jul 01 05:30:40 PM PDT 24
Finished Jul 01 05:50:13 PM PDT 24
Peak memory 201768 kb
Host smart-1bfe6336-a087-42d1-93ff-efa40de4bebf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102495489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1102495489
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1023374371
Short name T794
Test name
Test status
Simulation time 161249356308 ps
CPU time 352.07 seconds
Started Jul 01 05:30:33 PM PDT 24
Finished Jul 01 05:36:26 PM PDT 24
Peak memory 201960 kb
Host smart-185bbb2e-d7cf-4c33-850c-08691befe481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023374371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1023374371
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3717205690
Short name T562
Test name
Test status
Simulation time 322041579239 ps
CPU time 96.62 seconds
Started Jul 01 05:30:34 PM PDT 24
Finished Jul 01 05:32:12 PM PDT 24
Peak memory 201780 kb
Host smart-20a85cb5-2e7c-4c9a-8784-4c02e35f495b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717205690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3717205690
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2133562807
Short name T446
Test name
Test status
Simulation time 368310783682 ps
CPU time 82.09 seconds
Started Jul 01 05:30:46 PM PDT 24
Finished Jul 01 05:32:09 PM PDT 24
Peak memory 201668 kb
Host smart-664ae8fd-3e0a-41ca-958a-e039d0556fba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133562807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2133562807
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.666640591
Short name T486
Test name
Test status
Simulation time 208252541672 ps
CPU time 126.33 seconds
Started Jul 01 05:30:40 PM PDT 24
Finished Jul 01 05:32:47 PM PDT 24
Peak memory 201876 kb
Host smart-653d5ea5-cc31-436b-884e-0661d58cdd1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666640591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.666640591
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.426864238
Short name T426
Test name
Test status
Simulation time 112917744926 ps
CPU time 497.31 seconds
Started Jul 01 05:30:45 PM PDT 24
Finished Jul 01 05:39:03 PM PDT 24
Peak memory 202228 kb
Host smart-d7865ab6-f08e-4ed1-9096-e46638d1467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426864238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.426864238
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1606070420
Short name T384
Test name
Test status
Simulation time 41460036307 ps
CPU time 90.44 seconds
Started Jul 01 05:30:48 PM PDT 24
Finished Jul 01 05:32:19 PM PDT 24
Peak memory 201640 kb
Host smart-66bc1421-df45-4896-9e61-4bc1e9095ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606070420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1606070420
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.476075219
Short name T597
Test name
Test status
Simulation time 4017742795 ps
CPU time 2.55 seconds
Started Jul 01 05:30:46 PM PDT 24
Finished Jul 01 05:30:49 PM PDT 24
Peak memory 201460 kb
Host smart-03e85a83-0e82-4448-b2dc-55b72f9a809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476075219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.476075219
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.704062038
Short name T417
Test name
Test status
Simulation time 5901387187 ps
CPU time 13.78 seconds
Started Jul 01 05:30:36 PM PDT 24
Finished Jul 01 05:30:51 PM PDT 24
Peak memory 201672 kb
Host smart-4e63305d-ed78-4f6d-8939-506074987689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704062038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.704062038
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1718623342
Short name T239
Test name
Test status
Simulation time 557264339436 ps
CPU time 349.08 seconds
Started Jul 01 05:30:48 PM PDT 24
Finished Jul 01 05:36:38 PM PDT 24
Peak memory 201828 kb
Host smart-71975b35-7936-44a8-b2e7-8e3e88815a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718623342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1718623342
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.942661244
Short name T17
Test name
Test status
Simulation time 30880722081 ps
CPU time 77.07 seconds
Started Jul 01 05:30:45 PM PDT 24
Finished Jul 01 05:32:03 PM PDT 24
Peak memory 210648 kb
Host smart-c2908da8-2595-47b2-a2e2-684582d44fd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942661244 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.942661244
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3543875174
Short name T454
Test name
Test status
Simulation time 345667445 ps
CPU time 1.46 seconds
Started Jul 01 05:31:04 PM PDT 24
Finished Jul 01 05:31:06 PM PDT 24
Peak memory 201632 kb
Host smart-71773605-c43c-4fca-8864-426b8616c790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543875174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3543875174
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2088614035
Short name T450
Test name
Test status
Simulation time 270126351901 ps
CPU time 119.21 seconds
Started Jul 01 05:30:53 PM PDT 24
Finished Jul 01 05:32:53 PM PDT 24
Peak memory 201940 kb
Host smart-9d755f0b-e376-4238-847e-e29baaf073d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088614035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2088614035
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1838239503
Short name T747
Test name
Test status
Simulation time 493896973092 ps
CPU time 175.19 seconds
Started Jul 01 05:30:52 PM PDT 24
Finished Jul 01 05:33:48 PM PDT 24
Peak memory 201772 kb
Host smart-f1f3014c-3cd0-4828-857b-130d2b620dd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838239503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1838239503
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3990481022
Short name T595
Test name
Test status
Simulation time 495785830586 ps
CPU time 298.77 seconds
Started Jul 01 05:30:45 PM PDT 24
Finished Jul 01 05:35:44 PM PDT 24
Peak memory 201904 kb
Host smart-9fcc3d1c-b5fc-4d14-ab13-5b123018f468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990481022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3990481022
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1018050277
Short name T736
Test name
Test status
Simulation time 335936832190 ps
CPU time 183.76 seconds
Started Jul 01 05:30:44 PM PDT 24
Finished Jul 01 05:33:49 PM PDT 24
Peak memory 201888 kb
Host smart-38759c51-b20f-48ba-9211-4d7327d2d560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018050277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1018050277
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1872562436
Short name T249
Test name
Test status
Simulation time 524937804496 ps
CPU time 596.27 seconds
Started Jul 01 05:30:51 PM PDT 24
Finished Jul 01 05:40:49 PM PDT 24
Peak memory 202000 kb
Host smart-c243b88b-0012-4f06-ab32-72a38651c609
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872562436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1872562436
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2296000671
Short name T25
Test name
Test status
Simulation time 409472687463 ps
CPU time 834.69 seconds
Started Jul 01 05:30:51 PM PDT 24
Finished Jul 01 05:44:46 PM PDT 24
Peak memory 201932 kb
Host smart-77e0b55a-5c0c-4da8-94b5-0be0aa16b927
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296000671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2296000671
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2595671195
Short name T103
Test name
Test status
Simulation time 116791953954 ps
CPU time 586.49 seconds
Started Jul 01 05:30:57 PM PDT 24
Finished Jul 01 05:40:44 PM PDT 24
Peak memory 202148 kb
Host smart-13dfa696-2c3a-4562-b9b1-e6402b82ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595671195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2595671195
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1701380406
Short name T409
Test name
Test status
Simulation time 35937496889 ps
CPU time 20.47 seconds
Started Jul 01 05:30:51 PM PDT 24
Finished Jul 01 05:31:12 PM PDT 24
Peak memory 201668 kb
Host smart-1a7fc2b0-b257-4154-9f73-8dd0c579b821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701380406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1701380406
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.391656017
Short name T606
Test name
Test status
Simulation time 5298231990 ps
CPU time 12.01 seconds
Started Jul 01 05:30:50 PM PDT 24
Finished Jul 01 05:31:02 PM PDT 24
Peak memory 201764 kb
Host smart-92d2aef3-8be4-4ea0-a86e-eec2ad916a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391656017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.391656017
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1448175533
Short name T499
Test name
Test status
Simulation time 5891379849 ps
CPU time 13.94 seconds
Started Jul 01 05:30:45 PM PDT 24
Finished Jul 01 05:31:00 PM PDT 24
Peak memory 201784 kb
Host smart-fe8f6f30-7ddc-4011-882d-edba8a95e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448175533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1448175533
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.779141176
Short name T763
Test name
Test status
Simulation time 103373242326 ps
CPU time 435.61 seconds
Started Jul 01 05:30:56 PM PDT 24
Finished Jul 01 05:38:13 PM PDT 24
Peak memory 211600 kb
Host smart-27f8078f-d360-4582-8ac1-b40d86d8630c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779141176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
779141176
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1401278700
Short name T33
Test name
Test status
Simulation time 48729151645 ps
CPU time 76.48 seconds
Started Jul 01 05:30:57 PM PDT 24
Finished Jul 01 05:32:14 PM PDT 24
Peak memory 210272 kb
Host smart-0067b696-a3b9-4c07-a575-6da56b002d54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401278700 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1401278700
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1563409966
Short name T503
Test name
Test status
Simulation time 314658994 ps
CPU time 0.83 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:28:00 PM PDT 24
Peak memory 201580 kb
Host smart-bdae88e9-e1e4-4ca4-84ea-6cbe5bc5cf0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563409966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1563409966
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3609166845
Short name T298
Test name
Test status
Simulation time 503267628083 ps
CPU time 156.83 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:30:36 PM PDT 24
Peak memory 201900 kb
Host smart-6d3579cc-509a-44cf-b0bc-1b3ec5e788c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609166845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3609166845
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1100563501
Short name T578
Test name
Test status
Simulation time 347949770650 ps
CPU time 183.78 seconds
Started Jul 01 05:27:58 PM PDT 24
Finished Jul 01 05:31:03 PM PDT 24
Peak memory 201896 kb
Host smart-6a1ec871-b828-4239-bf46-0a9f3c4b30b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100563501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1100563501
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2167671437
Short name T672
Test name
Test status
Simulation time 487823514121 ps
CPU time 1170.07 seconds
Started Jul 01 05:27:50 PM PDT 24
Finished Jul 01 05:47:21 PM PDT 24
Peak memory 201880 kb
Host smart-4bc7b889-de01-4811-a418-bab83a55a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167671437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2167671437
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.763875136
Short name T793
Test name
Test status
Simulation time 168525410617 ps
CPU time 370.74 seconds
Started Jul 01 05:27:52 PM PDT 24
Finished Jul 01 05:34:04 PM PDT 24
Peak memory 201780 kb
Host smart-4c02de62-65c6-4bf2-ac18-9aa32efc65c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=763875136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.763875136
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3432884763
Short name T419
Test name
Test status
Simulation time 322524149246 ps
CPU time 692.61 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:39:31 PM PDT 24
Peak memory 201964 kb
Host smart-adc93643-57b9-41ed-ba05-e40263a53e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432884763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3432884763
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2109402113
Short name T180
Test name
Test status
Simulation time 163476792007 ps
CPU time 103.58 seconds
Started Jul 01 05:27:52 PM PDT 24
Finished Jul 01 05:29:37 PM PDT 24
Peak memory 201940 kb
Host smart-908f859c-14a5-49ed-a23f-f57a99c8f9bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109402113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2109402113
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.318824885
Short name T746
Test name
Test status
Simulation time 604248973687 ps
CPU time 1239.25 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:48:38 PM PDT 24
Peak memory 201864 kb
Host smart-1529440c-f375-44d5-a547-ad827555f5b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318824885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.318824885
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.758903878
Short name T421
Test name
Test status
Simulation time 47815227376 ps
CPU time 28.3 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:28:27 PM PDT 24
Peak memory 201680 kb
Host smart-92c50569-ded3-43b8-88fc-11a1881a82e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758903878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.758903878
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1538888298
Short name T472
Test name
Test status
Simulation time 5210237109 ps
CPU time 12.17 seconds
Started Jul 01 05:27:55 PM PDT 24
Finished Jul 01 05:28:08 PM PDT 24
Peak memory 201676 kb
Host smart-0bc7038d-8fac-4bdd-a091-e885973874d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538888298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1538888298
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1435669319
Short name T75
Test name
Test status
Simulation time 7866886470 ps
CPU time 5.22 seconds
Started Jul 01 05:27:58 PM PDT 24
Finished Jul 01 05:28:05 PM PDT 24
Peak memory 218184 kb
Host smart-74024df0-3c4c-4cd7-8c7f-04d7d09c3883
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435669319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1435669319
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3486954060
Short name T751
Test name
Test status
Simulation time 5586847696 ps
CPU time 7.02 seconds
Started Jul 01 05:27:52 PM PDT 24
Finished Jul 01 05:28:00 PM PDT 24
Peak memory 201780 kb
Host smart-d8a50a2b-4ca1-4d4e-a677-d0b532604d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486954060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3486954060
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1421430915
Short name T796
Test name
Test status
Simulation time 515922114020 ps
CPU time 435.23 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:35:14 PM PDT 24
Peak memory 201964 kb
Host smart-b0e13d3b-10bc-4753-9226-c390ec98151c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421430915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1421430915
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.104333896
Short name T19
Test name
Test status
Simulation time 52084975854 ps
CPU time 126.3 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:30:03 PM PDT 24
Peak memory 210212 kb
Host smart-c65121eb-3d08-4e2d-a816-c593f970d68c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104333896 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.104333896
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2756223112
Short name T671
Test name
Test status
Simulation time 443367284 ps
CPU time 0.97 seconds
Started Jul 01 05:31:17 PM PDT 24
Finished Jul 01 05:31:19 PM PDT 24
Peak memory 201700 kb
Host smart-98875ad3-72dc-43be-ba5e-d8112086fc61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756223112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2756223112
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.298461028
Short name T509
Test name
Test status
Simulation time 328135163609 ps
CPU time 330.83 seconds
Started Jul 01 05:31:12 PM PDT 24
Finished Jul 01 05:36:44 PM PDT 24
Peak memory 201932 kb
Host smart-a9fc7944-22f0-40a5-a911-e4e75912def0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298461028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.298461028
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.291029584
Short name T462
Test name
Test status
Simulation time 168339448660 ps
CPU time 44.94 seconds
Started Jul 01 05:31:06 PM PDT 24
Finished Jul 01 05:31:51 PM PDT 24
Peak memory 201880 kb
Host smart-c0aa9bd8-e48e-4154-8fd0-06152f4c4e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291029584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.291029584
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2221850439
Short name T555
Test name
Test status
Simulation time 325302949165 ps
CPU time 199.75 seconds
Started Jul 01 05:31:03 PM PDT 24
Finished Jul 01 05:34:23 PM PDT 24
Peak memory 201860 kb
Host smart-2240e34d-9231-40f4-81a2-3a7efc59ee4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221850439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2221850439
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3507328247
Short name T577
Test name
Test status
Simulation time 334076484334 ps
CPU time 188 seconds
Started Jul 01 05:31:03 PM PDT 24
Finished Jul 01 05:34:12 PM PDT 24
Peak memory 201884 kb
Host smart-4ec66253-b5a8-460a-a01d-bf9d6e0a4720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507328247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3507328247
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2894070250
Short name T714
Test name
Test status
Simulation time 490785687217 ps
CPU time 1006.56 seconds
Started Jul 01 05:31:04 PM PDT 24
Finished Jul 01 05:47:51 PM PDT 24
Peak memory 201856 kb
Host smart-e03bbc4a-3e12-4537-8026-45e46877b0b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894070250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2894070250
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3194081645
Short name T585
Test name
Test status
Simulation time 198238574155 ps
CPU time 209.29 seconds
Started Jul 01 05:31:13 PM PDT 24
Finished Jul 01 05:34:43 PM PDT 24
Peak memory 201872 kb
Host smart-606e5298-4c49-47b1-b055-ba187fc72b3b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194081645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3194081645
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.4018176688
Short name T619
Test name
Test status
Simulation time 85486092011 ps
CPU time 296.59 seconds
Started Jul 01 05:31:13 PM PDT 24
Finished Jul 01 05:36:10 PM PDT 24
Peak memory 202244 kb
Host smart-ef425bb1-b123-4f2c-b5b9-e0ba34332daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018176688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.4018176688
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2050481733
Short name T166
Test name
Test status
Simulation time 29779918315 ps
CPU time 34.4 seconds
Started Jul 01 05:31:11 PM PDT 24
Finished Jul 01 05:31:46 PM PDT 24
Peak memory 201756 kb
Host smart-bf75c058-3a70-4452-81a8-07212a815291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050481733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2050481733
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3946464987
Short name T494
Test name
Test status
Simulation time 3821600195 ps
CPU time 8.9 seconds
Started Jul 01 05:31:10 PM PDT 24
Finished Jul 01 05:31:20 PM PDT 24
Peak memory 201736 kb
Host smart-759a264e-5acc-4f56-aae1-53fbc7db7bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946464987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3946464987
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1856628038
Short name T350
Test name
Test status
Simulation time 5871893271 ps
CPU time 4.06 seconds
Started Jul 01 05:31:04 PM PDT 24
Finished Jul 01 05:31:09 PM PDT 24
Peak memory 201744 kb
Host smart-ff7ed55b-7456-4af3-8db4-8d29a458743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856628038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1856628038
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1274222474
Short name T789
Test name
Test status
Simulation time 519310493751 ps
CPU time 834.48 seconds
Started Jul 01 05:31:12 PM PDT 24
Finished Jul 01 05:45:08 PM PDT 24
Peak memory 212944 kb
Host smart-a9cf0b2d-b433-451d-bfb6-b117f84ab6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274222474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1274222474
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3306565330
Short name T361
Test name
Test status
Simulation time 317233984 ps
CPU time 1.35 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:31:27 PM PDT 24
Peak memory 201636 kb
Host smart-e7cb97ff-0c41-4b24-952b-90da919ba735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306565330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3306565330
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.851905206
Short name T161
Test name
Test status
Simulation time 165745403400 ps
CPU time 222.28 seconds
Started Jul 01 05:31:26 PM PDT 24
Finished Jul 01 05:35:09 PM PDT 24
Peak memory 201860 kb
Host smart-29133811-5501-4e92-8042-9c011d9f41f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=851905206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.851905206
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1771364307
Short name T478
Test name
Test status
Simulation time 160814223268 ps
CPU time 97.36 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:33:04 PM PDT 24
Peak memory 201896 kb
Host smart-bb275ef0-cc38-4756-987b-ab98d2282506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771364307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1771364307
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1890648112
Short name T658
Test name
Test status
Simulation time 501279761730 ps
CPU time 185.07 seconds
Started Jul 01 05:31:17 PM PDT 24
Finished Jul 01 05:34:23 PM PDT 24
Peak memory 201932 kb
Host smart-9b69749a-5ac2-437a-9146-c7a263817553
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890648112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1890648112
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1938504196
Short name T557
Test name
Test status
Simulation time 590610375569 ps
CPU time 287.77 seconds
Started Jul 01 05:31:16 PM PDT 24
Finished Jul 01 05:36:05 PM PDT 24
Peak memory 201932 kb
Host smart-70ab1fbb-2148-493d-bfb2-27840133bfe3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938504196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1938504196
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3281628458
Short name T211
Test name
Test status
Simulation time 106932286263 ps
CPU time 405.06 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:38:11 PM PDT 24
Peak memory 202208 kb
Host smart-4bb8474b-97b1-48e2-b8d5-db0d002dec5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281628458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3281628458
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.405106496
Short name T560
Test name
Test status
Simulation time 34123283036 ps
CPU time 69.48 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:32:36 PM PDT 24
Peak memory 201684 kb
Host smart-91672e9d-0bca-45a6-a8d8-66ce71dd5d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405106496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.405106496
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1868364727
Short name T366
Test name
Test status
Simulation time 4628174147 ps
CPU time 5.45 seconds
Started Jul 01 05:31:18 PM PDT 24
Finished Jul 01 05:31:24 PM PDT 24
Peak memory 201760 kb
Host smart-77478a34-641d-4794-a617-f055530383ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868364727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1868364727
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3187053569
Short name T584
Test name
Test status
Simulation time 5648622366 ps
CPU time 3.39 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:31:29 PM PDT 24
Peak memory 201684 kb
Host smart-81845cf7-ff74-4503-af84-f01ba1397c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187053569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3187053569
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.390463188
Short name T56
Test name
Test status
Simulation time 465010331578 ps
CPU time 190.94 seconds
Started Jul 01 05:31:26 PM PDT 24
Finished Jul 01 05:34:38 PM PDT 24
Peak memory 210168 kb
Host smart-23946a0b-153a-4a72-9343-2a9be3cb7219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390463188 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.390463188
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2797141364
Short name T541
Test name
Test status
Simulation time 286595706 ps
CPU time 1.07 seconds
Started Jul 01 05:31:31 PM PDT 24
Finished Jul 01 05:31:32 PM PDT 24
Peak memory 201680 kb
Host smart-0fb58cad-9073-489d-947d-8ed66048dbaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797141364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2797141364
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3306824874
Short name T168
Test name
Test status
Simulation time 172698440426 ps
CPU time 94.72 seconds
Started Jul 01 05:31:34 PM PDT 24
Finished Jul 01 05:33:09 PM PDT 24
Peak memory 201876 kb
Host smart-a526de86-8d17-4305-8e1e-cf5616472bcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306824874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3306824874
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2640027723
Short name T227
Test name
Test status
Simulation time 346140795010 ps
CPU time 786.02 seconds
Started Jul 01 05:31:32 PM PDT 24
Finished Jul 01 05:44:38 PM PDT 24
Peak memory 201812 kb
Host smart-534048ac-b572-413c-8c22-669b9b9664ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640027723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2640027723
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1210526109
Short name T183
Test name
Test status
Simulation time 327465819037 ps
CPU time 154.68 seconds
Started Jul 01 05:31:26 PM PDT 24
Finished Jul 01 05:34:01 PM PDT 24
Peak memory 202008 kb
Host smart-c47788f5-d245-490a-b8cf-07eff23985e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210526109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1210526109
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2488648645
Short name T549
Test name
Test status
Simulation time 498374035879 ps
CPU time 513.69 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:40:00 PM PDT 24
Peak memory 201844 kb
Host smart-885897bc-837a-44b3-ac94-29912474c24c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488648645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2488648645
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.510286889
Short name T644
Test name
Test status
Simulation time 493616610979 ps
CPU time 450.87 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:38:57 PM PDT 24
Peak memory 201972 kb
Host smart-e5b40a53-f2a4-432f-95b5-f34341daea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510286889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.510286889
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1226566969
Short name T495
Test name
Test status
Simulation time 324066087087 ps
CPU time 209.03 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:34:54 PM PDT 24
Peak memory 201912 kb
Host smart-3c7d8676-0a61-48e6-b979-7497b35dbcd8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226566969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1226566969
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.265602914
Short name T245
Test name
Test status
Simulation time 353207010839 ps
CPU time 772.59 seconds
Started Jul 01 05:31:34 PM PDT 24
Finished Jul 01 05:44:27 PM PDT 24
Peak memory 201952 kb
Host smart-e462cc9f-917d-4b20-84ec-a75d87b582ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265602914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.265602914
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2665094496
Short name T437
Test name
Test status
Simulation time 192315409481 ps
CPU time 114.89 seconds
Started Jul 01 05:31:35 PM PDT 24
Finished Jul 01 05:33:30 PM PDT 24
Peak memory 201848 kb
Host smart-6217e4b8-1cf4-4435-9ced-d50ac0673eed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665094496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2665094496
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4134009104
Short name T574
Test name
Test status
Simulation time 40826175867 ps
CPU time 96.8 seconds
Started Jul 01 05:31:31 PM PDT 24
Finished Jul 01 05:33:08 PM PDT 24
Peak memory 201684 kb
Host smart-af76724d-59d8-4337-b859-77bb40243e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134009104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4134009104
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1468694629
Short name T171
Test name
Test status
Simulation time 4854074265 ps
CPU time 2.57 seconds
Started Jul 01 05:31:30 PM PDT 24
Finished Jul 01 05:31:33 PM PDT 24
Peak memory 201672 kb
Host smart-466a4d75-1ba4-4d8e-bc1e-285b4794f630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468694629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1468694629
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.328547898
Short name T475
Test name
Test status
Simulation time 5767547745 ps
CPU time 7.18 seconds
Started Jul 01 05:31:25 PM PDT 24
Finished Jul 01 05:31:34 PM PDT 24
Peak memory 201880 kb
Host smart-be56ce3e-290e-4f75-8343-bf7c52ac1da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328547898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.328547898
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1417082085
Short name T287
Test name
Test status
Simulation time 170747790014 ps
CPU time 214.8 seconds
Started Jul 01 05:31:32 PM PDT 24
Finished Jul 01 05:35:08 PM PDT 24
Peak memory 201780 kb
Host smart-454c2b02-ac6d-462d-bd27-4c0d05118b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417082085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1417082085
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3015101322
Short name T582
Test name
Test status
Simulation time 159147568951 ps
CPU time 62.46 seconds
Started Jul 01 05:31:32 PM PDT 24
Finished Jul 01 05:32:35 PM PDT 24
Peak memory 210296 kb
Host smart-9406380d-eb43-47c2-8670-2410b5c9cc24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015101322 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3015101322
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1028830474
Short name T677
Test name
Test status
Simulation time 318475928 ps
CPU time 1.42 seconds
Started Jul 01 05:31:46 PM PDT 24
Finished Jul 01 05:31:48 PM PDT 24
Peak memory 201688 kb
Host smart-d01e8626-c747-4527-b64d-8061e321b0ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028830474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1028830474
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1129319943
Short name T274
Test name
Test status
Simulation time 389012306449 ps
CPU time 929.53 seconds
Started Jul 01 05:31:40 PM PDT 24
Finished Jul 01 05:47:10 PM PDT 24
Peak memory 202040 kb
Host smart-cd976d88-10ca-44e7-a695-5aedf3082242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129319943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1129319943
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2936365684
Short name T156
Test name
Test status
Simulation time 168878872803 ps
CPU time 210.08 seconds
Started Jul 01 05:31:39 PM PDT 24
Finished Jul 01 05:35:10 PM PDT 24
Peak memory 201960 kb
Host smart-c118cb4e-4fe8-40d9-b745-c23d26b4a377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936365684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2936365684
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.110028745
Short name T685
Test name
Test status
Simulation time 168058949971 ps
CPU time 27.12 seconds
Started Jul 01 05:31:39 PM PDT 24
Finished Jul 01 05:32:07 PM PDT 24
Peak memory 201912 kb
Host smart-a4bff849-9ccb-42c4-8677-3a350f14eeb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=110028745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.110028745
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3903750976
Short name T264
Test name
Test status
Simulation time 482967598740 ps
CPU time 994.13 seconds
Started Jul 01 05:31:39 PM PDT 24
Finished Jul 01 05:48:14 PM PDT 24
Peak memory 201932 kb
Host smart-32aedcc9-d74b-40d3-b1c8-9f809d6e8c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903750976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3903750976
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2684594082
Short name T379
Test name
Test status
Simulation time 480288187007 ps
CPU time 243.49 seconds
Started Jul 01 05:31:40 PM PDT 24
Finished Jul 01 05:35:44 PM PDT 24
Peak memory 201600 kb
Host smart-2b41d709-7be1-4aea-87a9-da071b230d51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684594082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2684594082
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2191644365
Short name T652
Test name
Test status
Simulation time 568173445201 ps
CPU time 209.93 seconds
Started Jul 01 05:31:38 PM PDT 24
Finished Jul 01 05:35:09 PM PDT 24
Peak memory 201956 kb
Host smart-165a61e9-12e2-4e6c-80f8-11ca019760ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191644365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2191644365
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3910361401
Short name T402
Test name
Test status
Simulation time 198276939457 ps
CPU time 468.51 seconds
Started Jul 01 05:31:38 PM PDT 24
Finished Jul 01 05:39:27 PM PDT 24
Peak memory 201952 kb
Host smart-b5b0e313-3273-46d2-945d-be4a2e3e705b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910361401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3910361401
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3305670586
Short name T344
Test name
Test status
Simulation time 116452518250 ps
CPU time 373.65 seconds
Started Jul 01 05:31:39 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 202196 kb
Host smart-38befc65-d08e-4e30-929b-44be3e1d741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305670586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3305670586
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2502346868
Short name T346
Test name
Test status
Simulation time 22976064308 ps
CPU time 14.51 seconds
Started Jul 01 05:31:40 PM PDT 24
Finished Jul 01 05:31:55 PM PDT 24
Peak memory 201788 kb
Host smart-d8f2eb7d-8329-499d-b0ac-241e1746bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502346868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2502346868
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3133211125
Short name T512
Test name
Test status
Simulation time 4565908226 ps
CPU time 2.25 seconds
Started Jul 01 05:31:40 PM PDT 24
Finished Jul 01 05:31:43 PM PDT 24
Peak memory 201764 kb
Host smart-3a0cf522-8f69-4e70-99f5-f78c868691bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133211125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3133211125
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3389102033
Short name T353
Test name
Test status
Simulation time 5643859577 ps
CPU time 14.04 seconds
Started Jul 01 05:31:40 PM PDT 24
Finished Jul 01 05:31:55 PM PDT 24
Peak memory 201444 kb
Host smart-780f0a86-bf17-4859-b8db-8c08b5ced6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389102033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3389102033
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3110182686
Short name T277
Test name
Test status
Simulation time 371926395615 ps
CPU time 858.61 seconds
Started Jul 01 05:31:44 PM PDT 24
Finished Jul 01 05:46:04 PM PDT 24
Peak memory 201872 kb
Host smart-e19d1bd7-14e3-4c75-9965-996511e7e37e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110182686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3110182686
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1441179454
Short name T319
Test name
Test status
Simulation time 19150215861 ps
CPU time 47.37 seconds
Started Jul 01 05:31:39 PM PDT 24
Finished Jul 01 05:32:27 PM PDT 24
Peak memory 210580 kb
Host smart-5f6f720e-2132-4ed4-8142-842b397e1ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441179454 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1441179454
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1958759250
Short name T422
Test name
Test status
Simulation time 385782899 ps
CPU time 0.83 seconds
Started Jul 01 05:31:58 PM PDT 24
Finished Jul 01 05:31:59 PM PDT 24
Peak memory 201616 kb
Host smart-f7aaa3be-5548-40cc-abd1-1100db31987f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958759250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1958759250
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2431402694
Short name T254
Test name
Test status
Simulation time 496126870135 ps
CPU time 623.19 seconds
Started Jul 01 05:31:53 PM PDT 24
Finished Jul 01 05:42:17 PM PDT 24
Peak memory 201860 kb
Host smart-7de6c1d0-ff84-4ec0-8d8d-b01a1456fab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431402694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2431402694
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.692915527
Short name T141
Test name
Test status
Simulation time 324027639533 ps
CPU time 744.96 seconds
Started Jul 01 05:31:51 PM PDT 24
Finished Jul 01 05:44:16 PM PDT 24
Peak memory 201864 kb
Host smart-ad012609-ccc6-4e00-ac4d-0143cf225d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692915527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.692915527
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.50724061
Short name T372
Test name
Test status
Simulation time 163534702025 ps
CPU time 134.71 seconds
Started Jul 01 05:31:46 PM PDT 24
Finished Jul 01 05:34:01 PM PDT 24
Peak memory 201852 kb
Host smart-fa2a8c54-018d-49db-b8e2-3f796719fa37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=50724061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt
_fixed.50724061
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.789603810
Short name T142
Test name
Test status
Simulation time 164804860761 ps
CPU time 184.33 seconds
Started Jul 01 05:31:46 PM PDT 24
Finished Jul 01 05:34:51 PM PDT 24
Peak memory 201940 kb
Host smart-764c349e-c97e-4d4c-8f43-7a624f6582bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789603810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.789603810
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2393120840
Short name T755
Test name
Test status
Simulation time 166652173067 ps
CPU time 184.53 seconds
Started Jul 01 05:31:46 PM PDT 24
Finished Jul 01 05:34:51 PM PDT 24
Peak memory 201832 kb
Host smart-492adb3d-3954-41d7-a73b-adcaeb9e35f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393120840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2393120840
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3806086188
Short name T165
Test name
Test status
Simulation time 189880474912 ps
CPU time 193.77 seconds
Started Jul 01 05:31:45 PM PDT 24
Finished Jul 01 05:35:00 PM PDT 24
Peak memory 201924 kb
Host smart-16881863-42c8-4584-b1df-a675ff49229a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806086188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3806086188
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2651095333
Short name T5
Test name
Test status
Simulation time 206180177810 ps
CPU time 95.5 seconds
Started Jul 01 05:31:52 PM PDT 24
Finished Jul 01 05:33:28 PM PDT 24
Peak memory 201864 kb
Host smart-2d0cf5aa-300b-4386-a9fc-10082a383652
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651095333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2651095333
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2434642815
Short name T524
Test name
Test status
Simulation time 84216149186 ps
CPU time 438.34 seconds
Started Jul 01 05:31:52 PM PDT 24
Finished Jul 01 05:39:11 PM PDT 24
Peak memory 202272 kb
Host smart-e4e7a886-488f-48a6-b0e0-f6da4ac2c9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434642815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2434642815
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.262529057
Short name T430
Test name
Test status
Simulation time 34433252053 ps
CPU time 76.53 seconds
Started Jul 01 05:31:53 PM PDT 24
Finished Jul 01 05:33:10 PM PDT 24
Peak memory 201756 kb
Host smart-17209274-222f-4f32-afbf-1893941b0c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262529057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.262529057
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3497854459
Short name T565
Test name
Test status
Simulation time 4814302787 ps
CPU time 11.19 seconds
Started Jul 01 05:31:53 PM PDT 24
Finished Jul 01 05:32:04 PM PDT 24
Peak memory 201636 kb
Host smart-e121e707-ce74-4739-b3c3-dbbdbf1268d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497854459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3497854459
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.663164959
Short name T392
Test name
Test status
Simulation time 5900564976 ps
CPU time 15.39 seconds
Started Jul 01 05:31:46 PM PDT 24
Finished Jul 01 05:32:02 PM PDT 24
Peak memory 201680 kb
Host smart-20cfb11b-b2f6-4b7e-9af7-18a0ddeaabe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663164959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.663164959
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3221611361
Short name T649
Test name
Test status
Simulation time 189132995382 ps
CPU time 115.29 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:33:55 PM PDT 24
Peak memory 201944 kb
Host smart-d945f7f8-c50c-4a9e-8133-6f513c63bc3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221611361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3221611361
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3077472650
Short name T14
Test name
Test status
Simulation time 19380558901 ps
CPU time 38.3 seconds
Started Jul 01 05:31:58 PM PDT 24
Finished Jul 01 05:32:37 PM PDT 24
Peak memory 202136 kb
Host smart-40e3a696-94b2-4eda-872f-e1a46b3e924a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077472650 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3077472650
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2337956457
Short name T775
Test name
Test status
Simulation time 470360697 ps
CPU time 0.88 seconds
Started Jul 01 05:32:09 PM PDT 24
Finished Jul 01 05:32:11 PM PDT 24
Peak memory 201672 kb
Host smart-864221b0-db47-46cb-89ab-7802b286e98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337956457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2337956457
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.4184108618
Short name T291
Test name
Test status
Simulation time 569096687916 ps
CPU time 234.45 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:35:54 PM PDT 24
Peak memory 201840 kb
Host smart-7e26e832-db91-4ff4-8aea-c634af3a9433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184108618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.4184108618
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.621202172
Short name T587
Test name
Test status
Simulation time 328176472406 ps
CPU time 360.31 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:38:00 PM PDT 24
Peak memory 201876 kb
Host smart-514433d2-cc26-42b1-b459-8799f424c2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621202172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.621202172
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.4272288434
Short name T648
Test name
Test status
Simulation time 327720757438 ps
CPU time 680.15 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:43:20 PM PDT 24
Peak memory 201836 kb
Host smart-36e37c8f-6216-4d31-91cb-19223901e468
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272288434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.4272288434
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1896863645
Short name T438
Test name
Test status
Simulation time 324401096860 ps
CPU time 198.41 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:35:19 PM PDT 24
Peak memory 201928 kb
Host smart-90d8addc-feba-4c91-8a49-43282af2c9c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896863645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1896863645
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2518090501
Short name T482
Test name
Test status
Simulation time 167178512950 ps
CPU time 102.22 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:33:42 PM PDT 24
Peak memory 201892 kb
Host smart-8aa5a699-b3a3-4e67-a3a8-b84972a1a57e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518090501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2518090501
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3128319531
Short name T564
Test name
Test status
Simulation time 587937231546 ps
CPU time 315.04 seconds
Started Jul 01 05:31:59 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 201864 kb
Host smart-d2224b78-bf4b-4607-af47-ff792065ad8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128319531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3128319531
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1812859534
Short name T481
Test name
Test status
Simulation time 76974574871 ps
CPU time 309.96 seconds
Started Jul 01 05:32:09 PM PDT 24
Finished Jul 01 05:37:20 PM PDT 24
Peak memory 202436 kb
Host smart-2253adcc-3e18-4390-864f-9f6804eddbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812859534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1812859534
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2658004418
Short name T639
Test name
Test status
Simulation time 38875888475 ps
CPU time 41.72 seconds
Started Jul 01 05:32:01 PM PDT 24
Finished Jul 01 05:32:44 PM PDT 24
Peak memory 201696 kb
Host smart-6c4d5f8f-a4c6-4fba-b501-d0df2dab04f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658004418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2658004418
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1514677439
Short name T771
Test name
Test status
Simulation time 4836096943 ps
CPU time 12.27 seconds
Started Jul 01 05:32:03 PM PDT 24
Finished Jul 01 05:32:16 PM PDT 24
Peak memory 201684 kb
Host smart-bb64a7eb-92b2-4b03-a02e-51037858320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514677439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1514677439
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2734634514
Short name T710
Test name
Test status
Simulation time 6031882033 ps
CPU time 4.42 seconds
Started Jul 01 05:31:58 PM PDT 24
Finished Jul 01 05:32:03 PM PDT 24
Peak memory 201748 kb
Host smart-530e9f53-23df-46a8-84df-5228dae32318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734634514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2734634514
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1792466290
Short name T425
Test name
Test status
Simulation time 166720156162 ps
CPU time 386.33 seconds
Started Jul 01 05:32:08 PM PDT 24
Finished Jul 01 05:38:36 PM PDT 24
Peak memory 201960 kb
Host smart-ac183afb-2d6c-4946-8c16-2495a1f09808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792466290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1792466290
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3005221286
Short name T762
Test name
Test status
Simulation time 55673393977 ps
CPU time 32.04 seconds
Started Jul 01 05:32:08 PM PDT 24
Finished Jul 01 05:32:41 PM PDT 24
Peak memory 210236 kb
Host smart-d9de3856-2939-4f75-ae81-03f315fafdcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005221286 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3005221286
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3033061407
Short name T720
Test name
Test status
Simulation time 435590241 ps
CPU time 1.61 seconds
Started Jul 01 05:32:22 PM PDT 24
Finished Jul 01 05:32:25 PM PDT 24
Peak memory 201636 kb
Host smart-be63d31b-fb9a-40b8-ad13-95f71eb7191d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033061407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3033061407
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3880644954
Short name T266
Test name
Test status
Simulation time 502571129373 ps
CPU time 220.91 seconds
Started Jul 01 05:32:16 PM PDT 24
Finished Jul 01 05:35:58 PM PDT 24
Peak memory 201868 kb
Host smart-446ef94a-3893-4e13-8bc7-06decd27f552
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880644954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3880644954
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1107338672
Short name T173
Test name
Test status
Simulation time 164419844262 ps
CPU time 178.56 seconds
Started Jul 01 05:32:09 PM PDT 24
Finished Jul 01 05:35:09 PM PDT 24
Peak memory 201960 kb
Host smart-889f9a4e-ffb7-4f68-8d62-b3087ce96339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107338672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1107338672
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1355547122
Short name T531
Test name
Test status
Simulation time 165021184883 ps
CPU time 99.58 seconds
Started Jul 01 05:32:10 PM PDT 24
Finished Jul 01 05:33:51 PM PDT 24
Peak memory 201904 kb
Host smart-b94f264f-ab32-4720-a6ec-6b94fd949949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355547122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1355547122
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3352605705
Short name T781
Test name
Test status
Simulation time 496242538027 ps
CPU time 277.59 seconds
Started Jul 01 05:32:08 PM PDT 24
Finished Jul 01 05:36:47 PM PDT 24
Peak memory 201920 kb
Host smart-38f07cc1-f200-4ff8-87f6-83504ed53eca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352605705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3352605705
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.26702391
Short name T235
Test name
Test status
Simulation time 366534156446 ps
CPU time 217.65 seconds
Started Jul 01 05:32:15 PM PDT 24
Finished Jul 01 05:35:53 PM PDT 24
Peak memory 201952 kb
Host smart-a0a6ec46-7433-49f9-8a8f-6ce46e16d55a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26702391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_w
akeup.26702391
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2580598253
Short name T385
Test name
Test status
Simulation time 599589473909 ps
CPU time 337.43 seconds
Started Jul 01 05:32:15 PM PDT 24
Finished Jul 01 05:37:54 PM PDT 24
Peak memory 201908 kb
Host smart-e306986e-d355-409f-8dbc-5d4ed3bffbcd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580598253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2580598253
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1686895383
Short name T757
Test name
Test status
Simulation time 120435883179 ps
CPU time 420.13 seconds
Started Jul 01 05:32:21 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 202192 kb
Host smart-bee55949-0839-4eae-be4d-d95a30eef03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686895383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1686895383
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.330747130
Short name T352
Test name
Test status
Simulation time 41646335991 ps
CPU time 21.15 seconds
Started Jul 01 05:32:22 PM PDT 24
Finished Jul 01 05:32:44 PM PDT 24
Peak memory 201672 kb
Host smart-4cb7ccf8-057e-4cd4-8422-875b1fecc9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330747130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.330747130
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1205629756
Short name T453
Test name
Test status
Simulation time 5190410987 ps
CPU time 5.94 seconds
Started Jul 01 05:32:21 PM PDT 24
Finished Jul 01 05:32:28 PM PDT 24
Peak memory 201760 kb
Host smart-5c90dc8f-70f4-4fa0-9bfc-aa9cee680d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205629756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1205629756
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4012984282
Short name T381
Test name
Test status
Simulation time 5906813287 ps
CPU time 14.03 seconds
Started Jul 01 05:32:10 PM PDT 24
Finished Jul 01 05:32:25 PM PDT 24
Peak memory 201748 kb
Host smart-0b27b9fd-31d5-4fde-8015-3915cf9e8478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012984282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4012984282
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.999170569
Short name T407
Test name
Test status
Simulation time 477747373 ps
CPU time 1.18 seconds
Started Jul 01 05:32:32 PM PDT 24
Finished Jul 01 05:32:34 PM PDT 24
Peak memory 201632 kb
Host smart-d2b680b8-944e-440a-9af9-45390e7ac7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999170569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.999170569
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1318473813
Short name T748
Test name
Test status
Simulation time 244752154946 ps
CPU time 3.12 seconds
Started Jul 01 05:32:33 PM PDT 24
Finished Jul 01 05:32:37 PM PDT 24
Peak memory 201928 kb
Host smart-d1950736-bbda-4fd4-91a5-9188f41d5f2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318473813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1318473813
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1988598438
Short name T259
Test name
Test status
Simulation time 333090975883 ps
CPU time 387.55 seconds
Started Jul 01 05:32:33 PM PDT 24
Finished Jul 01 05:39:02 PM PDT 24
Peak memory 201940 kb
Host smart-b74b9b25-62b4-4ebe-87ee-4331d4dcb1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988598438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1988598438
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2277684200
Short name T740
Test name
Test status
Simulation time 317685393106 ps
CPU time 759.33 seconds
Started Jul 01 05:32:27 PM PDT 24
Finished Jul 01 05:45:07 PM PDT 24
Peak memory 201796 kb
Host smart-17c0cfa3-672a-43a2-847e-2352f7913c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277684200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2277684200
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.522865261
Short name T704
Test name
Test status
Simulation time 322977337357 ps
CPU time 698.25 seconds
Started Jul 01 05:32:27 PM PDT 24
Finished Jul 01 05:44:06 PM PDT 24
Peak memory 201864 kb
Host smart-dded4402-f5a3-4993-8276-ca8348bbadbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=522865261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.522865261
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.817477862
Short name T621
Test name
Test status
Simulation time 331292611110 ps
CPU time 714.33 seconds
Started Jul 01 05:32:21 PM PDT 24
Finished Jul 01 05:44:16 PM PDT 24
Peak memory 201940 kb
Host smart-64378789-a3a9-4524-8794-5d0db94c68d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817477862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.817477862
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2762568744
Short name T590
Test name
Test status
Simulation time 483018189140 ps
CPU time 1137.3 seconds
Started Jul 01 05:32:21 PM PDT 24
Finished Jul 01 05:51:20 PM PDT 24
Peak memory 201976 kb
Host smart-95b849c4-f3c1-4106-88fa-79ec2b6eb7df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762568744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2762568744
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.60725388
Short name T248
Test name
Test status
Simulation time 376155124509 ps
CPU time 412.02 seconds
Started Jul 01 05:32:27 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 202028 kb
Host smart-5acbc653-695a-490c-ad58-328f16ef0e96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60725388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_w
akeup.60725388
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2233876111
Short name T633
Test name
Test status
Simulation time 609752099060 ps
CPU time 366.64 seconds
Started Jul 01 05:32:27 PM PDT 24
Finished Jul 01 05:38:34 PM PDT 24
Peak memory 201876 kb
Host smart-91002c46-6f39-407e-acbf-1388c8c39a1d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233876111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2233876111
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3678544475
Short name T756
Test name
Test status
Simulation time 88620965689 ps
CPU time 456.44 seconds
Started Jul 01 05:32:35 PM PDT 24
Finished Jul 01 05:40:12 PM PDT 24
Peak memory 202312 kb
Host smart-975aba88-e50a-44c1-b83c-264c6b4291cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678544475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3678544475
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2756328779
Short name T466
Test name
Test status
Simulation time 24981675202 ps
CPU time 9.04 seconds
Started Jul 01 05:32:35 PM PDT 24
Finished Jul 01 05:32:45 PM PDT 24
Peak memory 201792 kb
Host smart-c265d1ff-403a-4888-b73a-bad020fc0a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756328779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2756328779
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1522167125
Short name T463
Test name
Test status
Simulation time 4467574937 ps
CPU time 3.25 seconds
Started Jul 01 05:32:32 PM PDT 24
Finished Jul 01 05:32:36 PM PDT 24
Peak memory 201660 kb
Host smart-f0bce7c7-9682-4781-81ee-4b6549c56436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522167125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1522167125
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3636654921
Short name T169
Test name
Test status
Simulation time 5572629786 ps
CPU time 4.08 seconds
Started Jul 01 05:32:21 PM PDT 24
Finished Jul 01 05:32:26 PM PDT 24
Peak memory 201728 kb
Host smart-e77d0bb9-bc4f-47f1-8382-5cb1320d051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636654921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3636654921
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2581831361
Short name T673
Test name
Test status
Simulation time 497813771277 ps
CPU time 643.75 seconds
Started Jul 01 05:32:32 PM PDT 24
Finished Jul 01 05:43:17 PM PDT 24
Peak memory 210448 kb
Host smart-cf139705-2bb1-4db6-982d-54b541d8f635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581831361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2581831361
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.276846324
Short name T96
Test name
Test status
Simulation time 107725482654 ps
CPU time 47.88 seconds
Started Jul 01 05:32:33 PM PDT 24
Finished Jul 01 05:33:22 PM PDT 24
Peak memory 210432 kb
Host smart-06204faa-ac82-4eef-8024-bab5a758e5fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276846324 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.276846324
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1932844767
Short name T79
Test name
Test status
Simulation time 433533767 ps
CPU time 0.91 seconds
Started Jul 01 05:32:45 PM PDT 24
Finished Jul 01 05:32:47 PM PDT 24
Peak memory 201580 kb
Host smart-ba920bdb-e3dd-4173-959d-bec789a1ba74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932844767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1932844767
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.507844031
Short name T27
Test name
Test status
Simulation time 166033887134 ps
CPU time 215.47 seconds
Started Jul 01 05:32:39 PM PDT 24
Finished Jul 01 05:36:15 PM PDT 24
Peak memory 201876 kb
Host smart-253f3478-d387-4bd2-a844-3e1c6af709da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507844031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.507844031
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.386807847
Short name T154
Test name
Test status
Simulation time 384492315241 ps
CPU time 159.05 seconds
Started Jul 01 05:32:45 PM PDT 24
Finished Jul 01 05:35:25 PM PDT 24
Peak memory 201952 kb
Host smart-e0ab512e-eaf6-4378-9a2c-c5b0d152d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386807847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.386807847
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3470286898
Short name T567
Test name
Test status
Simulation time 166426490839 ps
CPU time 45.64 seconds
Started Jul 01 05:32:40 PM PDT 24
Finished Jul 01 05:33:27 PM PDT 24
Peak memory 201868 kb
Host smart-29585827-c1d2-4ea3-a6e0-7da4d5c2836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470286898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3470286898
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.307427009
Short name T586
Test name
Test status
Simulation time 319936836345 ps
CPU time 190.36 seconds
Started Jul 01 05:32:38 PM PDT 24
Finished Jul 01 05:35:49 PM PDT 24
Peak memory 201868 kb
Host smart-52b855e1-500f-4bd5-872f-7d0dbfe807a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=307427009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.307427009
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.212137297
Short name T327
Test name
Test status
Simulation time 168360352169 ps
CPU time 39.66 seconds
Started Jul 01 05:32:42 PM PDT 24
Finished Jul 01 05:33:22 PM PDT 24
Peak memory 201892 kb
Host smart-f95db3a8-339c-45bd-9471-aff202ca82c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212137297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.212137297
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2481083136
Short name T447
Test name
Test status
Simulation time 158459295789 ps
CPU time 349.84 seconds
Started Jul 01 05:32:41 PM PDT 24
Finished Jul 01 05:38:32 PM PDT 24
Peak memory 201824 kb
Host smart-ea7f8c82-bcf2-45e2-8da5-55f989414a43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481083136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2481083136
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3076408657
Short name T102
Test name
Test status
Simulation time 209441569519 ps
CPU time 112.48 seconds
Started Jul 01 05:32:41 PM PDT 24
Finished Jul 01 05:34:34 PM PDT 24
Peak memory 201884 kb
Host smart-44343e79-b004-45df-805e-01d807b22916
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076408657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3076408657
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1483645206
Short name T508
Test name
Test status
Simulation time 124699411731 ps
CPU time 419.78 seconds
Started Jul 01 05:32:46 PM PDT 24
Finished Jul 01 05:39:47 PM PDT 24
Peak memory 202204 kb
Host smart-dee641e3-5862-4f23-8050-7e8d9f67cc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483645206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1483645206
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3043688417
Short name T642
Test name
Test status
Simulation time 38919711484 ps
CPU time 40.48 seconds
Started Jul 01 05:32:46 PM PDT 24
Finished Jul 01 05:33:27 PM PDT 24
Peak memory 201764 kb
Host smart-e8de82a9-9c41-4e60-8b85-bb0b7191e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043688417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3043688417
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4022994286
Short name T393
Test name
Test status
Simulation time 3448223902 ps
CPU time 8.6 seconds
Started Jul 01 05:32:44 PM PDT 24
Finished Jul 01 05:32:54 PM PDT 24
Peak memory 201696 kb
Host smart-02e77977-6c20-411d-b39b-7d31d2e6a398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022994286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4022994286
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3327376418
Short name T399
Test name
Test status
Simulation time 5869669195 ps
CPU time 4.13 seconds
Started Jul 01 05:32:34 PM PDT 24
Finished Jul 01 05:32:39 PM PDT 24
Peak memory 201648 kb
Host smart-f8e54701-8f38-489f-91fe-9a74fba56bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327376418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3327376418
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4129669779
Short name T692
Test name
Test status
Simulation time 361315872806 ps
CPU time 743.11 seconds
Started Jul 01 05:32:47 PM PDT 24
Finished Jul 01 05:45:11 PM PDT 24
Peak memory 201904 kb
Host smart-427791a7-775f-469b-838e-45d8b836c9d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129669779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4129669779
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.880929439
Short name T515
Test name
Test status
Simulation time 140210598748 ps
CPU time 306.6 seconds
Started Jul 01 05:32:45 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 210576 kb
Host smart-b2074f9e-72d5-4fc5-bd97-c4e10b0c1447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880929439 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.880929439
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4182916251
Short name T408
Test name
Test status
Simulation time 445780530 ps
CPU time 1.09 seconds
Started Jul 01 05:32:58 PM PDT 24
Finished Jul 01 05:33:00 PM PDT 24
Peak memory 201624 kb
Host smart-2687a1a6-6421-4f92-8a58-cb3cfa54a182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182916251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4182916251
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.377932461
Short name T646
Test name
Test status
Simulation time 553532465095 ps
CPU time 141.73 seconds
Started Jul 01 05:32:51 PM PDT 24
Finished Jul 01 05:35:13 PM PDT 24
Peak memory 201924 kb
Host smart-ff9fc7a0-53d6-4b46-9d0d-080483f767ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377932461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.377932461
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3650868010
Short name T131
Test name
Test status
Simulation time 201175779921 ps
CPU time 247.07 seconds
Started Jul 01 05:32:52 PM PDT 24
Finished Jul 01 05:37:00 PM PDT 24
Peak memory 202060 kb
Host smart-ac3637fe-43fb-46b8-9d63-8276f1d18578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650868010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3650868010
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4134494023
Short name T263
Test name
Test status
Simulation time 487763043286 ps
CPU time 1192.47 seconds
Started Jul 01 05:32:48 PM PDT 24
Finished Jul 01 05:52:41 PM PDT 24
Peak memory 202024 kb
Host smart-70e16b5c-6232-4e57-adc4-84b84a086b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134494023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4134494023
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1340557492
Short name T365
Test name
Test status
Simulation time 494062449690 ps
CPU time 323.52 seconds
Started Jul 01 05:32:44 PM PDT 24
Finished Jul 01 05:38:09 PM PDT 24
Peak memory 201856 kb
Host smart-30aa3410-cb12-4cf5-b37d-9fdf9f37be41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340557492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1340557492
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1756268917
Short name T89
Test name
Test status
Simulation time 341690723649 ps
CPU time 781.87 seconds
Started Jul 01 05:32:45 PM PDT 24
Finished Jul 01 05:45:48 PM PDT 24
Peak memory 201876 kb
Host smart-98a20309-ef27-4a73-8283-c35e90a9a92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756268917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1756268917
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.283795443
Short name T744
Test name
Test status
Simulation time 160466798205 ps
CPU time 181.79 seconds
Started Jul 01 05:32:44 PM PDT 24
Finished Jul 01 05:35:47 PM PDT 24
Peak memory 201868 kb
Host smart-c37f5ad4-b9c1-4bd3-bbdb-54625bc63890
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=283795443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.283795443
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2433014905
Short name T9
Test name
Test status
Simulation time 205825222988 ps
CPU time 474.91 seconds
Started Jul 01 05:32:50 PM PDT 24
Finished Jul 01 05:40:46 PM PDT 24
Peak memory 201852 kb
Host smart-637f6128-468f-40bb-a5f9-4064ca4c5ea6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433014905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2433014905
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3010960360
Short name T662
Test name
Test status
Simulation time 22581448109 ps
CPU time 8.42 seconds
Started Jul 01 05:32:52 PM PDT 24
Finished Jul 01 05:33:01 PM PDT 24
Peak memory 201696 kb
Host smart-fea04eac-6678-4021-ae7d-d066c1b31429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010960360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3010960360
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.957303499
Short name T468
Test name
Test status
Simulation time 2939501430 ps
CPU time 2.63 seconds
Started Jul 01 05:32:51 PM PDT 24
Finished Jul 01 05:32:54 PM PDT 24
Peak memory 201612 kb
Host smart-76900c20-ab68-48ad-bf73-98b9d5f29248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957303499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.957303499
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3307779191
Short name T458
Test name
Test status
Simulation time 5494203123 ps
CPU time 14.5 seconds
Started Jul 01 05:32:45 PM PDT 24
Finished Jul 01 05:33:00 PM PDT 24
Peak memory 201684 kb
Host smart-df5197be-4963-4ee2-bf73-7541a5b002f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307779191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3307779191
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.436163017
Short name T276
Test name
Test status
Simulation time 228493557479 ps
CPU time 382.54 seconds
Started Jul 01 05:32:57 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 218580 kb
Host smart-73b9733a-9501-4cf5-abef-7625a262e15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436163017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
436163017
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.590616104
Short name T545
Test name
Test status
Simulation time 489334668 ps
CPU time 0.98 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:27:58 PM PDT 24
Peak memory 201700 kb
Host smart-ad0c3206-a670-4ea5-bac6-6bc694b21471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590616104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.590616104
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1816593480
Short name T546
Test name
Test status
Simulation time 438043583833 ps
CPU time 884.1 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:42:41 PM PDT 24
Peak memory 201864 kb
Host smart-1c5427f6-6946-4669-a242-50e6aa0779bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816593480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1816593480
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2318606245
Short name T217
Test name
Test status
Simulation time 351638975756 ps
CPU time 830.43 seconds
Started Jul 01 05:27:55 PM PDT 24
Finished Jul 01 05:41:46 PM PDT 24
Peak memory 201884 kb
Host smart-f4e049f5-0f4b-48f9-99f3-7a23475c7817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318606245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2318606245
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2936082997
Short name T218
Test name
Test status
Simulation time 165872734954 ps
CPU time 204.06 seconds
Started Jul 01 05:27:58 PM PDT 24
Finished Jul 01 05:31:24 PM PDT 24
Peak memory 201876 kb
Host smart-d92285b8-8bc8-49c3-a952-4e95ff6091b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936082997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2936082997
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1827341424
Short name T553
Test name
Test status
Simulation time 489374867600 ps
CPU time 579.4 seconds
Started Jul 01 05:27:58 PM PDT 24
Finished Jul 01 05:37:39 PM PDT 24
Peak memory 201856 kb
Host smart-f6fe5ee9-1ac7-4208-868b-6dd87942faeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827341424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1827341424
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1470986881
Short name T675
Test name
Test status
Simulation time 494206498517 ps
CPU time 1148.82 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:47:08 PM PDT 24
Peak memory 201888 kb
Host smart-73af172f-d05a-485f-9a9f-64847b4bc72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470986881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1470986881
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2103273218
Short name T626
Test name
Test status
Simulation time 161549711258 ps
CPU time 373.34 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:34:10 PM PDT 24
Peak memory 201896 kb
Host smart-347aa030-440c-4624-a01b-63517adfae87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103273218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2103273218
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.365774371
Short name T752
Test name
Test status
Simulation time 431934128527 ps
CPU time 979.27 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:44:17 PM PDT 24
Peak memory 201928 kb
Host smart-c6daf2e4-7d1b-47ee-80c7-69ebdcf642ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365774371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.365774371
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1067506772
Short name T152
Test name
Test status
Simulation time 400101282043 ps
CPU time 203.78 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:31:23 PM PDT 24
Peak memory 201932 kb
Host smart-0f9b6077-054f-4dde-819d-336e76e8fe17
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067506772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1067506772
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2300237576
Short name T210
Test name
Test status
Simulation time 118048891772 ps
CPU time 504.76 seconds
Started Jul 01 05:27:58 PM PDT 24
Finished Jul 01 05:36:24 PM PDT 24
Peak memory 202200 kb
Host smart-4d808d10-c88a-4ca1-92b1-e2fd124171c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300237576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2300237576
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4125786632
Short name T448
Test name
Test status
Simulation time 26423256685 ps
CPU time 3.98 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:28:02 PM PDT 24
Peak memory 201808 kb
Host smart-129454aa-1de8-4155-a99a-3988ca20c82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125786632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4125786632
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.31577203
Short name T683
Test name
Test status
Simulation time 4540494111 ps
CPU time 12.08 seconds
Started Jul 01 05:27:56 PM PDT 24
Finished Jul 01 05:28:10 PM PDT 24
Peak memory 201780 kb
Host smart-33021f10-24f0-4fe5-8cde-0335e409c0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31577203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.31577203
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.4166387650
Short name T85
Test name
Test status
Simulation time 7625888367 ps
CPU time 9.07 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:28:08 PM PDT 24
Peak memory 218140 kb
Host smart-bea47b55-60b4-4ef5-be95-1d0156e6eccd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166387650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.4166387650
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.4266458466
Short name T636
Test name
Test status
Simulation time 5951985837 ps
CPU time 14.42 seconds
Started Jul 01 05:27:55 PM PDT 24
Finished Jul 01 05:28:10 PM PDT 24
Peak memory 201744 kb
Host smart-ff27e557-884b-4639-b956-0ffe5e3e0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266458466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4266458466
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.967743560
Short name T516
Test name
Test status
Simulation time 348217802195 ps
CPU time 719.3 seconds
Started Jul 01 05:27:57 PM PDT 24
Finished Jul 01 05:39:58 PM PDT 24
Peak memory 201884 kb
Host smart-fc5f6658-c7ab-466a-8d5b-68c9c5b04f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967743560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.967743560
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1639206605
Short name T367
Test name
Test status
Simulation time 418158220 ps
CPU time 1.1 seconds
Started Jul 01 05:33:04 PM PDT 24
Finished Jul 01 05:33:06 PM PDT 24
Peak memory 201636 kb
Host smart-cff602f9-7cef-4532-a09a-897d5f7044c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639206605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1639206605
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.231769408
Short name T65
Test name
Test status
Simulation time 330545859969 ps
CPU time 180.52 seconds
Started Jul 01 05:33:05 PM PDT 24
Finished Jul 01 05:36:06 PM PDT 24
Peak memory 201940 kb
Host smart-ebaceb8c-352e-4982-b3c0-2d690189cc82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231769408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.231769408
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2774252018
Short name T330
Test name
Test status
Simulation time 163636054406 ps
CPU time 106.86 seconds
Started Jul 01 05:33:05 PM PDT 24
Finished Jul 01 05:34:53 PM PDT 24
Peak memory 202024 kb
Host smart-c790425d-de30-4f94-a827-734c3ef6c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774252018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2774252018
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2635791774
Short name T684
Test name
Test status
Simulation time 492723974451 ps
CPU time 238.66 seconds
Started Jul 01 05:32:58 PM PDT 24
Finished Jul 01 05:36:57 PM PDT 24
Peak memory 201872 kb
Host smart-277b30ea-67fa-496d-8cca-db4eada58dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635791774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2635791774
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3752360441
Short name T623
Test name
Test status
Simulation time 332012752812 ps
CPU time 198.06 seconds
Started Jul 01 05:33:04 PM PDT 24
Finished Jul 01 05:36:23 PM PDT 24
Peak memory 201840 kb
Host smart-72b42fd2-4c40-4f7e-ba8e-f52090370464
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752360441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3752360441
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2861186182
Short name T150
Test name
Test status
Simulation time 492782909886 ps
CPU time 1098.6 seconds
Started Jul 01 05:32:57 PM PDT 24
Finished Jul 01 05:51:17 PM PDT 24
Peak memory 201960 kb
Host smart-2369f7fa-c59e-41c0-ad1e-e48cd452c2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861186182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2861186182
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2783551577
Short name T667
Test name
Test status
Simulation time 163792974968 ps
CPU time 368.81 seconds
Started Jul 01 05:32:57 PM PDT 24
Finished Jul 01 05:39:06 PM PDT 24
Peak memory 201928 kb
Host smart-0e1f4671-de58-44cd-9194-ba3eae857616
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783551577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2783551577
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3330605092
Short name T221
Test name
Test status
Simulation time 635515051663 ps
CPU time 176.23 seconds
Started Jul 01 05:33:04 PM PDT 24
Finished Jul 01 05:36:02 PM PDT 24
Peak memory 201964 kb
Host smart-591f48b7-ab54-49c5-9c60-ec40d0d4674b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330605092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3330605092
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4192049077
Short name T722
Test name
Test status
Simulation time 392008787389 ps
CPU time 864.53 seconds
Started Jul 01 05:33:04 PM PDT 24
Finished Jul 01 05:47:30 PM PDT 24
Peak memory 201836 kb
Host smart-2fbc8b6a-813e-4a89-987d-5ffb07c84d8f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192049077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4192049077
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.904392002
Short name T575
Test name
Test status
Simulation time 82239725888 ps
CPU time 331.18 seconds
Started Jul 01 05:33:04 PM PDT 24
Finished Jul 01 05:38:37 PM PDT 24
Peak memory 202280 kb
Host smart-7ba99995-3119-4d11-a154-db810620e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904392002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.904392002
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1312022248
Short name T571
Test name
Test status
Simulation time 25721842866 ps
CPU time 16.15 seconds
Started Jul 01 05:33:04 PM PDT 24
Finished Jul 01 05:33:22 PM PDT 24
Peak memory 201692 kb
Host smart-57326b5f-45fe-46dc-a17f-086b4da917e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312022248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1312022248
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.149340623
Short name T172
Test name
Test status
Simulation time 4323289519 ps
CPU time 10.87 seconds
Started Jul 01 05:33:03 PM PDT 24
Finished Jul 01 05:33:15 PM PDT 24
Peak memory 201756 kb
Host smart-bb95f64d-459c-41e8-8dd1-f438ed4016ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149340623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.149340623
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.529424370
Short name T38
Test name
Test status
Simulation time 6068316738 ps
CPU time 14.51 seconds
Started Jul 01 05:32:58 PM PDT 24
Finished Jul 01 05:33:13 PM PDT 24
Peak memory 201780 kb
Host smart-06596763-c0f6-445c-9aa7-158e6e4f981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529424370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.529424370
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2904906477
Short name T682
Test name
Test status
Simulation time 575864967673 ps
CPU time 1817.9 seconds
Started Jul 01 05:33:03 PM PDT 24
Finished Jul 01 06:03:22 PM PDT 24
Peak memory 202172 kb
Host smart-f658d6ea-4912-467d-8406-97f96c6bbd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904906477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2904906477
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3485033664
Short name T57
Test name
Test status
Simulation time 418398309161 ps
CPU time 88.75 seconds
Started Jul 01 05:33:02 PM PDT 24
Finished Jul 01 05:34:31 PM PDT 24
Peak memory 212752 kb
Host smart-6d037591-ac5a-48a0-9c6d-f43644f9d167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485033664 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3485033664
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3431698443
Short name T674
Test name
Test status
Simulation time 494405339 ps
CPU time 1.7 seconds
Started Jul 01 05:33:14 PM PDT 24
Finished Jul 01 05:33:17 PM PDT 24
Peak memory 201632 kb
Host smart-cfecaf1a-cae6-4179-bb2c-d5e84ddc691a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431698443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3431698443
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2366745649
Short name T500
Test name
Test status
Simulation time 169306374430 ps
CPU time 206.05 seconds
Started Jul 01 05:33:15 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 201872 kb
Host smart-ddb923eb-2b63-4adf-95f6-047ae7103758
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366745649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2366745649
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.225626308
Short name T709
Test name
Test status
Simulation time 162493266180 ps
CPU time 301.24 seconds
Started Jul 01 05:33:09 PM PDT 24
Finished Jul 01 05:38:12 PM PDT 24
Peak memory 201956 kb
Host smart-da8c12a6-30c7-435e-8b74-aaaca562d24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225626308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.225626308
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1942345714
Short name T620
Test name
Test status
Simulation time 166400363204 ps
CPU time 314.24 seconds
Started Jul 01 05:33:10 PM PDT 24
Finished Jul 01 05:38:25 PM PDT 24
Peak memory 201832 kb
Host smart-05940e4b-aecb-4f7c-8682-f8f5237b4a2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942345714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1942345714
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3640027344
Short name T151
Test name
Test status
Simulation time 161140612994 ps
CPU time 207.31 seconds
Started Jul 01 05:33:09 PM PDT 24
Finished Jul 01 05:36:37 PM PDT 24
Peak memory 201884 kb
Host smart-1e03cb83-94b9-4b61-8b30-bc7cd2e51aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640027344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3640027344
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.820115240
Short name T92
Test name
Test status
Simulation time 497522521921 ps
CPU time 354.16 seconds
Started Jul 01 05:33:10 PM PDT 24
Finished Jul 01 05:39:05 PM PDT 24
Peak memory 201904 kb
Host smart-efaea4c8-993e-4d39-8da5-bb9b88467567
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=820115240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.820115240
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.561262090
Short name T260
Test name
Test status
Simulation time 628677151082 ps
CPU time 880.95 seconds
Started Jul 01 05:33:09 PM PDT 24
Finished Jul 01 05:47:51 PM PDT 24
Peak memory 201956 kb
Host smart-7e0d9362-d123-4e3b-972e-171c2be230f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561262090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.561262090
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1906709160
Short name T436
Test name
Test status
Simulation time 386626680120 ps
CPU time 208.18 seconds
Started Jul 01 05:33:09 PM PDT 24
Finished Jul 01 05:36:39 PM PDT 24
Peak memory 201860 kb
Host smart-fd98e0d5-fdd9-4286-aee3-9f58fcebb325
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906709160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1906709160
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.74494536
Short name T580
Test name
Test status
Simulation time 32648405254 ps
CPU time 76.21 seconds
Started Jul 01 05:33:14 PM PDT 24
Finished Jul 01 05:34:31 PM PDT 24
Peak memory 201700 kb
Host smart-e1ca2c65-cb98-4847-9b7a-312d375e2a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74494536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.74494536
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4294174294
Short name T439
Test name
Test status
Simulation time 5021671697 ps
CPU time 11.71 seconds
Started Jul 01 05:33:14 PM PDT 24
Finished Jul 01 05:33:27 PM PDT 24
Peak memory 201660 kb
Host smart-e9eab5ee-db16-41ad-a25b-5cea3d615f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294174294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4294174294
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1981708188
Short name T37
Test name
Test status
Simulation time 5916036861 ps
CPU time 4.11 seconds
Started Jul 01 05:33:09 PM PDT 24
Finished Jul 01 05:33:14 PM PDT 24
Peak memory 201684 kb
Host smart-dabb14bb-4088-462e-8a4b-c729e9acd03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981708188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1981708188
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.404755655
Short name T15
Test name
Test status
Simulation time 94571908990 ps
CPU time 206.65 seconds
Started Jul 01 05:33:14 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 210580 kb
Host smart-b5945cc7-8dc6-4f33-97b3-b321d4056580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404755655 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.404755655
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1646858047
Short name T31
Test name
Test status
Simulation time 533913254 ps
CPU time 0.77 seconds
Started Jul 01 05:33:30 PM PDT 24
Finished Jul 01 05:33:31 PM PDT 24
Peak memory 201632 kb
Host smart-64ce40ed-8dec-41bf-97f4-218bb8e690df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646858047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1646858047
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1948697963
Short name T547
Test name
Test status
Simulation time 369911097127 ps
CPU time 252.62 seconds
Started Jul 01 05:33:21 PM PDT 24
Finished Jul 01 05:37:35 PM PDT 24
Peak memory 201848 kb
Host smart-7ff57f6c-978e-464e-909b-743f87e0513a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948697963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1948697963
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4272756414
Short name T461
Test name
Test status
Simulation time 489338713432 ps
CPU time 382.63 seconds
Started Jul 01 05:33:20 PM PDT 24
Finished Jul 01 05:39:43 PM PDT 24
Peak memory 201860 kb
Host smart-27d76f63-a4b7-4b07-9c27-157b7d598c26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272756414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4272756414
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1242823972
Short name T566
Test name
Test status
Simulation time 331683388342 ps
CPU time 652.28 seconds
Started Jul 01 05:33:20 PM PDT 24
Finished Jul 01 05:44:13 PM PDT 24
Peak memory 201952 kb
Host smart-abbf432f-9fda-4182-9de7-4b2d96e312c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242823972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1242823972
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3603406727
Short name T397
Test name
Test status
Simulation time 330024077512 ps
CPU time 208.74 seconds
Started Jul 01 05:33:21 PM PDT 24
Finished Jul 01 05:36:50 PM PDT 24
Peak memory 201936 kb
Host smart-cd6c26f7-ad9e-4ac9-9c34-d24df0b1dfab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603406727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3603406727
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.105971443
Short name T194
Test name
Test status
Simulation time 180649037185 ps
CPU time 38.43 seconds
Started Jul 01 05:33:22 PM PDT 24
Finished Jul 01 05:34:01 PM PDT 24
Peak memory 201848 kb
Host smart-e55fdf71-0297-43d8-b301-96daf2132db2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105971443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.105971443
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3015384607
Short name T770
Test name
Test status
Simulation time 398026133328 ps
CPU time 926.92 seconds
Started Jul 01 05:33:20 PM PDT 24
Finished Jul 01 05:48:47 PM PDT 24
Peak memory 201904 kb
Host smart-0d9695c8-35b5-43d1-a313-239e0e8d26d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015384607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3015384607
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2603723912
Short name T59
Test name
Test status
Simulation time 97911547981 ps
CPU time 363.57 seconds
Started Jul 01 05:33:26 PM PDT 24
Finished Jul 01 05:39:30 PM PDT 24
Peak memory 202252 kb
Host smart-b8249e4a-0ab9-4393-9d39-c772f93934ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603723912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2603723912
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1286237079
Short name T641
Test name
Test status
Simulation time 32733654125 ps
CPU time 71.91 seconds
Started Jul 01 05:33:27 PM PDT 24
Finished Jul 01 05:34:39 PM PDT 24
Peak memory 201656 kb
Host smart-0014e458-2f6a-4e8f-bada-620dc9300927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286237079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1286237079
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2439808132
Short name T526
Test name
Test status
Simulation time 4480640483 ps
CPU time 5.42 seconds
Started Jul 01 05:33:20 PM PDT 24
Finished Jul 01 05:33:26 PM PDT 24
Peak memory 201792 kb
Host smart-a1bd6408-6a59-4110-940c-f52b8f6c8411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439808132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2439808132
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2457726627
Short name T404
Test name
Test status
Simulation time 5752854698 ps
CPU time 15.06 seconds
Started Jul 01 05:33:22 PM PDT 24
Finished Jul 01 05:33:37 PM PDT 24
Peak memory 201668 kb
Host smart-b5878bae-9e9f-4284-bb43-0959af21ea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457726627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2457726627
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1751145245
Short name T659
Test name
Test status
Simulation time 157987616703 ps
CPU time 846.24 seconds
Started Jul 01 05:33:34 PM PDT 24
Finished Jul 01 05:47:41 PM PDT 24
Peak memory 211532 kb
Host smart-0b3dd6b8-5a3b-4a1f-8edd-fb929451231a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751145245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1751145245
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.758150999
Short name T41
Test name
Test status
Simulation time 455874905 ps
CPU time 0.8 seconds
Started Jul 01 05:33:43 PM PDT 24
Finished Jul 01 05:33:45 PM PDT 24
Peak memory 201632 kb
Host smart-23988a03-94b2-4fd7-b796-460c39d5179d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758150999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.758150999
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1566844851
Short name T634
Test name
Test status
Simulation time 507735956035 ps
CPU time 339.44 seconds
Started Jul 01 05:33:38 PM PDT 24
Finished Jul 01 05:39:19 PM PDT 24
Peak memory 201872 kb
Host smart-c481eb18-3f26-408a-815c-5425e30495af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566844851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1566844851
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1732885193
Short name T181
Test name
Test status
Simulation time 332360540099 ps
CPU time 78.48 seconds
Started Jul 01 05:33:31 PM PDT 24
Finished Jul 01 05:34:51 PM PDT 24
Peak memory 201888 kb
Host smart-bfbf7687-60de-4bb8-a41e-19b9de78bf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732885193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1732885193
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.839475730
Short name T591
Test name
Test status
Simulation time 170528522784 ps
CPU time 397.7 seconds
Started Jul 01 05:33:31 PM PDT 24
Finished Jul 01 05:40:10 PM PDT 24
Peak memory 201872 kb
Host smart-252e845f-0209-4297-84a7-e98a17696bd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=839475730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.839475730
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3607159370
Short name T55
Test name
Test status
Simulation time 496583115448 ps
CPU time 335.1 seconds
Started Jul 01 05:33:30 PM PDT 24
Finished Jul 01 05:39:06 PM PDT 24
Peak memory 201836 kb
Host smart-1a8f7d74-c093-4c22-b6e2-5da1e5774acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607159370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3607159370
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1504474715
Short name T520
Test name
Test status
Simulation time 494149647372 ps
CPU time 135 seconds
Started Jul 01 05:33:31 PM PDT 24
Finished Jul 01 05:35:47 PM PDT 24
Peak memory 201948 kb
Host smart-81d83d45-3c6b-41c9-af5a-a84f0208100a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504474715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1504474715
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2763580755
Short name T581
Test name
Test status
Simulation time 494084322123 ps
CPU time 103.44 seconds
Started Jul 01 05:33:41 PM PDT 24
Finished Jul 01 05:35:25 PM PDT 24
Peak memory 201892 kb
Host smart-d8fff201-1e8d-4096-a38e-385c250b388e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763580755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2763580755
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4120461095
Short name T480
Test name
Test status
Simulation time 593498527325 ps
CPU time 639.1 seconds
Started Jul 01 05:33:38 PM PDT 24
Finished Jul 01 05:44:18 PM PDT 24
Peak memory 201908 kb
Host smart-5d3e931e-d5ab-4558-9a62-ff231f8f0850
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120461095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4120461095
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2655921897
Short name T91
Test name
Test status
Simulation time 119750987767 ps
CPU time 390.94 seconds
Started Jul 01 05:33:38 PM PDT 24
Finished Jul 01 05:40:10 PM PDT 24
Peak memory 202320 kb
Host smart-4006cd16-ceb9-4544-a417-08efcc8f49d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655921897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2655921897
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3309407483
Short name T396
Test name
Test status
Simulation time 30598170903 ps
CPU time 74.59 seconds
Started Jul 01 05:33:38 PM PDT 24
Finished Jul 01 05:34:54 PM PDT 24
Peak memory 201748 kb
Host smart-7f716ec6-4273-4574-aeeb-03e7ae094583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309407483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3309407483
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.239596919
Short name T414
Test name
Test status
Simulation time 4754972271 ps
CPU time 3.62 seconds
Started Jul 01 05:33:38 PM PDT 24
Finished Jul 01 05:33:42 PM PDT 24
Peak memory 201716 kb
Host smart-78192176-7d13-4c7a-9c51-601a8a10a3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239596919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.239596919
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3074145172
Short name T543
Test name
Test status
Simulation time 5716475564 ps
CPU time 6.71 seconds
Started Jul 01 05:33:30 PM PDT 24
Finished Jul 01 05:33:38 PM PDT 24
Peak memory 201680 kb
Host smart-0b9491d4-a1ec-46e4-a829-f4d98e259235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074145172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3074145172
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.56125711
Short name T723
Test name
Test status
Simulation time 202933364648 ps
CPU time 122.15 seconds
Started Jul 01 05:33:37 PM PDT 24
Finished Jul 01 05:35:40 PM PDT 24
Peak memory 201880 kb
Host smart-c39baa0c-8ed0-4f67-a288-98a912c3ff0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56125711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.56125711
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3353125068
Short name T50
Test name
Test status
Simulation time 138943735669 ps
CPU time 257.74 seconds
Started Jul 01 05:33:38 PM PDT 24
Finished Jul 01 05:37:57 PM PDT 24
Peak memory 210552 kb
Host smart-66ac164c-6773-4d85-89b0-ee4098dc39e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353125068 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3353125068
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1487634976
Short name T389
Test name
Test status
Simulation time 293096124 ps
CPU time 1.23 seconds
Started Jul 01 05:33:58 PM PDT 24
Finished Jul 01 05:34:00 PM PDT 24
Peak memory 201632 kb
Host smart-b1d7e146-18e2-4815-86ce-a42eda394d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487634976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1487634976
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2409150023
Short name T148
Test name
Test status
Simulation time 181585066905 ps
CPU time 220.23 seconds
Started Jul 01 05:33:51 PM PDT 24
Finished Jul 01 05:37:32 PM PDT 24
Peak memory 201944 kb
Host smart-6e6ff07f-87ba-4d64-b033-50dd17dba060
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409150023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2409150023
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.364184698
Short name T246
Test name
Test status
Simulation time 344045279940 ps
CPU time 715.19 seconds
Started Jul 01 05:33:50 PM PDT 24
Finished Jul 01 05:45:46 PM PDT 24
Peak memory 201884 kb
Host smart-a0111c46-8407-4481-9970-c76f44f0d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364184698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.364184698
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1672246311
Short name T335
Test name
Test status
Simulation time 491707231914 ps
CPU time 251.29 seconds
Started Jul 01 05:33:43 PM PDT 24
Finished Jul 01 05:37:55 PM PDT 24
Peak memory 201820 kb
Host smart-1bc85de1-5c0d-43f1-80db-5af4cf3fe7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672246311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1672246311
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1606348540
Short name T678
Test name
Test status
Simulation time 162148871470 ps
CPU time 379.78 seconds
Started Jul 01 05:33:43 PM PDT 24
Finished Jul 01 05:40:04 PM PDT 24
Peak memory 201848 kb
Host smart-dfef7d34-a0cc-4d15-861c-a356a84a2a4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606348540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1606348540
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1090751085
Short name T654
Test name
Test status
Simulation time 165637913549 ps
CPU time 210.11 seconds
Started Jul 01 05:33:43 PM PDT 24
Finished Jul 01 05:37:14 PM PDT 24
Peak memory 201964 kb
Host smart-66c159cd-d274-47ea-95ac-836e299cbc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090751085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1090751085
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2564907993
Short name T506
Test name
Test status
Simulation time 323014173932 ps
CPU time 678.43 seconds
Started Jul 01 05:33:42 PM PDT 24
Finished Jul 01 05:45:01 PM PDT 24
Peak memory 201784 kb
Host smart-39e7eda5-fad6-4a84-bfdb-23dd19d9807e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564907993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2564907993
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3548028099
Short name T329
Test name
Test status
Simulation time 545183073287 ps
CPU time 331.75 seconds
Started Jul 01 05:33:44 PM PDT 24
Finished Jul 01 05:39:17 PM PDT 24
Peak memory 201888 kb
Host smart-bde481b2-300c-43ef-96ca-0a4721436510
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548028099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3548028099
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2405274403
Short name T364
Test name
Test status
Simulation time 414641171877 ps
CPU time 906.77 seconds
Started Jul 01 05:33:49 PM PDT 24
Finished Jul 01 05:48:57 PM PDT 24
Peak memory 201864 kb
Host smart-51a25a2c-c07e-41c4-901a-ab15b7d56553
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405274403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2405274403
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1686501158
Short name T431
Test name
Test status
Simulation time 77053763328 ps
CPU time 382.1 seconds
Started Jul 01 05:33:56 PM PDT 24
Finished Jul 01 05:40:19 PM PDT 24
Peak memory 202204 kb
Host smart-a93e107f-6941-49c7-a1ab-c9ab2dbf98e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686501158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1686501158
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.934559073
Short name T765
Test name
Test status
Simulation time 39270809708 ps
CPU time 42.08 seconds
Started Jul 01 05:33:59 PM PDT 24
Finished Jul 01 05:34:41 PM PDT 24
Peak memory 201692 kb
Host smart-4de45ea2-ad8f-46da-b43e-ecabb76c3051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934559073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.934559073
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.4142204452
Short name T360
Test name
Test status
Simulation time 4296219289 ps
CPU time 3.31 seconds
Started Jul 01 05:33:50 PM PDT 24
Finished Jul 01 05:33:54 PM PDT 24
Peak memory 201760 kb
Host smart-cbf8fa17-d50b-427b-be6b-cc0a79cb0be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142204452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.4142204452
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2359786512
Short name T568
Test name
Test status
Simulation time 5696206065 ps
CPU time 13.41 seconds
Started Jul 01 05:33:43 PM PDT 24
Finished Jul 01 05:33:57 PM PDT 24
Peak memory 201684 kb
Host smart-0ab5c297-185f-4ced-a368-b3a901a1ce7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359786512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2359786512
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4187351409
Short name T35
Test name
Test status
Simulation time 336509321881 ps
CPU time 398.35 seconds
Started Jul 01 05:33:57 PM PDT 24
Finished Jul 01 05:40:36 PM PDT 24
Peak memory 201940 kb
Host smart-fb5bb07b-984c-47d7-89c6-dfd7908a48d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187351409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4187351409
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3161856540
Short name T690
Test name
Test status
Simulation time 531667875 ps
CPU time 1.69 seconds
Started Jul 01 05:34:07 PM PDT 24
Finished Jul 01 05:34:10 PM PDT 24
Peak memory 201704 kb
Host smart-80209e4f-5b25-4f98-9cbb-de35d3af36df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161856540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3161856540
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3209373114
Short name T44
Test name
Test status
Simulation time 164576215909 ps
CPU time 12.51 seconds
Started Jul 01 05:33:59 PM PDT 24
Finished Jul 01 05:34:13 PM PDT 24
Peak memory 201948 kb
Host smart-78a33759-32e3-48ee-b82c-8d82d27e5197
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209373114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3209373114
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2713658573
Short name T774
Test name
Test status
Simulation time 437676665692 ps
CPU time 144.58 seconds
Started Jul 01 05:34:01 PM PDT 24
Finished Jul 01 05:36:27 PM PDT 24
Peak memory 201876 kb
Host smart-5e940d89-a7b9-4d98-817f-c535e06e651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713658573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2713658573
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2647533562
Short name T256
Test name
Test status
Simulation time 499136343316 ps
CPU time 1114.07 seconds
Started Jul 01 05:34:00 PM PDT 24
Finished Jul 01 05:52:35 PM PDT 24
Peak memory 201952 kb
Host smart-98f3fd2d-3b24-4c92-bab5-e0ba30a70eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647533562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2647533562
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1798157361
Short name T705
Test name
Test status
Simulation time 494736026749 ps
CPU time 318.16 seconds
Started Jul 01 05:34:01 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 202052 kb
Host smart-b074aee1-56e4-4d65-b992-9b3e478466e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798157361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1798157361
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3069189312
Short name T617
Test name
Test status
Simulation time 161845266161 ps
CPU time 193.21 seconds
Started Jul 01 05:34:01 PM PDT 24
Finished Jul 01 05:37:15 PM PDT 24
Peak memory 201884 kb
Host smart-11b8fb2d-0c67-41ee-9637-3e0ad36380e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069189312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3069189312
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2090554595
Short name T660
Test name
Test status
Simulation time 165005356059 ps
CPU time 188.14 seconds
Started Jul 01 05:34:00 PM PDT 24
Finished Jul 01 05:37:09 PM PDT 24
Peak memory 201852 kb
Host smart-f95beb55-117c-45fa-9a26-6d0c1afd4a7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090554595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2090554595
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2319661545
Short name T328
Test name
Test status
Simulation time 620072065611 ps
CPU time 377.71 seconds
Started Jul 01 05:33:59 PM PDT 24
Finished Jul 01 05:40:18 PM PDT 24
Peak memory 201968 kb
Host smart-c3c01e74-2968-409f-951a-bd310c417537
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319661545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2319661545
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4118879148
Short name T653
Test name
Test status
Simulation time 606471819445 ps
CPU time 363.24 seconds
Started Jul 01 05:34:01 PM PDT 24
Finished Jul 01 05:40:05 PM PDT 24
Peak memory 201944 kb
Host smart-dc693aa1-88e0-486e-bead-ee0e8dc9b3ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118879148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4118879148
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3702930414
Short name T766
Test name
Test status
Simulation time 110839413530 ps
CPU time 498.12 seconds
Started Jul 01 05:34:05 PM PDT 24
Finished Jul 01 05:42:24 PM PDT 24
Peak memory 202200 kb
Host smart-23f498a3-baac-4cb5-b3e4-045b22f2b53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702930414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3702930414
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2628107906
Short name T625
Test name
Test status
Simulation time 23837962410 ps
CPU time 5.33 seconds
Started Jul 01 05:34:00 PM PDT 24
Finished Jul 01 05:34:06 PM PDT 24
Peak memory 201680 kb
Host smart-f0e13667-14b8-4e50-ad50-f139a6268752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628107906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2628107906
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2880148916
Short name T45
Test name
Test status
Simulation time 3364008160 ps
CPU time 2.13 seconds
Started Jul 01 05:34:00 PM PDT 24
Finished Jul 01 05:34:03 PM PDT 24
Peak memory 201688 kb
Host smart-1897bf1c-f559-4bce-8d17-e06f0c7f7f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880148916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2880148916
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4242782521
Short name T528
Test name
Test status
Simulation time 5950013879 ps
CPU time 8.25 seconds
Started Jul 01 05:33:57 PM PDT 24
Finished Jul 01 05:34:06 PM PDT 24
Peak memory 201688 kb
Host smart-51bbf393-a0cc-4cbd-8027-f351d053cca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242782521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4242782521
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2354480013
Short name T609
Test name
Test status
Simulation time 321391221273 ps
CPU time 1132.79 seconds
Started Jul 01 05:34:07 PM PDT 24
Finished Jul 01 05:53:00 PM PDT 24
Peak memory 202208 kb
Host smart-10fa7b7a-7729-46e5-84d5-46b9cdb35221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354480013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2354480013
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2250840071
Short name T456
Test name
Test status
Simulation time 469920818 ps
CPU time 1.75 seconds
Started Jul 01 05:34:19 PM PDT 24
Finished Jul 01 05:34:21 PM PDT 24
Peak memory 201660 kb
Host smart-7ef7b7eb-a68c-4b3c-b24c-289975888a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250840071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2250840071
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2294616381
Short name T197
Test name
Test status
Simulation time 363591466586 ps
CPU time 57.29 seconds
Started Jul 01 05:34:11 PM PDT 24
Finished Jul 01 05:35:09 PM PDT 24
Peak memory 201852 kb
Host smart-f600f2b4-2bc5-44e2-bc3b-ce5ae44129f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294616381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2294616381
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.880625822
Short name T224
Test name
Test status
Simulation time 162061398075 ps
CPU time 325.77 seconds
Started Jul 01 05:34:14 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 201920 kb
Host smart-2fdca289-2134-4a66-830c-55b76dc67a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880625822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.880625822
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1362663928
Short name T167
Test name
Test status
Simulation time 334662605065 ps
CPU time 401.64 seconds
Started Jul 01 05:34:13 PM PDT 24
Finished Jul 01 05:40:55 PM PDT 24
Peak memory 202008 kb
Host smart-cf683d54-2dde-4306-8f09-3dbb3dea326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362663928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1362663928
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2028366127
Short name T457
Test name
Test status
Simulation time 331337220329 ps
CPU time 549.53 seconds
Started Jul 01 05:34:13 PM PDT 24
Finished Jul 01 05:43:24 PM PDT 24
Peak memory 201860 kb
Host smart-fe8ddb74-ffd2-4aa8-8677-b18900f66200
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028366127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2028366127
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3666925838
Short name T178
Test name
Test status
Simulation time 165721221270 ps
CPU time 371.86 seconds
Started Jul 01 05:34:12 PM PDT 24
Finished Jul 01 05:40:25 PM PDT 24
Peak memory 201888 kb
Host smart-9fc72eaa-7cf7-4897-a2d3-094ac881e5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666925838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3666925838
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1823173234
Short name T721
Test name
Test status
Simulation time 493602793985 ps
CPU time 289.28 seconds
Started Jul 01 05:34:14 PM PDT 24
Finished Jul 01 05:39:04 PM PDT 24
Peak memory 201820 kb
Host smart-ef07b4c9-24c9-4d8e-8806-eaf71c049e89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823173234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1823173234
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2339870041
Short name T382
Test name
Test status
Simulation time 200076384949 ps
CPU time 235.33 seconds
Started Jul 01 05:34:12 PM PDT 24
Finished Jul 01 05:38:08 PM PDT 24
Peak memory 201880 kb
Host smart-2929ad45-5b10-4e0c-8cbc-02c1fbdd5697
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339870041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2339870041
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2828393117
Short name T61
Test name
Test status
Simulation time 89454019669 ps
CPU time 271.48 seconds
Started Jul 01 05:34:18 PM PDT 24
Finished Jul 01 05:38:50 PM PDT 24
Peak memory 202304 kb
Host smart-a51231f5-75a9-4c0d-bdd8-bad348a3457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828393117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2828393117
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4051023527
Short name T717
Test name
Test status
Simulation time 35600374609 ps
CPU time 81.69 seconds
Started Jul 01 05:34:18 PM PDT 24
Finished Jul 01 05:35:40 PM PDT 24
Peak memory 201616 kb
Host smart-16c617da-cfbf-4a49-aba6-f7b7c48eee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051023527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4051023527
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3359468176
Short name T727
Test name
Test status
Simulation time 3571876036 ps
CPU time 4.64 seconds
Started Jul 01 05:34:11 PM PDT 24
Finished Jul 01 05:34:17 PM PDT 24
Peak memory 201792 kb
Host smart-bc83b5c1-9fdb-4293-b676-3076c74d3092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359468176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3359468176
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3090844572
Short name T605
Test name
Test status
Simulation time 5821862797 ps
CPU time 4.35 seconds
Started Jul 01 05:34:06 PM PDT 24
Finished Jul 01 05:34:12 PM PDT 24
Peak memory 201680 kb
Host smart-4d2f431f-cc0b-4d57-9283-277bfd83ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090844572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3090844572
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1998922621
Short name T790
Test name
Test status
Simulation time 63026681989 ps
CPU time 33.84 seconds
Started Jul 01 05:34:19 PM PDT 24
Finished Jul 01 05:34:54 PM PDT 24
Peak memory 211308 kb
Host smart-3b606f69-68ab-4e76-8ef0-22c9e7695136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998922621 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1998922621
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1862176916
Short name T643
Test name
Test status
Simulation time 328475901 ps
CPU time 1.44 seconds
Started Jul 01 05:34:33 PM PDT 24
Finished Jul 01 05:34:35 PM PDT 24
Peak memory 201632 kb
Host smart-48a3f940-9dcc-4340-b162-af7213bc3232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862176916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1862176916
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.4121666960
Short name T612
Test name
Test status
Simulation time 324252671630 ps
CPU time 363.09 seconds
Started Jul 01 05:34:27 PM PDT 24
Finished Jul 01 05:40:31 PM PDT 24
Peak memory 201944 kb
Host smart-3b789c24-9bab-48ce-bffe-af35107fc441
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121666960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.4121666960
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2455344790
Short name T622
Test name
Test status
Simulation time 161697611211 ps
CPU time 108.98 seconds
Started Jul 01 05:34:18 PM PDT 24
Finished Jul 01 05:36:08 PM PDT 24
Peak memory 201956 kb
Host smart-d4d3a85b-dd9d-427c-9db7-45707e6a5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455344790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2455344790
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2274054387
Short name T554
Test name
Test status
Simulation time 489080561415 ps
CPU time 422.31 seconds
Started Jul 01 05:34:17 PM PDT 24
Finished Jul 01 05:41:19 PM PDT 24
Peak memory 201852 kb
Host smart-cb948aed-4a5a-408d-9953-be274e930a73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274054387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2274054387
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1796937811
Short name T139
Test name
Test status
Simulation time 486746856190 ps
CPU time 281 seconds
Started Jul 01 05:34:19 PM PDT 24
Finished Jul 01 05:39:00 PM PDT 24
Peak memory 201868 kb
Host smart-ba9c7515-fed8-45e4-abc3-0e8cb09051c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796937811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1796937811
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.812824281
Short name T401
Test name
Test status
Simulation time 504927665763 ps
CPU time 384.25 seconds
Started Jul 01 05:34:18 PM PDT 24
Finished Jul 01 05:40:43 PM PDT 24
Peak memory 201872 kb
Host smart-4e49eaa9-abf9-4347-9f97-ea4294191698
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=812824281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.812824281
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.502791798
Short name T247
Test name
Test status
Simulation time 344016309316 ps
CPU time 726.75 seconds
Started Jul 01 05:34:22 PM PDT 24
Finished Jul 01 05:46:30 PM PDT 24
Peak memory 201964 kb
Host smart-00faa88b-685b-4910-8865-8877ea575feb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502791798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.502791798
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1345473032
Short name T760
Test name
Test status
Simulation time 202110221750 ps
CPU time 479.28 seconds
Started Jul 01 05:34:22 PM PDT 24
Finished Jul 01 05:42:22 PM PDT 24
Peak memory 201940 kb
Host smart-d264a310-51c2-4d67-bbb3-9b74a5438ac1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345473032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1345473032
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2675901906
Short name T58
Test name
Test status
Simulation time 123803526802 ps
CPU time 576.27 seconds
Started Jul 01 05:34:26 PM PDT 24
Finished Jul 01 05:44:03 PM PDT 24
Peak memory 202200 kb
Host smart-c32b9b4f-585a-4ec7-8304-678a3b344aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675901906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2675901906
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2994190165
Short name T551
Test name
Test status
Simulation time 35517574771 ps
CPU time 38.83 seconds
Started Jul 01 05:34:30 PM PDT 24
Finished Jul 01 05:35:10 PM PDT 24
Peak memory 201688 kb
Host smart-d68ce5e5-06da-4059-9a00-2613a64c75f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994190165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2994190165
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1419865730
Short name T2
Test name
Test status
Simulation time 5272811803 ps
CPU time 6.45 seconds
Started Jul 01 05:34:25 PM PDT 24
Finished Jul 01 05:34:32 PM PDT 24
Peak memory 201636 kb
Host smart-41b13131-1c62-49ba-a032-adb4bfb0d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419865730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1419865730
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2367279547
Short name T519
Test name
Test status
Simulation time 5825873438 ps
CPU time 7.12 seconds
Started Jul 01 05:34:19 PM PDT 24
Finished Jul 01 05:34:27 PM PDT 24
Peak memory 201652 kb
Host smart-f43d87a4-0292-4930-af48-fa3a2530af6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367279547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2367279547
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2807803777
Short name T579
Test name
Test status
Simulation time 377723832258 ps
CPU time 457.61 seconds
Started Jul 01 05:34:30 PM PDT 24
Finished Jul 01 05:42:09 PM PDT 24
Peak memory 201964 kb
Host smart-252036de-1808-49d5-9be5-0b852eefa170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807803777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2807803777
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2283709759
Short name T635
Test name
Test status
Simulation time 201711611973 ps
CPU time 234.55 seconds
Started Jul 01 05:34:32 PM PDT 24
Finished Jul 01 05:38:28 PM PDT 24
Peak memory 210524 kb
Host smart-e65cbf0f-6958-4271-9d64-ffaec8d7763e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283709759 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2283709759
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2028282781
Short name T375
Test name
Test status
Simulation time 483113358 ps
CPU time 1.65 seconds
Started Jul 01 05:34:47 PM PDT 24
Finished Jul 01 05:34:50 PM PDT 24
Peak memory 201628 kb
Host smart-f8fd8cd1-6d73-4e73-a851-cfebd59e4c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028282781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2028282781
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3332946119
Short name T497
Test name
Test status
Simulation time 162546109634 ps
CPU time 373.57 seconds
Started Jul 01 05:34:36 PM PDT 24
Finished Jul 01 05:40:50 PM PDT 24
Peak memory 201864 kb
Host smart-c96a4abb-7712-42f5-ae25-339ba6eae40c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332946119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3332946119
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2731317664
Short name T281
Test name
Test status
Simulation time 189310220807 ps
CPU time 235.65 seconds
Started Jul 01 05:34:38 PM PDT 24
Finished Jul 01 05:38:34 PM PDT 24
Peak memory 201940 kb
Host smart-9f5c99e1-d74e-4567-99d0-2f087d4d3d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731317664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2731317664
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3665199533
Short name T777
Test name
Test status
Simulation time 319966641069 ps
CPU time 574.42 seconds
Started Jul 01 05:34:31 PM PDT 24
Finished Jul 01 05:44:07 PM PDT 24
Peak memory 201884 kb
Host smart-eef84965-5696-4478-9b17-3cc8799159c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665199533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3665199533
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3118331843
Short name T423
Test name
Test status
Simulation time 161410813820 ps
CPU time 53.37 seconds
Started Jul 01 05:34:42 PM PDT 24
Finished Jul 01 05:35:36 PM PDT 24
Peak memory 201744 kb
Host smart-8ada70ca-aa40-4c89-88dc-572f85f60aac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118331843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3118331843
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1824646495
Short name T187
Test name
Test status
Simulation time 487251934499 ps
CPU time 295.13 seconds
Started Jul 01 05:34:32 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 202008 kb
Host smart-0bcfdbb0-02bc-4faa-ae24-471fb0e697f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824646495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1824646495
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.792799829
Short name T778
Test name
Test status
Simulation time 332329406146 ps
CPU time 189.68 seconds
Started Jul 01 05:34:30 PM PDT 24
Finished Jul 01 05:37:41 PM PDT 24
Peak memory 201852 kb
Host smart-e09c73bb-bd00-46b6-afc0-818a29718516
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=792799829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.792799829
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2438477178
Short name T297
Test name
Test status
Simulation time 404675163233 ps
CPU time 246.06 seconds
Started Jul 01 05:34:42 PM PDT 24
Finished Jul 01 05:38:48 PM PDT 24
Peak memory 201780 kb
Host smart-690728bd-3988-47f0-b797-46fad1f55c21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438477178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2438477178
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4133481429
Short name T395
Test name
Test status
Simulation time 193138775083 ps
CPU time 413.31 seconds
Started Jul 01 05:34:37 PM PDT 24
Finished Jul 01 05:41:31 PM PDT 24
Peak memory 201932 kb
Host smart-59d8d4e8-24d3-4242-a871-04f273c665ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133481429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4133481429
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1456097624
Short name T699
Test name
Test status
Simulation time 129302549245 ps
CPU time 444.49 seconds
Started Jul 01 05:34:39 PM PDT 24
Finished Jul 01 05:42:05 PM PDT 24
Peak memory 202240 kb
Host smart-3eb2072c-64ea-470e-a1f1-0f21905b22ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456097624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1456097624
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.185537456
Short name T391
Test name
Test status
Simulation time 25008717789 ps
CPU time 10.62 seconds
Started Jul 01 05:34:37 PM PDT 24
Finished Jul 01 05:34:48 PM PDT 24
Peak memory 201684 kb
Host smart-247f41a0-2bdb-449e-a688-da8c2e8b1e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185537456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.185537456
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.669398474
Short name T191
Test name
Test status
Simulation time 4498036676 ps
CPU time 11.4 seconds
Started Jul 01 05:34:38 PM PDT 24
Finished Jul 01 05:34:50 PM PDT 24
Peak memory 201756 kb
Host smart-4156273c-a0ed-43e0-874c-8930345d74a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669398474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.669398474
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1723211045
Short name T104
Test name
Test status
Simulation time 5720975127 ps
CPU time 4.8 seconds
Started Jul 01 05:34:33 PM PDT 24
Finished Jul 01 05:34:38 PM PDT 24
Peak memory 201676 kb
Host smart-afe75cc6-8243-41bb-a160-c21f48a00d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723211045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1723211045
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.4042262695
Short name T556
Test name
Test status
Simulation time 288794783614 ps
CPU time 355.52 seconds
Started Jul 01 05:34:41 PM PDT 24
Finished Jul 01 05:40:37 PM PDT 24
Peak memory 202088 kb
Host smart-e27cac3d-e9d2-4a36-aa6b-ecf039cd9b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042262695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.4042262695
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3086692477
Short name T787
Test name
Test status
Simulation time 55191818036 ps
CPU time 97.89 seconds
Started Jul 01 05:34:36 PM PDT 24
Finished Jul 01 05:36:14 PM PDT 24
Peak memory 210444 kb
Host smart-da214046-4015-4694-8e9d-d364d9814005
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086692477 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3086692477
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1303972177
Short name T491
Test name
Test status
Simulation time 422404072 ps
CPU time 1.67 seconds
Started Jul 01 05:34:58 PM PDT 24
Finished Jul 01 05:35:00 PM PDT 24
Peak memory 201660 kb
Host smart-a36428cd-4daf-4741-bfe8-ec1a0a34495a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303972177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1303972177
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.267560749
Short name T663
Test name
Test status
Simulation time 373161653598 ps
CPU time 840.21 seconds
Started Jul 01 05:34:46 PM PDT 24
Finished Jul 01 05:48:47 PM PDT 24
Peak memory 201884 kb
Host smart-5750e066-7e3a-4399-af83-f9b1a8f65a3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267560749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.267560749
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1343352562
Short name T1
Test name
Test status
Simulation time 170737135263 ps
CPU time 76.25 seconds
Started Jul 01 05:34:51 PM PDT 24
Finished Jul 01 05:36:08 PM PDT 24
Peak memory 201900 kb
Host smart-5afb724a-638b-4c6e-8d4c-e91b36fb63f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343352562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1343352562
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.621372768
Short name T563
Test name
Test status
Simulation time 491415441664 ps
CPU time 540.76 seconds
Started Jul 01 05:34:46 PM PDT 24
Finished Jul 01 05:43:47 PM PDT 24
Peak memory 201992 kb
Host smart-f2d48d4d-6516-49a3-b12b-45f1e5a7ea27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=621372768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.621372768
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1911046825
Short name T236
Test name
Test status
Simulation time 488277269217 ps
CPU time 1109.72 seconds
Started Jul 01 05:34:47 PM PDT 24
Finished Jul 01 05:53:17 PM PDT 24
Peak memory 201948 kb
Host smart-f74364ab-a0a4-47d6-9da8-7b43f0a0dfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911046825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1911046825
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.319052500
Short name T428
Test name
Test status
Simulation time 161798042580 ps
CPU time 350.49 seconds
Started Jul 01 05:34:45 PM PDT 24
Finished Jul 01 05:40:37 PM PDT 24
Peak memory 201948 kb
Host smart-65629dc4-8902-4217-9fa5-4feb5ec55d7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=319052500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.319052500
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3646012943
Short name T299
Test name
Test status
Simulation time 352618724055 ps
CPU time 802.73 seconds
Started Jul 01 05:34:45 PM PDT 24
Finished Jul 01 05:48:09 PM PDT 24
Peak memory 201952 kb
Host smart-f77e6a57-ee41-4d2c-9b5b-ca3e3925ff83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646012943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3646012943
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1456694654
Short name T451
Test name
Test status
Simulation time 194903783490 ps
CPU time 69.44 seconds
Started Jul 01 05:34:45 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 201836 kb
Host smart-d07b1faa-a35a-4b3d-8c1c-16dbc86b3efd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456694654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1456694654
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1879401943
Short name T572
Test name
Test status
Simulation time 96446154944 ps
CPU time 295.74 seconds
Started Jul 01 05:34:51 PM PDT 24
Finished Jul 01 05:39:47 PM PDT 24
Peak memory 202180 kb
Host smart-3a3b0304-5b83-4adc-b18d-d95d5f17c6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879401943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1879401943
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2864116158
Short name T349
Test name
Test status
Simulation time 45103524895 ps
CPU time 52.33 seconds
Started Jul 01 05:34:53 PM PDT 24
Finished Jul 01 05:35:46 PM PDT 24
Peak memory 201744 kb
Host smart-161f2095-08c6-4b54-bd40-f3b9fc5f884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864116158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2864116158
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1868172203
Short name T26
Test name
Test status
Simulation time 2964998142 ps
CPU time 2.45 seconds
Started Jul 01 05:34:51 PM PDT 24
Finished Jul 01 05:34:54 PM PDT 24
Peak memory 201684 kb
Host smart-803267d5-0a56-4d68-b8ee-ad13d6d1ec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868172203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1868172203
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.557656604
Short name T190
Test name
Test status
Simulation time 6118325943 ps
CPU time 3.91 seconds
Started Jul 01 05:34:45 PM PDT 24
Finished Jul 01 05:34:50 PM PDT 24
Peak memory 201684 kb
Host smart-fef452ca-3e67-429d-a514-48d1b7698fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557656604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.557656604
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2369207605
Short name T317
Test name
Test status
Simulation time 592747941645 ps
CPU time 689.73 seconds
Started Jul 01 05:34:57 PM PDT 24
Finished Jul 01 05:46:28 PM PDT 24
Peak memory 201808 kb
Host smart-ec473e52-c012-4b45-bb16-64a8226759af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369207605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2369207605
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2916244630
Short name T21
Test name
Test status
Simulation time 581868144903 ps
CPU time 177.59 seconds
Started Jul 01 05:34:52 PM PDT 24
Finished Jul 01 05:37:50 PM PDT 24
Peak memory 210556 kb
Host smart-69a2cad7-8e22-4607-8b4e-1ed39d9d1cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916244630 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2916244630
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3498862096
Short name T741
Test name
Test status
Simulation time 394322539 ps
CPU time 0.8 seconds
Started Jul 01 05:28:02 PM PDT 24
Finished Jul 01 05:28:04 PM PDT 24
Peak memory 201636 kb
Host smart-fbc59159-64fd-4bf3-a48a-35e7a4991a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498862096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3498862096
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1130574980
Short name T149
Test name
Test status
Simulation time 485168468017 ps
CPU time 87.79 seconds
Started Jul 01 05:28:03 PM PDT 24
Finished Jul 01 05:29:31 PM PDT 24
Peak memory 201980 kb
Host smart-e6a1a929-b57f-4358-86cd-712aeac6bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130574980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1130574980
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.522837551
Short name T624
Test name
Test status
Simulation time 489635191998 ps
CPU time 1021.99 seconds
Started Jul 01 05:28:00 PM PDT 24
Finished Jul 01 05:45:03 PM PDT 24
Peak memory 201828 kb
Host smart-d0aa3ba9-ca6d-495a-a6df-4ec53ee5f17a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=522837551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.522837551
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2579524307
Short name T222
Test name
Test status
Simulation time 329668057495 ps
CPU time 672.12 seconds
Started Jul 01 05:28:03 PM PDT 24
Finished Jul 01 05:39:16 PM PDT 24
Peak memory 201972 kb
Host smart-6ca8eafe-443e-4bd6-952c-090de21abd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579524307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2579524307
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2588700848
Short name T656
Test name
Test status
Simulation time 504643057193 ps
CPU time 612.52 seconds
Started Jul 01 05:28:02 PM PDT 24
Finished Jul 01 05:38:15 PM PDT 24
Peak memory 201872 kb
Host smart-355b826b-36ea-4f9f-9654-2c6616c39c8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588700848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2588700848
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.844082220
Short name T307
Test name
Test status
Simulation time 543057239822 ps
CPU time 581.27 seconds
Started Jul 01 05:28:04 PM PDT 24
Finished Jul 01 05:37:46 PM PDT 24
Peak memory 201940 kb
Host smart-4054c702-c220-4f48-a552-a98d8a8bf211
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844082220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.844082220
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.572854034
Short name T413
Test name
Test status
Simulation time 205545369204 ps
CPU time 461.23 seconds
Started Jul 01 05:28:04 PM PDT 24
Finished Jul 01 05:35:46 PM PDT 24
Peak memory 201916 kb
Host smart-61a8fe01-087f-4fe7-867d-bedb7d03fac4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572854034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.572854034
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2885506307
Short name T201
Test name
Test status
Simulation time 94593649283 ps
CPU time 328.46 seconds
Started Jul 01 05:28:02 PM PDT 24
Finished Jul 01 05:33:32 PM PDT 24
Peak memory 202208 kb
Host smart-ebee35d8-9182-4d5d-8783-cbaf1f8bf8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885506307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2885506307
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1384336538
Short name T687
Test name
Test status
Simulation time 41214129425 ps
CPU time 13.91 seconds
Started Jul 01 05:28:03 PM PDT 24
Finished Jul 01 05:28:18 PM PDT 24
Peak memory 201760 kb
Host smart-0a3115e6-1ab0-41be-8da4-bed876daacd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384336538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1384336538
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1431323548
Short name T488
Test name
Test status
Simulation time 3745454460 ps
CPU time 3.14 seconds
Started Jul 01 05:28:03 PM PDT 24
Finished Jul 01 05:28:07 PM PDT 24
Peak memory 201728 kb
Host smart-8668f95a-5510-4b52-8429-6ef070f9c061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431323548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1431323548
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1390228340
Short name T540
Test name
Test status
Simulation time 5642449739 ps
CPU time 13.97 seconds
Started Jul 01 05:28:06 PM PDT 24
Finished Jul 01 05:28:20 PM PDT 24
Peak memory 201752 kb
Host smart-dbe57410-26cf-4108-8482-76080c62651b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390228340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1390228340
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3159131952
Short name T241
Test name
Test status
Simulation time 425635700686 ps
CPU time 698.9 seconds
Started Jul 01 05:28:03 PM PDT 24
Finished Jul 01 05:39:43 PM PDT 24
Peak memory 218620 kb
Host smart-5b310c2d-eaba-4739-a2d8-ede36180ac8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159131952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3159131952
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1659145459
Short name T279
Test name
Test status
Simulation time 297704508631 ps
CPU time 232.6 seconds
Started Jul 01 05:28:03 PM PDT 24
Finished Jul 01 05:31:56 PM PDT 24
Peak memory 210640 kb
Host smart-4c7d9aa6-e2d6-441c-8ab0-7e0ad01b32ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659145459 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1659145459
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4111703343
Short name T507
Test name
Test status
Simulation time 450744168 ps
CPU time 1.05 seconds
Started Jul 01 05:28:09 PM PDT 24
Finished Jul 01 05:28:12 PM PDT 24
Peak memory 201620 kb
Host smart-cc5763e0-91e9-456e-b177-7968601025ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111703343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4111703343
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4157826459
Short name T157
Test name
Test status
Simulation time 583629293962 ps
CPU time 246.96 seconds
Started Jul 01 05:28:08 PM PDT 24
Finished Jul 01 05:32:16 PM PDT 24
Peak memory 201896 kb
Host smart-65952109-9a9d-4a75-8e89-ca671163eb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157826459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4157826459
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3594313089
Short name T305
Test name
Test status
Simulation time 166616619798 ps
CPU time 96.43 seconds
Started Jul 01 05:28:02 PM PDT 24
Finished Jul 01 05:29:39 PM PDT 24
Peak memory 201940 kb
Host smart-70ac305a-3480-4bf9-81db-c7310509ef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594313089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3594313089
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1091121231
Short name T711
Test name
Test status
Simulation time 166584826476 ps
CPU time 97.01 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:29:45 PM PDT 24
Peak memory 201936 kb
Host smart-d3642b96-d65f-418e-953e-a713a319dcb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091121231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1091121231
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2950484010
Short name T177
Test name
Test status
Simulation time 324927512468 ps
CPU time 761.39 seconds
Started Jul 01 05:28:06 PM PDT 24
Finished Jul 01 05:40:48 PM PDT 24
Peak memory 201964 kb
Host smart-1a3caa7f-c2da-4843-930c-ad8a6f67ea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950484010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2950484010
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2141677656
Short name T400
Test name
Test status
Simulation time 481251837395 ps
CPU time 294.74 seconds
Started Jul 01 05:28:06 PM PDT 24
Finished Jul 01 05:33:01 PM PDT 24
Peak memory 201920 kb
Host smart-f0a989d5-3d18-41b4-8128-bb3b5d1675b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141677656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2141677656
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.420631355
Short name T185
Test name
Test status
Simulation time 366774092779 ps
CPU time 227.59 seconds
Started Jul 01 05:28:08 PM PDT 24
Finished Jul 01 05:31:57 PM PDT 24
Peak memory 201856 kb
Host smart-6d633e80-4321-4f69-aa75-643095b478ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420631355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.420631355
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3279900571
Short name T730
Test name
Test status
Simulation time 396471467104 ps
CPU time 916.13 seconds
Started Jul 01 05:28:06 PM PDT 24
Finished Jul 01 05:43:23 PM PDT 24
Peak memory 201984 kb
Host smart-ea0347cb-1697-4043-ab0f-03ebee162cce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279900571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3279900571
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.97439506
Short name T474
Test name
Test status
Simulation time 110519066961 ps
CPU time 504.71 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:36:33 PM PDT 24
Peak memory 202172 kb
Host smart-81514b5e-0875-4f54-8eef-911b8be780fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97439506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.97439506
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.622001669
Short name T518
Test name
Test status
Simulation time 36274211864 ps
CPU time 20.55 seconds
Started Jul 01 05:28:08 PM PDT 24
Finished Jul 01 05:28:30 PM PDT 24
Peak memory 201720 kb
Host smart-0c6b6695-31ab-48e5-bf68-dca82c18f5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622001669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.622001669
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2397913598
Short name T691
Test name
Test status
Simulation time 4559259028 ps
CPU time 8.74 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:28:20 PM PDT 24
Peak memory 201812 kb
Host smart-56b0a142-f96d-4a04-8d73-5e32210bf36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397913598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2397913598
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4159263970
Short name T788
Test name
Test status
Simulation time 5725241832 ps
CPU time 3.75 seconds
Started Jul 01 05:28:05 PM PDT 24
Finished Jul 01 05:28:10 PM PDT 24
Peak memory 201816 kb
Host smart-354aa729-6321-4446-aee6-01c68ce9c408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159263970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4159263970
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.362260514
Short name T30
Test name
Test status
Simulation time 395049907087 ps
CPU time 891.92 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:43:00 PM PDT 24
Peak memory 201936 kb
Host smart-9ad04e39-a6c9-4381-82b2-ea205281629f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362260514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.362260514
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.559965122
Short name T615
Test name
Test status
Simulation time 100648102378 ps
CPU time 53.4 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:29:01 PM PDT 24
Peak memory 210588 kb
Host smart-9e85c779-ddef-42d2-8504-49c0ab0971c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559965122 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.559965122
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.280211155
Short name T373
Test name
Test status
Simulation time 330788827 ps
CPU time 1.36 seconds
Started Jul 01 05:28:15 PM PDT 24
Finished Jul 01 05:28:17 PM PDT 24
Peak memory 201584 kb
Host smart-59565fc9-0529-4898-b8db-3d561436477f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280211155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.280211155
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1663578036
Short name T483
Test name
Test status
Simulation time 164215144981 ps
CPU time 104.01 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:29:52 PM PDT 24
Peak memory 201872 kb
Host smart-fb7a4917-a1fb-4591-a5b9-9927bbebfdf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663578036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1663578036
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3338645503
Short name T146
Test name
Test status
Simulation time 171091328842 ps
CPU time 387.32 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:34:36 PM PDT 24
Peak memory 201896 kb
Host smart-f7ac248a-0d9a-411b-9c4d-0fc2a3915b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338645503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3338645503
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1683478626
Short name T758
Test name
Test status
Simulation time 507402053586 ps
CPU time 1198.24 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:48:10 PM PDT 24
Peak memory 201888 kb
Host smart-a49ba37d-2097-4d9a-958f-1bf280b0f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683478626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1683478626
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.270003047
Short name T593
Test name
Test status
Simulation time 168588379748 ps
CPU time 404.34 seconds
Started Jul 01 05:28:08 PM PDT 24
Finished Jul 01 05:34:54 PM PDT 24
Peak memory 201856 kb
Host smart-7aec8661-27b9-49e7-89a6-985043047aa2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=270003047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.270003047
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.519511501
Short name T174
Test name
Test status
Simulation time 487683045087 ps
CPU time 378.12 seconds
Started Jul 01 05:28:09 PM PDT 24
Finished Jul 01 05:34:28 PM PDT 24
Peak memory 201948 kb
Host smart-a0c109d7-2e77-4f77-b19f-c4ca15e085f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519511501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.519511501
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.722899012
Short name T716
Test name
Test status
Simulation time 491797214587 ps
CPU time 514.34 seconds
Started Jul 01 05:28:09 PM PDT 24
Finished Jul 01 05:36:45 PM PDT 24
Peak memory 201872 kb
Host smart-4eb3f718-af61-405e-bb8d-e7935742bd3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=722899012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.722899012
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3013641171
Short name T333
Test name
Test status
Simulation time 197180789270 ps
CPU time 120.72 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:30:12 PM PDT 24
Peak memory 201896 kb
Host smart-0da6bb8b-4027-4741-b739-ed79c4b02550
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013641171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3013641171
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4223647250
Short name T412
Test name
Test status
Simulation time 392341616456 ps
CPU time 217.98 seconds
Started Jul 01 05:28:08 PM PDT 24
Finished Jul 01 05:31:47 PM PDT 24
Peak memory 201936 kb
Host smart-9e19724c-8dd1-4196-bc9b-d127399ea500
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223647250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4223647250
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1320488386
Short name T521
Test name
Test status
Simulation time 79048655772 ps
CPU time 302.12 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:33:10 PM PDT 24
Peak memory 202244 kb
Host smart-2d87b76e-0633-45b5-b061-6fba350be3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320488386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1320488386
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.915555564
Short name T773
Test name
Test status
Simulation time 32917059477 ps
CPU time 20.84 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:28:33 PM PDT 24
Peak memory 201500 kb
Host smart-d1b45a3f-b767-4a87-bf40-d8f3ad5e8fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915555564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.915555564
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.415758329
Short name T695
Test name
Test status
Simulation time 4363078995 ps
CPU time 10.87 seconds
Started Jul 01 05:28:09 PM PDT 24
Finished Jul 01 05:28:21 PM PDT 24
Peak memory 201768 kb
Host smart-8e5754cb-f7cc-47fc-bcd0-e42b2c9858a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415758329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.415758329
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2003740891
Short name T390
Test name
Test status
Simulation time 5728641389 ps
CPU time 4.18 seconds
Started Jul 01 05:28:08 PM PDT 24
Finished Jul 01 05:28:13 PM PDT 24
Peak memory 201732 kb
Host smart-929ebd9f-dfe5-4587-967e-bd3e9154895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003740891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2003740891
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3084399789
Short name T326
Test name
Test status
Simulation time 219080086395 ps
CPU time 116.1 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:30:07 PM PDT 24
Peak memory 202012 kb
Host smart-5cc9993c-d538-43fa-ac37-215a585b8cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084399789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3084399789
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.842360696
Short name T469
Test name
Test status
Simulation time 198379620368 ps
CPU time 125.68 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:30:14 PM PDT 24
Peak memory 210480 kb
Host smart-4b257a59-ab2c-4433-a04a-616c3c36b16e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842360696 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.842360696
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.975335491
Short name T487
Test name
Test status
Simulation time 379827551 ps
CPU time 1.44 seconds
Started Jul 01 05:28:22 PM PDT 24
Finished Jul 01 05:28:24 PM PDT 24
Peak memory 201584 kb
Host smart-76b483c6-8915-41b5-b920-d45fcb1ab684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975335491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.975335491
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1120055149
Short name T337
Test name
Test status
Simulation time 162183438625 ps
CPU time 53.66 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:29:08 PM PDT 24
Peak memory 201860 kb
Host smart-3564700e-2601-4912-b4cc-f54b3504a462
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120055149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1120055149
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1059512609
Short name T596
Test name
Test status
Simulation time 166786708869 ps
CPU time 59.97 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:29:11 PM PDT 24
Peak memory 201948 kb
Host smart-2139951f-218e-4eea-bff7-a4f3f1517c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059512609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1059512609
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3761091489
Short name T737
Test name
Test status
Simulation time 327413322700 ps
CPU time 745.67 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:40:33 PM PDT 24
Peak memory 201912 kb
Host smart-0cc2d226-8ac3-48fa-ac5d-610d0ecf64ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761091489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3761091489
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3534226771
Short name T415
Test name
Test status
Simulation time 326296352310 ps
CPU time 178.31 seconds
Started Jul 01 05:28:07 PM PDT 24
Finished Jul 01 05:31:06 PM PDT 24
Peak memory 201956 kb
Host smart-1bb541f7-b93b-4849-b003-2e2738be155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534226771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3534226771
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.944478347
Short name T800
Test name
Test status
Simulation time 328727854517 ps
CPU time 742.61 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:40:34 PM PDT 24
Peak memory 201972 kb
Host smart-bc22061e-ba4f-4360-863e-bf728d5cfea3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=944478347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.944478347
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.536555218
Short name T320
Test name
Test status
Simulation time 179439763078 ps
CPU time 101.08 seconds
Started Jul 01 05:28:09 PM PDT 24
Finished Jul 01 05:29:52 PM PDT 24
Peak memory 202068 kb
Host smart-aba66523-358c-4fbf-921b-92c39488ff36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536555218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.536555218
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2618945241
Short name T455
Test name
Test status
Simulation time 402359997912 ps
CPU time 924.33 seconds
Started Jul 01 05:28:14 PM PDT 24
Finished Jul 01 05:43:40 PM PDT 24
Peak memory 201872 kb
Host smart-5444608c-ce25-4716-adb2-182e925959ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618945241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2618945241
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4184318265
Short name T548
Test name
Test status
Simulation time 110089874482 ps
CPU time 346.68 seconds
Started Jul 01 05:28:16 PM PDT 24
Finished Jul 01 05:34:04 PM PDT 24
Peak memory 202284 kb
Host smart-37099179-8180-4b97-8a8d-084155f0f69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184318265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4184318265
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3568907351
Short name T535
Test name
Test status
Simulation time 36733010606 ps
CPU time 80.16 seconds
Started Jul 01 05:28:16 PM PDT 24
Finished Jul 01 05:29:37 PM PDT 24
Peak memory 201768 kb
Host smart-c1cc3baf-3f83-4081-8d87-43a8b4bdde53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568907351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3568907351
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.306997408
Short name T779
Test name
Test status
Simulation time 4799884289 ps
CPU time 1.91 seconds
Started Jul 01 05:28:13 PM PDT 24
Finished Jul 01 05:28:17 PM PDT 24
Peak memory 201688 kb
Host smart-a7a6cefc-1b56-4a6f-89e4-c2cab389ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306997408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.306997408
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1216868922
Short name T614
Test name
Test status
Simulation time 5656587832 ps
CPU time 15.46 seconds
Started Jul 01 05:28:10 PM PDT 24
Finished Jul 01 05:28:27 PM PDT 24
Peak memory 201408 kb
Host smart-b85b8b11-cd0e-421b-9514-4a53f6ad4b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216868922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1216868922
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2716847767
Short name T34
Test name
Test status
Simulation time 164248555731 ps
CPU time 91.47 seconds
Started Jul 01 05:28:14 PM PDT 24
Finished Jul 01 05:29:47 PM PDT 24
Peak memory 201976 kb
Host smart-0a4cadc0-501f-4b9f-ba4a-3cbd9320645b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716847767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2716847767
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3741476092
Short name T22
Test name
Test status
Simulation time 149450259662 ps
CPU time 175.04 seconds
Started Jul 01 05:28:14 PM PDT 24
Finished Jul 01 05:31:11 PM PDT 24
Peak memory 218724 kb
Host smart-8429b87e-787c-4663-a2c6-25a99c35439a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741476092 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3741476092
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.686783873
Short name T611
Test name
Test status
Simulation time 521199140 ps
CPU time 1.84 seconds
Started Jul 01 05:28:14 PM PDT 24
Finished Jul 01 05:28:18 PM PDT 24
Peak memory 201640 kb
Host smart-229b5390-8879-4ce5-be19-58d7c2feb155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686783873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.686783873
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.270230063
Short name T445
Test name
Test status
Simulation time 187828063116 ps
CPU time 413.13 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:35:07 PM PDT 24
Peak memory 201940 kb
Host smart-497be91c-3d0e-41ff-951a-469ff661d9a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270230063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.270230063
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2610492703
Short name T776
Test name
Test status
Simulation time 507846683653 ps
CPU time 287.33 seconds
Started Jul 01 05:28:13 PM PDT 24
Finished Jul 01 05:33:02 PM PDT 24
Peak memory 201952 kb
Host smart-75272ae7-59f9-48b4-b319-23efa12cabb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610492703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2610492703
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2167275026
Short name T665
Test name
Test status
Simulation time 159270016530 ps
CPU time 173.35 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:31:07 PM PDT 24
Peak memory 201828 kb
Host smart-42fd965b-4bbd-41b3-9a29-05abd6f11802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167275026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2167275026
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2566859489
Short name T460
Test name
Test status
Simulation time 497801142196 ps
CPU time 1213.44 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:48:28 PM PDT 24
Peak memory 201984 kb
Host smart-4c6be7bf-4239-4e32-9ae5-bccef1825092
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566859489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2566859489
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2793879201
Short name T300
Test name
Test status
Simulation time 163920343104 ps
CPU time 20.93 seconds
Started Jul 01 05:28:22 PM PDT 24
Finished Jul 01 05:28:44 PM PDT 24
Peak memory 201904 kb
Host smart-72df1b10-a252-4109-851a-46657e3bb4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793879201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2793879201
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2006797667
Short name T192
Test name
Test status
Simulation time 331231218765 ps
CPU time 206.41 seconds
Started Jul 01 05:28:12 PM PDT 24
Finished Jul 01 05:31:40 PM PDT 24
Peak memory 201924 kb
Host smart-5596d1ca-cd61-4aea-9228-8ddbf0ff03ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006797667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2006797667
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.355255693
Short name T100
Test name
Test status
Simulation time 169897897803 ps
CPU time 94.6 seconds
Started Jul 01 05:28:22 PM PDT 24
Finished Jul 01 05:29:58 PM PDT 24
Peak memory 201900 kb
Host smart-47bdbdfe-eb61-40f3-8e8e-50c7683b253a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355255693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.355255693
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2331822726
Short name T87
Test name
Test status
Simulation time 197112656875 ps
CPU time 100.64 seconds
Started Jul 01 05:28:13 PM PDT 24
Finished Jul 01 05:29:55 PM PDT 24
Peak memory 201860 kb
Host smart-cf024561-76b9-45e8-80ab-6cae1ef7e519
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331822726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2331822726
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.466405117
Short name T598
Test name
Test status
Simulation time 108656901985 ps
CPU time 567.38 seconds
Started Jul 01 05:28:22 PM PDT 24
Finished Jul 01 05:37:51 PM PDT 24
Peak memory 202196 kb
Host smart-251c9a5b-b38a-4572-8bd0-f3459b3f2f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466405117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.466405117
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.570569533
Short name T371
Test name
Test status
Simulation time 22575145515 ps
CPU time 49.39 seconds
Started Jul 01 05:28:14 PM PDT 24
Finished Jul 01 05:29:05 PM PDT 24
Peak memory 201688 kb
Host smart-5acfe873-1c75-4457-86d6-568820953eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570569533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.570569533
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1892495701
Short name T434
Test name
Test status
Simulation time 2877285499 ps
CPU time 2.32 seconds
Started Jul 01 05:28:13 PM PDT 24
Finished Jul 01 05:28:18 PM PDT 24
Peak memory 201632 kb
Host smart-a25e0944-4993-4ccf-81cb-0ccc7c8fe9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892495701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1892495701
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2319651188
Short name T374
Test name
Test status
Simulation time 6101808882 ps
CPU time 3.05 seconds
Started Jul 01 05:28:13 PM PDT 24
Finished Jul 01 05:28:18 PM PDT 24
Peak memory 201684 kb
Host smart-f41fb5d3-00ea-4866-9f8a-47b4c7fd9b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319651188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2319651188
Directory /workspace/9.adc_ctrl_smoke/latest
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