Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6775	1			T7	58		T8	20		T12	35
testmodes[AdcCtrlTestmodeNormal]	5326	1			T1	1		T2	1		T6	2
testmodes[AdcCtrlTestmodeLowpower]	5353	1			T1	2		T3	2		T5	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3694	1			T7	24		T8	19		T12	27
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1693	1			T7	20		T12	8		T71	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1278	1			T7	13		T51	1		T44	22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1668	1			T7	19		T12	7		T71	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1980	1			T6	1		T7	10		T11	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1342	1			T1	1		T7	19		T11	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1304	1			T7	15		T51	1		T44	24
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1310	1			T7	17		T14	1		T51	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2486	1			T1	1		T3	1		T5	10