Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22376

1

T1

26

T2

10

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3409

1

T1

2

T3

14

T11

58

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19626

1

T1

2

T3

17

T5

11

auto[1]

6159

1

T1

26

T2

10

T3

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T239	4		-	-		-	-
values[0]	37	1			T11	19		T195	1		T240	5
values[1]	739	1			T3	14		T11	16		T14	13
values[2]	651	1			T13	6		T44	18		T52	6
values[3]	585	1			T12	8		T51	1		T37	13
values[4]	725	1			T156	8		T195	1		T157	1
values[5]	709	1			T1	2		T3	17		T13	13
values[6]	586	1			T48	30		T49	1		T158	1
values[7]	708	1			T1	24		T14	15		T46	17
values[8]	763	1			T51	8		T155	22		T170	12
values[9]	3786	1			T1	2		T2	10		T6	2
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	911	1			T3	14		T11	35		T13	6
values[1]	579	1			T44	18		T49	7		T155	22
values[2]	706	1			T12	8		T51	1		T37	13
values[3]	662	1			T64	11		T195	1		T157	1
values[4]	765	1			T1	2		T3	17		T13	13
values[5]	634	1			T46	17		T49	1		T158	1
values[6]	2967	1			T2	10		T6	2		T14	15
values[7]	771	1			T1	24		T51	8		T156	15
values[8]	1134	1			T11	23		T68	13		T192	8
values[9]	163	1			T1	2		T9	12		T46	9
minimum	16493	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T160	1		T200	8		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	14		T11	23		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T49	1		T64	1		T166	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	9		T155	11		T52	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T51	1		T37	1		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T53	11		T219	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T195	1		T199	14		T241	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T64	1		T157	1		T241	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T3	17		T48	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	13		T14	14		T199	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	1		T158	1		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	10		T34	12		T17	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T2	1		T6	2		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T155	1		T56	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	12		T161	16		T242	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	5		T156	15		T170	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T68	10		T155	20		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T11	13		T192	1		T160	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T9	6		T46	3		T194	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T1	1		T32	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16348	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T200	11		T33	1		T243	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	12		T14	6		T192	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	6		T64	2		T166	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	9		T155	11		T64	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	12		T44	3		T198	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	7		T53	6		T98	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T201	10		T244	6		T118	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T64	10		T26	2		T210	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T48	16		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	14		T16	1		T242	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	9		T32	12		T40	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	7		T34	2		T17	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T2	9		T14	9		T200	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T155	1		T158	15		T201	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	12		T161	15		T242	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	3		T105	12		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T68	3		T155	2		T165	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	10		T192	7		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T9	6		T46	6		T194	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T1	1		T32	6		T165	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T239	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T246	1		T116	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T11	12		T195	1		T240	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T160	1		T200	8		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	14		T11	11		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T64	1		T166	15		T247	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	6		T44	9		T52	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	1		T37	1		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T155	11		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T156	8		T195	1		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T157	1		T53	11		T241	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T3	17		T161	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	13		T14	14		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	14		T49	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	3		T17	14		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	12		T14	6		T200	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T46	10		T155	1		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T155	20		T159	3		T26	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	5		T170	12		T171	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1842	1			T2	1		T6	2		T9	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	454	1			T1	1		T11	13		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T239	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T11	7		T213	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T200	11		T33	1		T243	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	5		T14	6		T192	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T64	2		T166	11		T247	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T44	9		T64	2		T200	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T37	12		T44	3		T49	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	7		T155	11		T98	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T198	4		T161	1		T201	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T53	6		T26	2		T210	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T161	10		T32	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	14		T64	10		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	16		T39	13		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T16	1		T17	6		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	12		T14	9		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T46	7		T155	1		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T155	2		T159	2		T26	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T51	3		T105	12		T127	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T2	9		T9	6		T68	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T1	1		T11	10		T192	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T160	1		T200	12		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T11	14		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	7		T64	3		T166	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T44	10		T155	12		T52	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T51	1		T37	13		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	8		T53	12		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T195	1		T199	1		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T64	11		T157	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	2		T3	1		T48	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T14	15		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	1		T158	1		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	8		T34	3		T17	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T2	10		T6	2		T14	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T155	2		T56	1		T158	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	13		T161	16		T242	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T51	5		T156	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T68	4		T155	3		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	11		T192	8		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T9	7		T46	7		T194	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T1	2		T32	7		T165	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16493	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T200	7		T33	1		T243	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	13		T11	21		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T166	14		T247	12		T66	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T44	8		T155	10		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	3		T156	7		T198	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T53	5		T219	8		T120	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T199	13		T241	7		T201	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T241	16		T26	2		T248	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	16		T48	13		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	12		T14	13		T199	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	10		T32	8		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	9		T34	11		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T14	5		T54	30		T50	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	10		T173	4		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	11		T161	15		T242	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T51	3		T156	14		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T68	9		T155	19		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	12		T160	11		T39	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T9	5		T46	2		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T193	3		T251	7		T252	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T239	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T246	2		T116	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T11	8		T195	1		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T160	1		T200	12		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T11	6		T14	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T64	3		T166	12		T247	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	1		T44	10		T52	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T51	1		T37	13		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	8		T155	12		T98	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T156	1		T195	1		T198	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T157	1		T53	12		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	2		T3	1		T161	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	1		T14	15		T64	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	17		T49	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	3		T17	15		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	13		T14	10		T200	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T46	8		T155	2		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T155	3		T159	3		T26	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T51	5		T170	1		T171	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T2	10		T6	2		T9	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T1	2		T11	11		T192	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T239	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T11	11		T240	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T200	7		T33	1		T243	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	13		T11	10		T14	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T166	14		T247	12		T66	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	5		T44	8		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T44	3		T66	11		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T155	10		T253	7		T254	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T156	7		T198	5		T199	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T53	5		T241	16		T26	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	16		T161	8		T32	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	12		T14	13		T199	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T48	13		T39	20		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	1		T17	5		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	11		T14	5		T200	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	9		T56	10		T120	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T155	19		T159	2		T26	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	3		T170	11		T173	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T9	5		T54	30		T68	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T11	12		T156	14		T160	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22206

1

T1

4

T2

10

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

3579

1

T1

24

T9

12

T11

42

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19648

1

T1

26

T5

11

T7

145

auto[1]

6137

1

T1

2

T2

10

T3

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T255	9		T256	35		-	-
values[0]	17	1			T257	12		T258	1		T259	4
values[1]	602	1			T11	23		T68	13		T48	30
values[2]	708	1			T1	2		T3	14		T11	19
values[3]	624	1			T1	24		T13	13		T14	15
values[4]	682	1			T3	17		T9	12		T156	8
values[5]	596	1			T51	8		T192	14		T155	22
values[6]	794	1			T13	6		T155	22		T156	9
values[7]	806	1			T12	8		T49	1		T52	6
values[8]	2904	1			T1	2		T2	10		T6	2
values[9]	1516	1			T11	16		T14	13		T49	7
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	778	1			T3	14		T11	23		T68	13
values[1]	637	1			T1	2		T11	19		T14	15
values[2]	597	1			T1	24		T9	12		T13	13
values[3]	761	1			T3	17		T51	8		T192	14
values[4]	604	1			T13	6		T155	44		T156	9
values[5]	900	1			T12	8		T164	1		T158	11
values[6]	2937	1			T2	10		T6	2		T54	32
values[7]	577	1			T1	2		T14	28		T51	1
values[8]	1233	1			T11	16		T14	13		T49	7
values[9]	235	1			T156	15		T260	1		T261	1
minimum	16526	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	14		T48	14		T64	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	13		T68	10		T159	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T200	4		T32	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	12		T14	6		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	13		T46	3		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	12		T9	6		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	17		T51	5		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T64	1		T32	8		T219	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	6		T156	9		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T155	31		T219	5		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T158	1		T39	21		T26	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T12	1		T164	1		T262	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T2	1		T6	2		T54	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	1		T157	1		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T51	1		T198	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	14		T46	10		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T11	11		T49	1		T199	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T14	7		T195	1		T199	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T260	1		T261	1		T193	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T156	15		T263	1		T264	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16369	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	16		T64	2		T32	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	10		T68	3		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T1	1		T200	7		T32	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	7		T14	9		T192	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	6		T155	1		T161	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	12		T9	6		T37	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T51	3		T192	13		T161	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T64	10		T32	7		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T64	2		T39	8		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T155	13		T219	14		T201	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T158	10		T39	13		T26	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	7		T16	1		T166	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T2	9		T266	16		T217	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	6		T26	1		T184	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	1		T198	4		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T14	14		T46	7		T242	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	5		T49	6		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T14	6		T200	11		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T193	9		T267	11		T268	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T269	6		T267	13		T270	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T51	5		T37	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T255	3		T256	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T257	6		T259	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	14		T64	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	13		T68	10		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T3	14		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	12		T192	1		T199	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	13		T46	3		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	12		T14	6		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	17		T156	8		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	6		T26	6		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T51	5		T192	1		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T155	20		T64	1		T166	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	6		T156	9		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T155	11		T262	10		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T52	6		T198	6		T34	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	1		T49	1		T53	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T1	1		T2	1		T6	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	14		T46	10		T56	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T11	11		T49	1		T199	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	449	1			T14	7		T156	15		T200	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T255	6		T256	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T257	6		T259	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	16		T64	2		T32	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	10		T68	3		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	1		T155	1		T200	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	7		T192	7		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	6		T200	14		T165	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	12		T14	9		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T161	16		T184	7		T40	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T9	6		T26	2		T32	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T51	3		T192	13		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T155	2		T64	10		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T158	10		T39	21		T26	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T155	11		T16	1		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T198	4		T34	2		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	7		T53	6		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T1	1		T2	9		T161	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	14		T46	7		T184	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T11	5		T49	6		T158	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T14	6		T200	11		T29	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1