Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21988

1

T1

4

T2

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3797

1

T1

24

T3

31

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19835

1

T1

4

T3

14

T5

11

auto[1]

5950

1

T1

24

T2

10

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T1	4		T64	11		T32	15
values[0]	64	1			T195	1		T65	18		T123	7
values[1]	687	1			T3	31		T12	8		T192	8
values[2]	868	1			T198	10		T170	4		T29	20
values[3]	656	1			T11	42		T14	13		T68	13
values[4]	719	1			T13	13		T44	18		T48	30
values[5]	2961	1			T2	10		T6	2		T54	32
values[6]	758	1			T9	12		T14	43		T199	14
values[7]	613	1			T1	24		T13	6		T51	8
values[8]	701	1			T49	1		T155	22		T32	21
values[9]	1024	1			T11	16		T37	13		T46	9
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	728	1			T3	14		T12	8		T156	8
values[1]	807	1			T14	13		T46	17		T52	6
values[2]	624	1			T11	42		T13	13		T68	13
values[3]	2992	1			T2	10		T6	2		T54	32
values[4]	806	1			T51	1		T155	2		T64	6
values[5]	608	1			T9	12		T14	43		T199	14
values[6]	755	1			T1	24		T13	6		T51	8
values[7]	691	1			T49	1		T155	22		T26	8
values[8]	916	1			T1	2		T11	16		T37	13
values[9]	126	1			T1	2		T64	11		T32	15
minimum	16732	1			T3	17		T5	11		T7	145

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T195	1		T53	11		T200	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	14		T12	1		T156	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T201	1		T248	15		T173	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	7		T46	10		T52	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	13		T68	10		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	25		T44	4		T199	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T2	1		T6	2		T54	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	9		T195	1		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T155	1		T64	1		T200	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T51	1		T64	1		T161	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	14		T166	7		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	6		T14	6		T199	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	6		T160	12		T199	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	12		T51	5		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	1		T26	6		T219	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T155	20		T218	1		T166	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	1		T46	3		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	11		T37	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T1	1		T105	1		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T64	1		T32	8		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16444	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T3	17		T192	1		T244	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T53	6		T200	7		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T12	7		T198	4		T39	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T201	10		T184	9		T66	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	6		T46	7		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T68	3		T242	14		T40	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	17		T44	3		T219	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T2	9		T48	16		T266	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T44	9		T32	6		T17	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T155	1		T64	2		T200	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T64	2		T161	15		T39	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	14		T166	5		T98	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	6		T14	9		T161	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T26	15		T173	18		T247	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	12		T51	3		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	2		T219	6		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T155	2		T166	11		T183	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T46	6		T34	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	5		T37	12		T192	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T1	1		T105	10		T176	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T64	10		T32	7		T334	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T51	5		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T192	7		T244	6		T65	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T1	2		T18	2		T296	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T64	1		T32	8		T101	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T195	1		T333	10		T326	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T65	11		T123	4		T188	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T156	9		T53	11		T161	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	31		T12	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T201	14		T173	5		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T198	6		T170	4		T29	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T68	10		T157	1		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	25		T14	7		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	13		T48	14		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T44	9		T195	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T2	1		T6	2		T54	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T51	1		T64	1		T161	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	14		T200	21		T166	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T9	6		T14	6		T199	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	6		T160	12		T199	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	12		T51	5		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	1		T219	7		T247	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T155	20		T32	9		T183	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T46	3		T56	11		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T11	11		T37	1		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T1	2		T296	9		T335	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T64	10		T32	7		T334	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T65	7		T123	3		T327	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T53	6		T161	1		T200	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	7		T192	7		T39	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T201	20		T184	9		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T198	4		T29	9		T289	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T68	3		T242	14		T66	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	17		T14	6		T44	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	16		T184	7		T40	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T44	9		T32	6		T17	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T2	9		T155	1		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T64	2		T161	15		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	14		T200	25		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	6		T14	9		T39	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T26	15		T173	18		T40	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	12		T51	3		T49	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T219	6		T247	14		T105	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T155	2		T32	12		T183	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T46	6		T26	2		T34	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	5		T37	12		T192	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T195	1		T53	12		T200	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T12	8		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T201	11		T248	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	7		T46	8		T52	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	1		T68	4		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	19		T44	4		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T2	10		T6	2		T54	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T44	10		T195	1		T32	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T155	2		T64	3		T200	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	1		T64	3		T161	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	15		T166	6		T98	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	7		T14	10		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T160	1		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	13		T51	5		T49	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	1		T26	6		T219	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T155	3		T218	1		T166	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T1	2		T46	7		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	6		T37	13		T192	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T1	2		T105	11		T176	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T64	11		T32	8		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16541	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T3	1		T192	8		T244	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T53	5		T200	3		T241	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	13		T156	7		T198	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T248	14		T173	4		T66	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	6		T46	9		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	12		T68	9		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	23		T44	3		T199	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T54	30		T48	13		T50	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T44	8		T17	5		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T200	19		T243	8		T120	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T161	15		T39	9		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T14	13		T166	6		T284	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	5		T14	5		T199	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	5		T160	11		T199	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	11		T51	3		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T26	2		T219	6		T243	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T155	19		T166	14		T183	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	2		T56	10		T262	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	10		T170	11		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T32	7		T334	18		T214	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T156	8		T161	6		T250	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T3	16		T65	5		T123	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T1	4		T18	2		T296	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T64	11		T32	8		T101	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T195	1		T333	1		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T65	13		T123	5		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T156	1		T53	12		T161	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	2		T12	8		T192	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T201	22		T173	1		T184	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T198	5		T170	1		T29	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T68	4		T157	1		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	19		T14	7		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T48	17		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T44	10		T195	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T2	10		T6	2		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T51	1		T64	3		T161	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	15		T200	27		T166	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	7		T14	10		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T160	1		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	13		T51	5		T49	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	1		T219	7		T247	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T155	3		T32	13		T183	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T46	7		T56	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T11	6		T37	13		T192	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T41	5		T267	13		T290	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T32	7		T334	18		T193	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T333	9		T326	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T65	5		T123	2		T188	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T156	8		T53	5		T161	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	29		T156	7		T39	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T201	12		T173	4		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T198	5		T170	3		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T68	9		T242	9		T248	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	23		T14	6		T44	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	12		T48	13		T156	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T44	8		T17	5		T67	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T54	30		T50	40		T271	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T161	15		T16	1		T34	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	13		T200	19		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	5		T14	5		T199	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	5		T160	11		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	11		T51	3		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T219	6		T247	19		T285	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T155	19		T32	8		T183	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	2		T56	10		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	10		T170	11		T33	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5