Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22275

1

T1

2

T2

10

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

3510

1

T1

26

T11

16

T12

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19943

1

T1

26

T3

31

T5

11

auto[1]

5842

1

T1

2

T2

10

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T3	17		T11	16		T170	12
values[0]	56	1			T32	7		T224	15		T336	12
values[1]	755	1			T1	2		T155	2		T156	15
values[2]	2931	1			T2	10		T6	2		T9	12
values[3]	567	1			T12	8		T46	9		T64	11
values[4]	646	1			T13	6		T68	13		T44	7
values[5]	773	1			T14	13		T44	18		T199	24
values[6]	826	1			T11	19		T14	28		T155	22
values[7]	633	1			T1	24		T3	14		T13	13
values[8]	710	1			T1	2		T37	13		T46	17
values[9]	1154	1			T11	23		T14	15		T51	8
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	793	1			T155	2		T156	15		T157	1
values[1]	2940	1			T2	10		T6	2		T9	12
values[2]	464	1			T170	4		T32	21		T55	3
values[3]	853	1			T13	6		T68	13		T44	7
values[4]	738	1			T14	41		T44	18		T199	24
values[5]	732	1			T11	19		T155	22		T56	11
values[6]	738	1			T1	24		T3	14		T13	13
values[7]	698	1			T1	2		T37	13		T46	17
values[8]	1071	1			T3	17		T11	39		T14	15
values[9]	101	1			T173	30		T105	13		T284	5
minimum	16657	1			T1	2		T5	11		T7	145

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T156	15		T157	1		T199	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T155	1		T26	1		T32	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T2	1		T6	2		T9	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T192	1		T64	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T32	9		T55	3		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T170	4		T101	1		T67	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T13	6		T68	10		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T48	14		T17	14		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	14		T164	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	7		T44	9		T199	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	12		T155	20		T56	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T200	13		T166	10		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	14		T51	1		T160	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	12		T13	13		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T200	8		T158	1		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T37	1		T46	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T3	17		T11	13		T14	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	11		T49	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T296	1		T20	8		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T173	12		T105	1		T284	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16399	1			T1	1		T5	11		T7	145
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T66	1		T337	4		T187	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T161	15		T200	7		T105	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T155	1		T26	1		T32	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T2	9		T9	6		T46	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	7		T192	7		T64	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T32	12		T173	1		T286	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T67	6		T167	17		T284	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T68	3		T44	3		T40	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	16		T17	6		T184	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	14		T26	15		T219	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	6		T44	9		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	7		T155	2		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T200	14		T166	12		T243	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T34	7		T166	5		T244	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	12		T161	10		T338	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T200	11		T158	15		T26	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T37	12		T46	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T11	10		T14	9		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	5		T49	6		T192	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T296	9		T20	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T173	18		T105	12		T284	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	1		T12	1		T51	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T337	12		T257	6		T327	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T3	17		T170	12		T39	21
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T11	11		T16	3		T173	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T32	1		T224	1		T336	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T35	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T156	15		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T155	1		T165	1		T201	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1565	1			T2	1		T6	2		T9	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T192	1		T64	2		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T46	3		T64	1		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T170	4		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	6		T68	10		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	14		T17	14		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T219	7		T247	13		T335	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	7		T44	9		T199	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T11	12		T14	14		T155	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T200	13		T166	10		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	14		T51	1		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	12		T13	13		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T195	1		T158	1		T26	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	1		T37	1		T46	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T11	13		T14	6		T51	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T49	1		T192	1		T155	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T39	13		T98	10		T179	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T11	5		T16	1		T173	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T32	6		T224	14		T336	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T161	15		T200	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T155	1		T165	4		T201	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T2	9		T9	6		T266	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T192	7		T64	4		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T46	6		T64	10		T32	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	7		T67	6		T167	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T68	3		T44	3		T173	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T48	16		T17	6		T184	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T219	6		T247	7		T335	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	6		T44	9		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	7		T14	14		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T200	14		T166	12		T98	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	7		T166	5		T244	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	12		T161	10		T243	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	15		T26	2		T183	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	1		T37	12		T46	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	10		T14	9		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T49	6		T192	13		T155	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T156	1		T157	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T155	2		T26	2		T32	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	10		T6	2		T9	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	8		T192	8		T64	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T32	13		T55	3		T173	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T170	1		T101	1		T67	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T68	4		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T48	17		T17	15		T184	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	15		T164	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	7		T44	10		T199	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	8		T155	3		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T200	15		T166	13		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T51	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	13		T13	1		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T200	12		T158	16		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	2		T37	13		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T3	1		T11	11		T14	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	6		T49	7		T192	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T296	10		T20	7		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T173	19		T105	13		T284	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16541	1			T1	2		T5	11		T7	145
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T66	1		T337	13		T187	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T156	14		T199	13		T161	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	7		T201	12		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T9	5		T54	30		T46	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	10		T219	4		T242	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T32	8		T286	9		T309	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T170	3		T67	4		T167	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	5		T68	9		T44	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	13		T17	5		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	13		T26	5		T219	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	6		T44	8		T199	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	11		T155	19		T56	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T200	12		T166	9		T243	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	13		T160	11		T34	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	11		T13	12		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T200	7		T26	2		T183	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	9		T156	7		T53	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	16		T11	12		T14	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	10		T155	10		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T20	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T173	11		T284	2		T214	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T240	4		T315	15		T302	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T337	3		T187	13		T257	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T3	1		T170	1		T39	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T11	6		T16	3		T173	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T32	7		T224	15		T336	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T35	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	2		T156	1		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T155	2		T165	5		T201	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T2	10		T6	2		T9	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T192	8		T64	6		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	7		T64	11		T32	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	8		T170	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T68	4		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	17		T17	15		T184	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T219	7		T247	8		T335	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	7		T44	10		T199	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	8		T14	15		T155	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T200	15		T166	13		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T51	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	13		T13	1		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T195	1		T158	16		T26	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	2		T37	13		T46	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T11	11		T14	10		T51	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T49	7		T192	14		T155	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T3	16		T170	11		T39	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T11	10		T16	1		T173	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T240	4		T315	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T156	14		T199	13		T161	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T201	12		T173	4		T120	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T9	5		T54	30		T50	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	10		T32	7		T219	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T46	2		T32	8		T286	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T170	3		T67	4		T167	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	5		T68	9		T44	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	13		T17	5		T245	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T219	6		T247	12		T294	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	6		T44	8		T199	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	11		T14	13		T155	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T200	12		T166	9		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	13		T160	11		T34	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	11		T13	12		T161	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T26	2		T183	11		T228	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	9		T156	7		T53	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	12		T14	5		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T155	10		T156	8		T159	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5