Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22229

1

T1

4

T2

10

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

3556

1

T1

24

T9

12

T11

42

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19654

1

T1

26

T5

11

T7

145

auto[1]

6131

1

T1

2

T2

10

T3

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	364	1			T14	13		T156	15		T199	11
values[0]	19	1			T264	15		T259	4		-	-
values[1]	591	1			T11	23		T68	13		T48	30
values[2]	684	1			T1	2		T3	14		T11	19
values[3]	722	1			T1	24		T13	13		T14	15
values[4]	620	1			T3	17		T9	12		T156	8
values[5]	589	1			T13	6		T51	8		T192	14
values[6]	888	1			T12	8		T155	22		T156	9
values[7]	740	1			T52	6		T53	17		T198	10
values[8]	2884	1			T1	2		T2	10		T6	2
values[9]	1192	1			T11	16		T49	7		T170	16
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T3	14		T11	23		T48	30
values[1]	573	1			T1	2		T11	19		T14	15
values[2]	660	1			T1	24		T3	17		T9	12
values[3]	803	1			T51	8		T192	14		T64	11
values[4]	541	1			T13	6		T155	22		T156	9
values[5]	913	1			T12	8		T155	22		T164	1
values[6]	2883	1			T2	10		T6	2		T54	32
values[7]	656	1			T1	2		T14	28		T51	1
values[8]	1271	1			T11	16		T14	13		T49	7
values[9]	168	1			T156	15		T260	1		T261	1
minimum	16673	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	14		T48	14		T64	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	13		T241	17		T248	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	1		T192	1		T200	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	12		T14	6		T199	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	17		T13	13		T46	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	12		T9	6		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T51	5		T192	1		T195	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T64	1		T32	8		T219	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	6		T156	9		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T155	20		T18	2		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T158	1		T39	21		T262	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	1		T155	11		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T2	1		T6	2		T54	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T49	1		T157	1		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T51	1		T161	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	14		T46	10		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T11	11		T49	1		T199	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T14	7		T200	8		T170	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T260	1		T261	1		T339	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T156	15		T269	6		T267	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16387	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T68	10		T33	3		T286	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	16		T64	2		T32	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	10		T40	10		T105	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T1	1		T192	7		T200	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	7		T14	9		T159	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T46	6		T155	1		T200	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	12		T9	6		T37	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T51	3		T192	13		T161	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T64	10		T32	7		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T64	2		T39	8		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T155	2		T340	4		T341	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T158	10		T39	13		T26	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	7		T155	11		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T2	9		T198	4		T266	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T53	6		T26	1		T184	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T161	10		T244	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	14		T46	7		T242	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T11	5		T49	6		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T14	6		T200	11		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T342	14		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T269	6		T267	13		T270	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T51	5		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T68	3		T33	1		T286	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T199	11		T260	1		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T14	7		T156	15		T200	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T264	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T259	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	14		T64	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	13		T68	10		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	1		T3	14		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	12		T199	13		T241	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	13		T46	3		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	12		T14	6		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	17		T156	8		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	6		T26	6		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	6		T51	5		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T155	20		T64	1		T288	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T156	9		T158	1		T39	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T155	11		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T52	6		T198	6		T34	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T53	11		T164	1		T241	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T1	1		T2	1		T6	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	14		T46	10		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T11	11		T49	1		T170	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T170	12		T29	11		T201	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T158	15		T166	12		T234	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T14	6		T200	11		T247	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T264	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T259	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	16		T64	2		T32	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	10		T68	3		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	1		T192	7		T32	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	7		T159	2		T65	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T46	6		T155	1		T200	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	12		T14	9		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T161	16		T184	7		T65	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T9	6		T26	2		T32	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T51	3		T192	13		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T155	2		T64	10		T122	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T158	10		T39	13		T26	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	7		T155	11		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T198	4		T34	2		T173	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T53	6		T26	1		T105	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T1	1		T2	9		T161	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	14		T46	7		T184	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	5		T49	6		T165	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T29	9		T201	10		T242	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T48	17		T64	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	11		T241	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T1	2		T192	8		T200	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	8		T14	10		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T13	1		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	13		T9	7		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T51	5		T192	14		T195	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T64	11		T32	8		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	1		T156	1		T64	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T155	3		T18	2		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T158	11		T39	14		T262	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T12	8		T155	12		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T2	10		T6	2		T54	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T49	1		T157	1		T53	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	2		T51	1		T161	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	15		T46	8		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T11	6		T49	7		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T14	7		T200	12		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T260	1		T261	1		T339	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T156	1		T269	9		T267	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16571	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T68	4		T33	3		T286	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	13		T48	13		T34	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	12		T241	16		T248	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T200	3		T32	8		T242	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	11		T14	5		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	16		T13	12		T46	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	11		T9	5		T44	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T51	3		T161	21		T65	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T32	7		T219	8		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	5		T156	8		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T155	19		T324	11		T340	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T39	20		T262	9		T26	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T155	10		T16	1		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T54	30		T50	40		T271	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T53	5		T241	7		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T161	8		T228	6		T122	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	13		T46	9		T56	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T11	10		T199	10		T170	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T14	6		T200	7		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T272	13		T342	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T156	14		T269	3		T267	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T343	13		T264	2		T187	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T68	9		T33	1		T286	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T199	1		T260	1		T158	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	7		T156	1		T200	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T264	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T259	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	17		T64	3		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	11		T68	4		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	2		T3	1		T192	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	8		T199	1		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	1		T46	7		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	13		T14	10		T37	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	1		T156	1		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	7		T26	6		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T51	5		T192	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T155	3		T64	11		T288	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T156	1		T158	11		T39	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	8		T155	12		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T52	5		T198	5		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T53	12		T164	1		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T1	2		T2	10		T6	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	15		T46	8		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T11	6		T49	7		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T170	1		T29	10		T201	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T199	10		T166	9		T344	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T14	6		T156	14		T200	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T264	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	13		T243	8		T67	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	12		T68	9		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	13		T32	8		T34	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	11		T199	12		T241	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	12		T46	2		T200	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	11		T14	5		T44	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	16		T156	7		T161	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T9	5		T26	2		T32	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	5		T51	3		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T155	19		T122	12		T177	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T156	8		T39	20		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T155	10		T16	1		T166	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T52	1		T198	5		T34	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T53	5		T241	7		T250	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T54	30		T50	40		T271	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	13		T46	9		T56	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	10		T170	3		T219	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T170	11		T29	10		T201	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5