Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21964

1

T1

24

T2

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3821

1

T1

4

T3

31

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19156

1

T3

14

T5

11

T7

140

auto[1]

6629

1

T1

28

T2

10

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	705	1			T1	2		T7	5		T44	6
values[0]	60	1			T48	30		T161	8		T260	1
values[1]	755	1			T1	24		T12	8		T44	18
values[2]	3030	1			T2	10		T3	14		T6	2
values[3]	567	1			T159	5		T173	5		T184	18
values[4]	758	1			T9	12		T51	9		T44	7
values[5]	588	1			T11	23		T56	11		T160	13
values[6]	684	1			T46	17		T64	14		T199	11
values[7]	749	1			T13	13		T156	15		T200	30
values[8]	791	1			T1	2		T3	17		T37	13
values[9]	1051	1			T14	56		T68	13		T52	6
minimum	16047	1			T5	11		T7	140		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	896	1			T11	35		T12	8		T44	18
values[1]	2870	1			T2	10		T3	14		T6	2
values[2]	670	1			T9	12		T51	9		T49	7
values[3]	714	1			T11	23		T44	7		T160	12
values[4]	583	1			T56	11		T64	11		T160	1
values[5]	724	1			T46	17		T156	15		T64	3
values[6]	793	1			T3	17		T13	13		T199	14
values[7]	777	1			T1	2		T14	28		T37	13
values[8]	993	1			T1	2		T14	28		T68	13
values[9]	98	1			T100	1		T66	9		T238	1
minimum	16667	1			T1	24		T5	11		T7	145

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	23		T161	7		T200	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	1		T44	9		T46	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	1		T6	2		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	14		T39	21		T201	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T51	6		T49	1		T241	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T9	6		T164	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	13		T288	1		T247	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T44	4		T160	12		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T56	11		T244	1		T17	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T64	1		T160	1		T241	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	10		T156	15		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T199	11		T158	1		T32	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	13		T101	1		T210	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	17		T199	14		T200	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	13		T157	1		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	1		T37	1		T192	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T68	10		T155	20		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T1	1		T14	14		T155	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T100	1		T66	5		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T302	12		T300	13		T292	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16401	1			T1	12		T5	11		T7	145
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T128	1		T293	1		T349	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	12		T161	1		T200	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	7		T44	9		T46	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T2	9		T155	1		T266	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	13		T201	10		T67	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	3		T49	6		T159	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	6		T184	16		T243	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	10		T247	7		T243	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T44	3		T198	4		T39	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T244	6		T17	6		T122	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T64	10		T219	6		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T46	7		T64	2		T200	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T158	15		T32	12		T285	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T210	12		T245	1		T253	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T200	11		T289	8		T173	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	15		T53	6		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T37	12		T192	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T68	3		T155	2		T64	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T14	14		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T66	4		T301	5		T323	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T300	16		T292	6		T327	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	12		T12	1		T51	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T293	7		T349	12		T246	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	552	1			T7	5		T44	6		T70	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T1	1		T155	11		T123	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T161	7		T260	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T48	14		T293	1		T294	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	12		T183	12		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T44	9		T26	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T2	1		T6	2		T11	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	14		T46	3		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T159	3		T173	5		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T184	2		T243	14		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T51	6		T49	1		T241	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T9	6		T44	4		T198	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	13		T56	11		T243	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T160	13		T219	7		T98	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	10		T64	1		T244	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T64	1		T199	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	13		T156	15		T200	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T200	8		T219	9		T289	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T157	1		T53	11		T161	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	1		T3	17		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T14	13		T68	10		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T14	14		T52	6		T199	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15902	1			T5	11		T7	140		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T155	2		T64	2		T120	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T1	1		T155	11		T123	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T161	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T48	16		T293	7		T294	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	12		T183	11		T40	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	7		T44	9		T26	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T2	9		T11	12		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	6		T161	15		T39	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T159	2		T224	14		T254	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T184	16		T243	10		T105	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T51	3		T49	6		T247	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	6		T44	3		T198	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	10		T243	5		T122	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T219	6		T98	11		T286	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	7		T64	2		T244	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T64	10		T158	15		T32	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T200	7		T32	6		T210	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T200	11		T289	8		T173	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T53	6		T161	10		T158	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T37	12		T192	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	15		T68	3		T32	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	14		T34	2		T165	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	14		T161	2		T200	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T12	8		T44	10		T46	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T2	10		T6	2		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T39	14		T201	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T51	6		T49	7		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	7		T164	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	11		T288	1		T247	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	4		T160	1		T198	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T56	1		T244	7		T17	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T64	11		T160	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	8		T156	1		T64	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T199	1		T158	16		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	1		T101	1		T210	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T199	1		T200	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	17		T157	1		T53	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	2		T37	13		T192	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T68	4		T155	3		T64	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T1	2		T14	15		T155	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T100	1		T66	5		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T302	1		T300	17		T292	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16541	1			T1	13		T5	11		T7	145
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T128	1		T293	8		T349	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	21		T161	6		T200	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T44	8		T46	2		T48	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T13	5		T54	30		T50	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	13		T39	20		T201	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T51	3		T241	7		T159	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T9	5		T243	13		T298	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	12		T247	12		T243	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	3		T160	11		T198	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T56	10		T17	5		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T241	16		T219	6		T286	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T46	9		T156	14		T200	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T199	10		T32	8		T219	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	12		T210	11		T245	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	16		T199	13		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	11		T53	5		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T199	12		T170	14		T34	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T68	9		T155	19		T32	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	13		T155	10		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T66	4		T301	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T302	11		T300	12		T292	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T1	11		T265	12		T21	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T188	12		T257	5		T290	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	517	1			T7	5		T44	6		T70	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T1	2		T155	12		T123	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T161	2		T260	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T48	17		T293	8		T294	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	13		T183	12		T40	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	8		T44	10		T26	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T2	10		T6	2		T11	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	1		T46	7		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T159	3		T173	1		T224	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T184	18		T243	11		T105	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T51	6		T49	7		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	7		T44	4		T198	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	11		T56	1		T243	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T160	2		T219	7		T98	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T46	8		T64	3		T244	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T64	11		T199	1		T158	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T156	1		T200	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T200	12		T219	1		T289	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T157	1		T53	12		T161	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	2		T3	1		T37	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T14	17		T68	4		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T14	15		T52	5		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16047	1			T5	11		T7	140		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T155	19		T120	11		T302	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T155	10		T123	2		T300	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T161	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T48	13		T294	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	11		T183	11		T265	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T44	8		T26	5		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T11	21		T13	5		T54	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	13		T46	2		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T159	2		T173	4		T254	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T243	13		T67	4		T284	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	3		T241	7		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	5		T44	3		T198	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	12		T56	10		T243	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T160	11		T219	6		T286	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	9		T244	13		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T199	10		T32	8		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	12		T156	14		T200	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T200	7		T219	8		T173	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T53	5		T161	8		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	16		T199	13		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	11		T68	9		T32	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T14	13		T52	1		T199	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5