Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22213

1

T1

4

T2

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3572

1

T1

24

T3

31

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T1

4

T3

17

T5

11

auto[1]

6174

1

T1

24

T2

10

T3

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	362	1			T155	22		T16	4		T201	11
values[0]	66	1			T184	10		T300	29		T307	7
values[1]	879	1			T14	15		T44	18		T46	17
values[2]	620	1			T14	28		T37	13		T48	30
values[3]	664	1			T9	12		T49	1		T161	31
values[4]	679	1			T1	2		T11	19		T46	9
values[5]	3237	1			T1	24		T2	10		T6	2
values[6]	656	1			T1	2		T14	13		T51	9
values[7]	659	1			T3	14		T12	8		T155	2
values[8]	660	1			T13	19		T68	13		T44	7
values[9]	811	1			T3	17		T52	6		T64	3
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	708	1			T37	13		T46	17		T49	7
values[1]	577	1			T14	28		T44	18		T48	30
values[2]	670	1			T9	12		T11	19		T161	31
values[3]	3023	1			T1	26		T2	10		T6	2
values[4]	917	1			T11	39		T155	22		T64	3
values[5]	725	1			T1	2		T3	14		T12	8
values[6]	654	1			T13	19		T155	2		T157	1
values[7]	624	1			T68	13		T44	7		T192	14
values[8]	864	1			T3	17		T52	6		T160	1
values[9]	121	1			T155	22		T64	3		T33	4
minimum	16902	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T37	1		T49	1		T56	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T46	10		T170	12		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	14		T48	14		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T44	9		T165	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T161	16		T158	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	6		T11	12		T166	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T1	1		T2	1		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	12		T156	9		T200	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	11		T200	13		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	13		T155	20		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T14	7		T51	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	14		T12	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T13	19		T157	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T155	1		T199	27		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T44	4		T156	15		T170	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T68	10		T192	1		T242	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T52	6		T160	1		T262	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T3	17		T164	1		T241	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T155	11		T64	1		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T201	1		T294	6		T350	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T161	7		T248	15		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	12		T49	6		T198	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T46	7		T26	1		T201	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	14		T48	16		T39	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T44	9		T165	7		T98	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T161	15		T158	15		T173	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	6		T11	7		T166	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T1	1		T2	9		T46	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	12		T200	11		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	5		T200	14		T286	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	10		T155	2		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	1		T14	6		T51	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	7		T158	10		T26	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T165	4		T285	13		T118	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T155	1		T244	16		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T44	3		T253	15		T294	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T68	3		T192	13		T242	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	1		T242	14		T17	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T26	15		T32	6		T173	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T155	11		T64	2		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T201	10		T294	7		T306	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	1		T14	9		T51	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T161	1		T289	8		T184	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T155	11		T16	3		T17	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T201	1		T173	12		T250	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T300	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T184	1		T307	4		T194	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T14	6		T49	1		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T44	9		T46	10		T161	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	14		T37	1		T48	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T165	1		T201	13		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	1		T161	16		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	6		T166	17		T183	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T46	3		T159	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	12		T165	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1690	1			T2	1		T6	2		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	12		T11	13		T155	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T14	7		T51	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T51	1		T53	11		T199	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T157	1		T34	22		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	14		T12	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	19		T44	4		T156	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T68	10		T192	1		T199	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T52	6		T64	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T3	17		T164	1		T241	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T155	11		T16	1		T17	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T201	10		T173	18		T319	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T300	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T184	9		T307	3		T194	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	9		T49	6		T184	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	9		T46	7		T161	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	14		T37	12		T48	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T165	7		T201	10		T98	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T161	15		T158	15		T105	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	6		T166	17		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T1	1		T46	6		T159	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	7		T165	10		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T2	9		T11	5		T192	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	12		T11	10		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T14	6		T51	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	6		T158	10		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	9		T165	4		T228	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	7		T155	1		T26	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T44	3		T253	15		T254	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T68	3		T192	13		T242	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T64	2		T33	1		T242	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T26	15		T32	6		T65	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T37	13		T49	7		T56	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T46	8		T170	1		T26	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	15		T48	17		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T44	10		T165	8		T98	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T161	16		T158	16		T173	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T9	7		T11	8		T166	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T1	2		T2	10		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	13		T156	1		T200	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	6		T200	15		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	11		T155	3		T64	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	2		T14	7		T51	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	1		T12	8		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	2		T157	1		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T155	2		T199	2		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	4		T156	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T68	4		T192	14		T242	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T52	5		T160	1		T262	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T164	1		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T155	12		T64	3		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T201	11		T294	8		T350	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16597	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T161	2		T248	1		T289	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T56	10		T198	5		T243	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T46	9		T170	11		T201	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	13		T48	13		T156	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T44	8		T250	13		T351	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T161	15		T305	4		T193	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	5		T11	11		T166	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T54	30		T46	2		T50	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	11		T156	8		T200	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	10		T200	12		T286	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	12		T155	19		T53	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	6		T51	3		T200	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	13		T26	2		T32	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	17		T219	8		T285	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T199	25		T244	13		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T44	3		T156	14		T170	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T68	9		T242	18		T309	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T52	1		T262	9		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	16		T241	16		T26	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T155	10		T33	1		T273	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T294	5		T352	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T14	5		T160	11		T123	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T161	6		T248	14		T265	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T155	12		T16	3		T17	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T201	11		T173	19		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T300	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T184	10		T307	5		T194	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	10		T49	7		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T44	10		T46	8		T161	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	15		T37	13		T48	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T165	8		T201	11		T98	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	1		T161	16		T158	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	7		T166	19		T183	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	2		T46	7		T159	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	8		T165	11		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T2	10		T6	2		T11	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	13		T11	11		T155	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	2		T14	7		T51	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	1		T53	12		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T157	1		T34	11		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T12	8		T155	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	2		T44	4		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T68	4		T192	14		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T52	5		T64	3		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	1		T164	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T155	10		T16	1		T17	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T173	11		T250	10		T319	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T300	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T307	2		T194	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	5		T160	11		T243	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T44	8		T46	9		T161	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	13		T48	13		T156	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T201	12		T250	13		T310	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T161	15		T120	16		T193	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	5		T166	15		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T46	2		T159	2		T173	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	11		T66	4		T167	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T11	10		T54	30		T50	40
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	11		T11	12		T155	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	6		T51	3		T200	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T53	5		T199	10		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T34	20		T219	8		T285	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	13		T199	12		T26	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	17		T44	3		T156	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T68	9		T199	13		T242	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T52	1		T262	9		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	16		T241	16		T26	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5