Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20043

1

T1

2

T3

31

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

5742

1

T1

26

T2

10

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20153

1

T1

28

T5

11

T7

145

auto[1]

5632

1

T2

10

T3

31

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	284	1			T14	28		T242	24		T105	3
values[0]	69	1			T49	7		T158	1		T167	35
values[1]	635	1			T155	22		T52	6		T56	11
values[2]	685	1			T9	12		T49	1		T199	14
values[3]	632	1			T1	26		T64	11		T219	19
values[4]	756	1			T12	8		T13	13		T14	28
values[5]	710	1			T3	17		T51	1		T44	18
values[6]	776	1			T13	6		T156	9		T160	1
values[7]	634	1			T3	14		T11	35		T51	8
values[8]	810	1			T11	23		T68	13		T199	13
values[9]	3302	1			T1	2		T2	10		T6	2
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	568	1			T49	1		T52	6		T56	11
values[1]	2985	1			T2	10		T6	2		T9	12
values[2]	589	1			T1	2		T12	8		T64	11
values[3]	845	1			T1	24		T13	13		T14	28
values[4]	615	1			T3	17		T51	1		T46	9
values[5]	799	1			T13	6		T156	9		T160	1
values[6]	655	1			T3	14		T11	35		T51	8
values[7]	825	1			T11	23		T68	13		T156	8
values[8]	1030	1			T14	28		T44	7		T46	17
values[9]	109	1			T1	2		T192	8		T164	1
minimum	16765	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	1		T56	11		T34	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T52	6		T64	1		T161	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T199	14		T26	6		T34	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1610	1			T2	1		T6	2		T9	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T12	1		T201	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T64	1		T219	5		T319	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	13		T14	13		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	12		T200	4		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	17		T51	1		T46	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T64	1		T26	8		T243	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T160	1		T157	1		T199	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T13	6		T156	9		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	14		T11	12		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	11		T51	5		T48	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	13		T68	10		T39	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T156	8		T53	11		T200	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T14	14		T44	4		T46	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T161	16		T170	4		T262	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T353	1		T301	10		T332	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T1	1		T192	1		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16392	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T155	11		T243	14		T167	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T34	7		T165	4		T247	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T64	2		T161	1		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T26	2		T34	2		T165	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	987	1			T2	9		T9	6		T266	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T12	7		T201	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T64	10		T219	14		T319	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	15		T37	12		T44	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	12		T200	7		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	6		T198	4		T26	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T64	2		T26	15		T243	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T40	11		T286	10		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T32	6		T166	12		T244	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	7		T155	1		T161	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	5		T51	3		T48	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	10		T68	3		T39	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T53	6		T200	11		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	14		T44	3		T46	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T161	15		T165	7		T242	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T301	5		T320	11		T354	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T1	1		T192	7		T336	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T51	5		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T155	11		T243	10		T167	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T14	14		T105	1		T355	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T242	10		T263	1		T336	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T49	1		T287	10		T290	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T158	1		T167	18		T305	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	11		T16	3		T34	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T155	11		T52	6		T64	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	1		T199	14		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	6		T158	1		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T98	1		T210	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	12		T64	1		T219	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	1		T13	13		T14	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T200	4		T164	1		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	17		T51	1		T44	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T64	1		T243	6		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T160	1		T157	1		T199	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T13	6		T156	9		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	14		T11	12		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	11		T51	5		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	13		T68	10		T199	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T200	8		T170	12		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T44	4		T46	10		T155	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1661	1			T1	1		T2	1		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T14	14		T105	2		T340	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T242	14		T336	11		T20	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T49	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T167	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T16	1		T34	7		T247	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T155	11		T64	2		T161	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	2		T34	2		T165	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	6		T158	15		T32	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T98	10		T210	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	12		T64	10		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	7		T14	15		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T200	7		T29	9		T173	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	9		T46	6		T198	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T64	2		T243	5		T193	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T40	11		T243	8		T286	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	15		T166	12		T65	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	7		T155	1		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	5		T51	3		T48	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	10		T68	3		T39	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T200	11		T33	1		T224	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T44	3		T46	7		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1022	1			T1	1		T2	9		T192	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	1		T56	1		T34	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	5		T64	3		T161	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T199	1		T26	6		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1343	1			T2	10		T6	2		T9	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	2		T12	8		T201	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T64	11		T219	15		T319	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T14	17		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	13		T200	8		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T51	1		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T64	3		T26	18		T243	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T160	1		T157	1		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T13	1		T156	1		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T11	8		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	6		T51	5		T48	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	11		T68	4		T39	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T156	1		T53	12		T200	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	15		T44	4		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T161	16		T170	1		T262	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T353	1		T301	11		T332	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T1	2		T192	8		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16563	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T155	12		T243	11		T167	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T56	10		T34	9		T247	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T52	1		T161	6		T219	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T199	13		T26	2		T34	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1254	1			T9	5		T54	30		T50	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T201	12		T309	13		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T219	4		T319	1		T324	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	12		T14	11		T44	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	11		T200	3		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	16		T46	2		T198	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T26	5		T243	5		T299	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T199	10		T286	9		T284	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	5		T156	8		T241	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	13		T11	11		T199	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	10		T51	3		T48	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	12		T68	9		T39	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T156	7		T53	5		T200	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T14	13		T44	3		T46	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T161	15		T170	3		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T301	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T327	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T16	1		T254	9		T287	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T155	10		T243	13		T167	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T14	15		T105	3		T355	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T242	15		T263	1		T336	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T49	7		T287	1		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T158	1		T167	18		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T56	1		T16	3		T34	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T155	12		T52	5		T64	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T49	1		T199	1		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	7		T158	16		T32	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	2		T98	11		T210	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	13		T64	11		T219	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	8		T13	1		T14	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T200	8		T164	1		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	1		T51	1		T44	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T64	3		T243	6		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T160	1		T157	1		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	1		T156	1		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T11	8		T155	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	6		T51	5		T48	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	11		T68	4		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T200	12		T170	1		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T44	4		T46	8		T155	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1377	1			T1	2		T2	10		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T14	13		T340	9		T291	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T242	9		T303	10		T356	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T287	9		T290	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T167	17		T305	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T56	10		T16	1		T34	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T155	10		T52	1		T161	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T199	13		T26	2		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	5		T32	8		T17	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T210	11		T120	11		T254	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	11		T219	4		T118	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	12		T14	11		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T200	3		T29	10		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	16		T44	8		T46	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T243	5		T193	15		T251	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T199	10		T243	8		T286	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	5		T156	8		T241	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	13		T11	11		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	10		T51	3		T48	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	12		T68	9		T199	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T200	7		T170	11		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T44	3		T46	9		T155	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1306	1			T54	30		T50	40		T271	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5