Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T48	17		T64	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	11		T68	4		T159	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T200	8		T32	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	8		T14	10		T192	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T46	7		T155	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	13		T9	7		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T51	5		T192	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T64	11		T32	8		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T156	1		T64	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T155	15		T219	15		T201	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T158	11		T39	14		T26	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	8		T164	1		T262	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T2	10		T6	2		T54	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	1		T157	1		T53	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	2		T51	1		T198	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	15		T46	8		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T11	6		T49	7		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T14	7		T195	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T260	1		T261	1		T193	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T156	1		T263	1		T264	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16507	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	13		T48	13		T241	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	12		T68	9		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T200	3		T32	8		T34	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	11		T14	5		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	12		T46	2		T156	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	11		T9	5		T44	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	16		T51	3		T161	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T32	7		T219	8		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	5		T156	8		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T155	29		T219	4		T166	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	20		T26	5		T34	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T262	9		T16	1		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T54	30		T50	40		T271	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T53	5		T241	7		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T198	5		T161	8		T170	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	13		T46	9		T56	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T11	10		T199	10		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T14	6		T199	13		T200	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T193	3		T272	13		T267	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T156	14		T264	5		T269	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T264	2		T187	4		T273	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T255	7		T256	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T257	7		T259	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	17		T64	3		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	11		T68	4		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	2		T3	1		T155	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	8		T192	8		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T46	7		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	13		T14	10		T37	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	1		T156	1		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	7		T26	6		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	5		T192	14		T64	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T155	3		T64	11		T166	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	1		T156	1		T158	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T155	12		T262	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T52	5		T198	5		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	8		T49	1		T53	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T1	2		T2	10		T6	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	15		T46	8		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T11	6		T49	7		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	438	1			T14	7		T156	1		T200	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T255	2		T256	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T257	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	13		T243	8		T67	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	12		T68	9		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	13		T200	3		T241	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	11		T199	12		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	12		T46	2		T200	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	11		T14	5		T44	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	16		T156	7		T161	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T9	5		T26	2		T32	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	3		T160	11		T120	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T155	19		T166	6		T122	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	5		T156	8		T39	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T155	10		T262	9		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T52	1		T198	5		T34	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	5		T241	7		T243	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T54	30		T50	40		T271	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	13		T46	9		T56	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T11	10		T199	10		T170	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T14	6		T156	14		T200	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5