Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22185

1

T2

10

T3

31

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3600

1

T1

28

T11

16

T14

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19204

1

T1

4

T3

14

T5

11

auto[1]

6581

1

T1

24

T2

10

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T274	1		T275	1		T276	1
values[0]	24	1			T277	10		T278	2		T279	12
values[1]	607	1			T11	23		T51	1		T192	14
values[2]	661	1			T3	17		T12	8		T44	18
values[3]	903	1			T3	14		T9	12		T46	26
values[4]	3020	1			T2	10		T6	2		T11	16
values[5]	886	1			T14	15		T37	13		T155	2
values[6]	644	1			T13	13		T14	13		T44	7
values[7]	605	1			T49	1		T155	22		T156	15
values[8]	689	1			T1	24		T11	19		T14	28
values[9]	1251	1			T1	4		T13	6		T51	8
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	811	1			T11	23		T12	8		T51	1
values[1]	674	1			T3	31		T44	18		T46	9
values[2]	822	1			T9	12		T46	17		T64	3
values[3]	3193	1			T2	10		T6	2		T11	16
values[4]	758	1			T14	13		T44	7		T192	8
values[5]	688	1			T158	11		T159	5		T26	8
values[6]	627	1			T11	19		T13	13		T14	28
values[7]	697	1			T1	24		T164	1		T244	37
values[8]	823	1			T1	4		T13	6		T51	8
values[9]	188	1			T39	34		T280	5		T203	20
minimum	16504	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	13		T12	1		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	14		T49	1		T161	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	31		T160	1		T39	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	9		T46	3		T52	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	6		T200	8		T170	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	10		T64	1		T262	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1701	1			T2	1		T6	2		T14	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	11		T156	8		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T64	1		T198	6		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T14	7		T44	4		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T171	1		T18	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T158	1		T159	3		T26	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	12		T13	13		T14	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T157	1		T200	4		T26	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T164	1		T244	15		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	12		T243	14		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	6		T53	11		T248	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T1	2		T51	5		T199	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T39	21		T203	11		T41	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T280	4		T281	3		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16359	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	10		T12	7		T192	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	16		T49	6		T161	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	8		T165	4		T242	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T44	9		T46	6		T17	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	6		T200	11		T32	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	7		T64	2		T173	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T2	9		T14	9		T68	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	5		T64	10		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T64	2		T198	4		T26	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	6		T44	3		T192	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T105	2		T67	6		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T158	10		T159	2		T26	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	7		T14	14		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T200	7		T26	15		T282	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T244	22		T66	4		T265	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	12		T243	10		T261	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T53	6		T105	12		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	2		T51	3		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T39	13		T203	9		T41	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T280	1		T281	16		T283	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T274	1		T275	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T277	5		T278	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	13		T51	1		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T161	9		T158	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	17		T12	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T44	9		T48	14		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T3	14		T9	6		T200	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	13		T156	8		T52	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T2	1		T6	2		T54	32
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	11		T64	2		T160	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	6		T37	1		T56	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T155	1		T195	1		T161	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	13		T260	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	7		T44	4		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	1		T155	20		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T157	1		T200	4		T26	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	12		T14	14		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	12		T238	1		T261	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T13	6		T53	11		T39	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T1	2		T51	5		T199	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T277	5		T278	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	10		T192	13		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T161	10		T33	1		T284	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	7		T39	8		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T44	9		T48	16		T49	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	6		T200	11		T32	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	13		T173	1		T184	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T2	9		T68	3		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	5		T64	12		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	9		T37	12		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T155	1		T161	15		T158	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	1		T105	12		T67	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	6		T44	3		T192	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T155	2		T200	14		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T200	7		T26	17		T242	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	7		T14	14		T219	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	12		T261	4		T284	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T53	6		T39	13		T105	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T1	2		T51	3		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	11		T12	8		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T48	17		T49	7		T161	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	2		T160	1		T39	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	10		T46	7		T52	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	7		T200	12		T170	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T46	8		T64	3		T262	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T2	10		T6	2		T14	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	6		T156	1		T64	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T64	3		T198	5		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	7		T44	4		T192	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T171	1		T18	1		T105	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T158	11		T159	3		T26	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	8		T13	1		T14	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T157	1		T200	8		T26	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T164	1		T244	24		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	13		T243	11		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T53	12		T248	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	4		T51	5		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T39	14		T203	10		T41	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T280	4		T281	17		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16493	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	12		T155	10		T201	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	13		T161	8		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	29		T39	9		T242	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	8		T46	2		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	5		T200	7		T170	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	9		T262	9		T285	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T14	5		T54	30		T68	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	10		T156	7		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T198	5		T241	16		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	6		T44	3		T199	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T67	4		T286	2		T265	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T159	2		T26	2		T34	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	11		T13	12		T14	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T200	3		T26	5		T282	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T244	13		T66	4		T265	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	11		T243	13		T284	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	5		T53	5		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T51	3		T199	13		T241	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T39	20		T203	10		T41	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T280	1		T281	2		T283	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T287	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T274	1		T275	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T277	6		T278	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	11		T51	1		T192	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T161	11		T158	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T12	8		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T44	10		T48	17		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T3	1		T9	7		T200	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T46	15		T156	1		T52	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	10		T6	2		T54	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	6		T64	14		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	10		T37	13		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T155	2		T195	1		T161	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T260	1		T26	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	7		T44	4		T192	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	1		T155	3		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T157	1		T200	8		T26	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	8		T14	15		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	13		T238	1		T261	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	1		T53	12		T39	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T1	4		T51	5		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T279	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T277	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	12		T155	10		T201	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T161	8		T33	1		T284	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	16		T170	3		T39	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T44	8		T48	13		T17	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	13		T9	5		T200	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	11		T156	7		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T54	30		T68	9		T50	40
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	10		T160	11		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	5		T56	10		T198	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T161	15		T183	11		T167	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	12		T67	4		T265	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	6		T44	3		T199	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T155	19		T156	14		T200	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T200	3		T26	7		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	11		T14	13		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	11		T284	12		T122	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	5		T53	5		T39	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T51	3		T199	13		T241	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5