Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22194

1

T1

26

T2

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3591

1

T1

2

T3

31

T11

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19080

1

T1

24

T3

14

T5

11

auto[1]

6705

1

T1

4

T2

10

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	457	1			T7	5		T44	6		T70	1
values[0]	114	1			T48	30		T161	8		T260	1
values[1]	725	1			T1	24		T3	14		T12	8
values[2]	3001	1			T2	10		T6	2		T11	35
values[3]	569	1			T159	5		T173	5		T184	18
values[4]	716	1			T9	12		T51	9		T44	7
values[5]	652	1			T11	23		T56	11		T160	12
values[6]	663	1			T46	17		T64	14		T160	1
values[7]	720	1			T13	13		T156	15		T161	19
values[8]	877	1			T1	2		T3	17		T14	28
values[9]	1244	1			T1	2		T14	28		T68	13
minimum	16047	1			T5	11		T7	140		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1065	1			T1	24		T11	35		T12	8
values[1]	2875	1			T2	10		T3	14		T6	2
values[2]	637	1			T9	12		T51	9		T44	7
values[3]	736	1			T11	23		T49	7		T160	12
values[4]	609	1			T56	11		T64	11		T160	1
values[5]	678	1			T46	17		T156	15		T64	3
values[6]	751	1			T3	17		T13	13		T199	14
values[7]	820	1			T1	2		T14	28		T37	13
values[8]	905	1			T14	28		T68	13		T155	44
values[9]	205	1			T1	2		T166	26		T247	15
minimum	16504	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	12		T46	3		T48	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T11	23		T12	1		T44	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T2	1		T6	2		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	14		T49	1		T156	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	6		T51	6		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	4		T26	6		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	13		T198	6		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T49	1		T160	12		T241	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	11		T160	1		T17	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T64	1		T219	7		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	10		T156	15		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T199	11		T200	4		T32	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	13		T289	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	17		T199	14		T161	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	13		T157	1		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T1	1		T37	1		T192	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T68	10		T52	6		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T14	14		T155	31		T262	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T1	1		T100	1		T185	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T166	15		T247	8		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T290	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T1	12		T46	6		T48	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	12		T12	7		T44	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T2	9		T155	1		T266	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	13		T201	10		T284	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	6		T51	3		T219	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T44	3		T26	2		T184	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	10		T198	4		T247	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T49	6		T39	8		T184	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	6		T40	11		T98	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T64	10		T219	6		T244	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	7		T64	2		T158	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T200	7		T32	12		T167	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T289	8		T210	12		T245	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T161	10		T200	11		T173	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	15		T53	6		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T37	12		T192	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T68	3		T64	2		T165	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	14		T155	13		T165	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T1	1		T185	8		T291	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T166	11		T247	7		T292	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	457	1			T7	5		T44	6		T70	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T48	14		T161	7		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T293	1		T294	6		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	12		T33	3		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	14		T12	1		T44	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T2	1		T6	2		T13	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	23		T49	1		T156	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T159	3		T173	5		T243	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T184	2		T105	1		T284	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	6		T51	6		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T44	4		T49	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	13		T56	11		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T160	12		T241	17		T286	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	10		T64	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T64	1		T199	11		T32	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	13		T156	15		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T161	9		T200	4		T219	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T53	11		T170	4		T295	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T1	1		T3	17		T14	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T1	1		T14	13		T68	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T155	31		T262	10		T34	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15902	1			T5	11		T7	140		T8	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T48	16		T161	1		T34	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T293	7		T294	7		T258	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	12		T33	1		T165	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	7		T44	9		T26	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T2	9		T46	6		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	12		T161	15		T39	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T159	2		T243	10		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T184	16		T105	12		T284	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	6		T51	3		T198	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T44	3		T49	6		T39	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	10		T40	11		T243	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T286	10		T296	8		T297	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	7		T64	2		T158	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T64	10		T32	12		T219	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T32	6		T289	8		T210	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T161	10		T200	7		T167	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T53	6		T158	10		T166	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	1		T14	14		T37	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T1	1		T14	15		T68	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T155	13		T34	2		T165	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T1	13		T46	7		T48	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T11	14		T12	8		T44	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T2	10		T6	2		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	1		T49	1		T156	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	7		T51	6		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	4		T26	6		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	11		T198	5		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	7		T160	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T56	1		T160	1		T17	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T64	11		T219	7		T244	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	8		T156	1		T64	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T199	1		T200	8		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	1		T289	9		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T199	1		T161	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	17		T157	1		T53	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	2		T37	13		T192	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T68	4		T52	5		T64	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	15		T155	15		T262	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T1	2		T100	1		T185	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T166	12		T247	8		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	11		T46	2		T48	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	21		T44	8		T161	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T13	5		T54	30		T50	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	13		T156	15		T39	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	5		T51	3		T241	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T44	3		T26	2		T298	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	12		T198	5		T247	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T160	11		T241	16		T39	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T56	10		T17	5		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T219	6		T286	9		T299	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T46	9		T156	14		T244	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T199	10		T200	3		T32	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	12		T210	11		T245	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	16		T199	13		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	11		T53	5		T170	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T199	12		T170	11		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T68	9		T52	1		T242	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	13		T155	29		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T185	8		T300	12		T301	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T166	14		T247	7		T302	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T290	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	447	1			T7	5		T44	6		T70	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T48	17		T161	2		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T293	8		T294	8		T258	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	13		T33	3		T165	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T12	8		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T2	10		T6	2		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	14		T49	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T159	3		T173	1		T243	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T184	18		T105	13		T284	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	7		T51	6		T198	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T44	4		T49	7		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	11		T56	1		T40	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T160	1		T241	1		T286	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T46	8		T64	3		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T64	11		T199	1		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T156	1		T32	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T161	11		T200	8		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T53	12		T170	1		T295	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	2		T3	1		T14	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T1	2		T14	17		T68	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T155	15		T262	1		T34	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16047	1			T5	11		T7	140		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T290	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T48	13		T161	6		T34	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T294	5		T303	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T1	11		T33	1		T183	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	13		T44	8		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T13	5		T54	30		T46	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	21		T156	7		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T159	2		T173	4		T243	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T284	12		T280	1		T304	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	5		T51	3		T198	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T44	3		T39	9		T26	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	12		T56	10		T243	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T160	11		T241	16		T286	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	9		T244	13		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T199	10		T32	8		T219	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	12		T156	14		T210	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T161	8		T200	3		T219	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T53	5		T170	3		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	16		T14	13		T199	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	11		T68	9		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T155	29		T262	9		T34	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5