Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22213

1

T1

4

T2

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3572

1

T1

24

T3

31

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T1

4

T3

17

T5

11

auto[1]

6174

1

T1

24

T2

10

T3

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T201	11		T18	1		T265	19
values[0]	93	1			T184	10		T210	27		T300	29
values[1]	831	1			T14	15		T44	18		T46	17
values[2]	618	1			T14	28		T37	13		T156	8
values[3]	705	1			T9	12		T48	30		T49	1
values[4]	740	1			T1	2		T11	19		T46	9
values[5]	3194	1			T1	24		T2	10		T6	2
values[6]	674	1			T1	2		T51	9		T64	11
values[7]	651	1			T3	14		T12	8		T14	13
values[8]	559	1			T13	19		T68	13		T192	14
values[9]	1193	1			T3	17		T155	22		T52	6
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1087	1			T14	15		T37	13		T46	17
values[1]	700	1			T14	28		T44	18		T48	30
values[2]	503	1			T11	19		T166	12		T98	12
values[3]	3145	1			T1	26		T2	10		T6	2
values[4]	854	1			T11	16		T155	22		T64	3
values[5]	706	1			T1	2		T3	14		T12	8
values[6]	738	1			T13	19		T155	2		T156	15
values[7]	542	1			T68	13		T44	7		T192	14
values[8]	850	1			T3	17		T52	6		T160	1
values[9]	166	1			T155	22		T64	3		T158	1
minimum	16494	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T14	6		T37	1		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T46	10		T161	7		T170	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	14		T48	14		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T44	9		T165	1		T166	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T101	1		T105	1		T305	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	12		T166	7		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T1	1		T2	1		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T1	12		T9	6		T11	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	11		T200	13		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T155	20		T64	1		T53	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T14	7		T51	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	14		T12	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T13	19		T156	15		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T155	1		T199	27		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	4		T170	4		T101	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T68	10		T192	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T52	6		T160	1		T262	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	17		T164	1		T241	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T155	11		T64	1		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T158	1		T201	1		T250	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16348	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T14	9		T37	12		T49	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	7		T161	1		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	14		T48	16		T161	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T44	9		T165	7		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T105	12		T193	1		T281	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	7		T166	5		T98	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T1	1		T2	9		T46	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	12		T9	6		T11	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	5		T200	14		T238	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T155	2		T64	2		T53	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T14	6		T51	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	7		T26	2		T32	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	7		T228	1		T285	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T155	1		T242	21		T244	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T44	3		T253	15		T294	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T68	3		T192	13		T40	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	1		T17	6		T243	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	15		T32	6		T173	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T155	11		T64	2		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T201	10		T294	7		T306	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T201	1		T18	1		T265	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T210	13		T300	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T184	1		T307	4		T194	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	6		T49	1		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T44	9		T46	10		T161	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	14		T37	1		T156	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T165	1		T201	13		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	14		T49	1		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	6		T166	10		T183	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T46	3		T159	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	12		T156	9		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T2	1		T6	2		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T1	12		T11	13		T155	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	1		T51	5		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	1		T53	11		T199	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	7		T44	4		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	14		T12	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	19		T156	15		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T68	10		T192	1		T199	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T155	11		T52	6		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T3	17		T164	1		T241	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T201	10		T265	9		T308	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T210	14		T300	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T184	9		T307	3		T194	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	9		T49	6		T184	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T44	9		T46	7		T161	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	14		T37	12		T198	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T165	7		T201	10		T98	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T48	16		T161	15		T158	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	6		T166	12		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T46	6		T159	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	7		T32	12		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T2	9		T11	5		T192	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	12		T11	10		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T51	3		T64	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	6		T158	10		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	6		T44	3		T34	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	7		T155	1		T26	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T254	13		T294	3		T41	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T68	3		T192	13		T242	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T155	11		T64	2		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T26	15		T32	6		T173	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T14	10		T37	13		T49	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T46	8		T161	2		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	15		T48	17		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	10		T165	8		T166	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T101	1		T105	13		T305	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	8		T166	6		T98	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T1	2		T2	10		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T1	13		T9	7		T11	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	6		T200	15		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T155	3		T64	3		T53	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	2		T14	7		T51	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T12	8		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	2		T156	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T155	2		T199	2		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T44	4		T170	1		T101	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T68	4		T192	14		T40	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T52	5		T160	1		T262	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	1		T164	1		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T155	12		T64	3		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T158	1		T201	11		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16493	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T14	5		T56	10		T160	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	9		T161	6		T170	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	13		T48	13		T156	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T44	8		T166	9		T250	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T305	4		T193	12		T281	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	11		T166	6		T202	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T54	30		T46	2		T50	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	11		T9	5		T11	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	10		T200	12		T210	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T155	19		T53	5		T199	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	6		T51	3		T200	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	13		T26	2		T32	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	17		T156	14		T34	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T199	25		T242	18		T244	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T44	3		T170	3		T253	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T68	9		T309	13		T122	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T52	1		T262	9		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	16		T241	16		T26	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T155	10		T33	1		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T250	10		T294	5		T264	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T201	11		T18	1		T265	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T210	15		T300	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T184	10		T307	5		T194	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	10		T49	7		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T44	10		T46	8		T161	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	15		T37	13		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T165	8		T201	11		T98	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	17		T49	1		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	7		T166	13		T183	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	2		T46	7		T159	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	8		T156	1		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T2	10		T6	2		T11	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	13		T11	11		T155	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	2		T51	5		T64	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T51	1		T53	12		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	7		T44	4		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	1		T12	8		T155	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T156	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T68	4		T192	14		T199	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T155	12		T52	5		T64	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T3	1		T164	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T265	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T210	12		T300	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T307	2		T194	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	5		T160	11		T243	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T44	8		T46	9		T161	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	13		T156	7		T56	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T201	12		T250	13		T310	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T48	13		T161	15		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	5		T166	9		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	2		T159	2		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	11		T156	8		T32	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T11	10		T54	30		T50	40
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	11		T11	12		T155	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T51	3		T200	3		T286	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T53	5		T199	10		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	6		T44	3		T241	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	13		T26	2		T244	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	17		T156	14		T170	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T68	9		T199	25		T242	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T155	10		T52	1		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T3	16		T241	16		T26	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5