Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20071

1

T1

2

T3

31

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

5714

1

T1

26

T2

10

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20205

1

T1

28

T5

11

T7

145

auto[1]

5580

1

T2

10

T3

31

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	46	1			T303	15		T317	1		T318	11
values[0]	28	1			T49	7		T158	1		T168	3
values[1]	703	1			T9	12		T155	22		T52	6
values[2]	621	1			T49	1		T199	14		T158	16
values[3]	671	1			T1	26		T219	19		T98	11
values[4]	718	1			T12	8		T13	13		T14	28
values[5]	748	1			T3	17		T51	1		T44	18
values[6]	783	1			T3	14		T13	6		T156	9
values[7]	634	1			T11	35		T51	8		T48	30
values[8]	752	1			T11	23		T68	13		T199	13
values[9]	3589	1			T1	2		T2	10		T6	2
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	834	1			T49	8		T155	22		T52	6
values[1]	2939	1			T2	10		T6	2		T9	12
values[2]	606	1			T12	8		T14	15		T64	11
values[3]	806	1			T1	26		T13	13		T14	13
values[4]	602	1			T51	1		T46	9		T64	3
values[5]	873	1			T3	17		T13	6		T156	9
values[6]	653	1			T3	14		T11	35		T48	30
values[7]	831	1			T11	23		T68	13		T51	8
values[8]	886	1			T14	28		T44	7		T46	17
values[9]	225	1			T1	2		T192	8		T155	22
minimum	16530	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T49	2		T56	11		T161	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T155	11		T52	6		T64	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T199	14		T26	6		T34	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1590	1			T2	1		T6	2		T9	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T14	6		T201	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T64	1		T219	5		T319	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T13	13		T14	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	12		T164	1		T29	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	3		T195	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T51	1		T64	1		T200	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	17		T157	1		T199	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T13	6		T156	9		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	14		T11	12		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	11		T48	14		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	13		T68	10		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T51	5		T156	23		T53	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T14	14		T44	4		T46	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T170	4		T164	1		T262	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T155	20		T169	1		T174	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T1	1		T192	1		T161	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16369	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T214	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T49	6		T161	1		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T155	11		T64	2		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T26	2		T34	2		T165	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	967	1			T2	9		T9	6		T266	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	7		T14	9		T201	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T64	10		T219	14		T319	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T14	6		T37	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	12		T29	9		T66	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	6		T198	4		T26	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T64	2		T200	7		T26	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T40	11		T286	10		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T32	6		T166	12		T244	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	7		T155	1		T161	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	5		T48	16		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	10		T68	3		T200	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T51	3		T53	6		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	14		T44	3		T46	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T165	7		T242	14		T247	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T155	2		T301	5		T320	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T1	1		T192	7		T161	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T51	5		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T303	11		T317	1		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T49	1		T168	1		T290	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T158	1		T169	1		T321	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T56	11		T161	7		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	6		T155	11		T52	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T49	1		T199	14		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T158	1		T32	9		T17	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	1		T98	1		T210	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	12		T219	5		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T13	13		T14	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T64	1		T200	4		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	17		T44	9		T46	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	1		T29	11		T243	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	14		T160	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	6		T156	9		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	12		T155	1		T161	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	11		T51	5		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	13		T68	10		T199	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T170	12		T33	3		T55	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T14	14		T44	4		T46	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1735	1			T1	1		T2	1		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T303	4		T318	10		T322	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T49	6		T168	2		T323	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T161	1		T16	1		T34	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	6		T155	11		T64	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	2		T34	2		T165	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T158	15		T32	12		T17	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T98	10		T210	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	12		T219	14		T118	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	7		T14	15		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T64	10		T200	7		T173	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T44	9		T46	6		T198	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	9		T243	5		T193	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	11		T243	8		T286	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T64	2		T26	15		T166	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	7		T155	1		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	5		T51	3		T48	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	10		T68	3		T200	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T33	1		T224	14		T122	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T14	14		T44	3		T46	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1079	1			T1	1		T2	9		T192	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T49	8		T56	1		T161	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T155	12		T52	5		T64	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T199	1		T26	6		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1318	1			T2	10		T6	2		T9	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	8		T14	10		T201	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T64	11		T219	15		T319	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	2		T13	1		T14	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	13		T164	1		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	7		T195	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	1		T64	3		T200	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T157	1		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	1		T156	1		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T11	8		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	6		T48	17		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	11		T68	4		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T51	5		T156	2		T53	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T14	15		T44	4		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T170	1		T164	1		T262	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T155	3		T169	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	2		T192	8		T161	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16508	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T214	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T56	10		T161	6		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T155	10		T52	1		T32	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T199	13		T26	2		T34	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1239	1			T9	5		T54	30		T50	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	5		T201	12		T309	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T219	4		T319	1		T324	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	12		T14	6		T44	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	11		T29	10		T66	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	2		T198	5		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T200	3		T26	5		T173	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	16		T199	10		T286	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	5		T156	8		T241	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	13		T11	11		T199	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	10		T48	13		T166	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	12		T68	9		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T51	3		T156	21		T53	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	13		T44	3		T46	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T170	3		T262	9		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T155	19		T174	5		T325	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T161	15		T326	13		T327	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T254	9		T328	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T303	5		T317	1		T318	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T49	7		T168	3		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T158	1		T169	1		T321	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T56	1		T161	2		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	7		T155	12		T52	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T49	1		T199	1		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T158	16		T32	13		T17	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	2		T98	11		T210	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	13		T219	15		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	8		T13	1		T14	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T64	11		T200	8		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T44	10		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T51	1		T29	10		T243	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T160	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	1		T156	1		T64	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	8		T155	2		T161	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	6		T51	5		T48	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	11		T68	4		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T170	1		T33	3		T55	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T14	15		T44	4		T46	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1444	1			T1	2		T2	10		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T303	10		T322	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T290	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T56	10		T161	6		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	5		T155	10		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T199	13		T26	2		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T32	8		T17	5		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T210	11		T120	11		T294	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	11		T219	4		T118	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	12		T14	11		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T200	3		T173	11		T66	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	16		T44	8		T46	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	10		T243	5		T193	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	13		T199	10		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	5		T156	8		T241	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	11		T161	8		T39	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	10		T51	3		T48	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	12		T68	9		T199	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T170	11		T33	1		T228	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T14	13		T44	3		T46	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1370	1			T54	30		T50	40		T271	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5