Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22335

1

T1

26

T2

10

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3450

1

T1

2

T3

14

T11

58

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19625

1

T1

2

T3

17

T5

11

auto[1]

6160

1

T1

26

T2

10

T3

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	370	1			T1	2		T11	23		T192	8
values[0]	20	1			T11	19		T195	1		-	-
values[1]	706	1			T3	14		T14	13		T192	14
values[2]	698	1			T11	16		T13	6		T44	18
values[3]	602	1			T12	8		T51	1		T37	13
values[4]	699	1			T156	8		T195	1		T157	1
values[5]	674	1			T3	17		T13	13		T14	28
values[6]	589	1			T1	2		T48	30		T49	1
values[7]	745	1			T14	15		T46	17		T155	2
values[8]	704	1			T1	24		T51	8		T155	22
values[9]	3486	1			T2	10		T6	2		T9	12
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	779	1			T3	14		T11	35		T13	6
values[1]	498	1			T44	18		T49	7		T52	6
values[2]	770	1			T12	8		T51	1		T37	13
values[3]	623	1			T64	11		T195	1		T157	1
values[4]	802	1			T1	2		T3	17		T13	13
values[5]	582	1			T46	17		T49	1		T158	1
values[6]	2942	1			T2	10		T6	2		T14	15
values[7]	862	1			T1	24		T51	8		T155	22
values[8]	1124	1			T11	23		T68	13		T192	8
values[9]	123	1			T1	2		T9	12		T46	9
minimum	16680	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T200	8		T33	3		T243	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	14		T11	23		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	1		T64	1		T166	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T44	9		T52	6		T64	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T51	1		T37	1		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T155	11		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T195	1		T198	6		T241	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T64	1		T157	1		T241	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	1		T3	17		T48	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T13	13		T14	14		T199	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	1		T158	1		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	10		T17	14		T243	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T2	1		T6	2		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T155	1		T56	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	12		T155	20		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	5		T164	1		T171	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T68	10		T156	9		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T11	13		T192	1		T170	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T9	6		T46	3		T194	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T1	1		T160	12		T32	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16437	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T195	1		T254	10		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T200	11		T33	1		T243	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	12		T14	6		T192	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	6		T64	2		T166	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T44	9		T64	2		T200	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	12		T44	3		T161	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	7		T155	11		T53	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T198	4		T201	10		T244	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T64	10		T26	2		T210	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T48	16		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	14		T16	1		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	9		T32	12		T40	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T46	7		T17	6		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T2	9		T14	9		T200	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T155	1		T158	15		T201	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	12		T155	2		T161	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	3		T105	12		T297	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T68	3		T219	14		T183	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	10		T192	7		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T9	6		T46	6		T194	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T1	1		T32	6		T165	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T51	5		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T254	13		T213	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T170	4		T210	13		T41	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	1		T11	13		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T11	12		T195	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T160	1		T200	8		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	14		T14	7		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T64	1		T166	15		T247	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	11		T13	6		T44	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T51	1		T37	1		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T155	11		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T156	8		T195	1		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T157	1		T53	11		T241	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	17		T161	9		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	13		T14	14		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T48	14		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	3		T17	14		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	6		T200	4		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T46	10		T155	1		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	12		T155	20		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T51	5		T164	1		T171	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1796	1			T2	1		T6	2		T9	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T170	12		T39	10		T34	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T210	14		T41	11		T330	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T1	1		T11	10		T192	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T11	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T200	11		T33	1		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	6		T192	13		T165	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T64	2		T166	11		T247	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	5		T44	9		T64	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T37	12		T44	3		T49	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	7		T155	11		T98	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T198	4		T161	1		T201	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T53	6		T26	2		T210	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T161	10		T32	7		T244	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	14		T64	10		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T48	16		T39	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T16	1		T17	6		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	9		T200	7		T159	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T46	7		T155	1		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	12		T155	2		T26	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	3		T105	12		T127	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T2	9		T9	6		T68	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T39	8		T34	7		T165	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T200	12		T33	3		T243	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	1		T11	14		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	7		T64	3		T166	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T44	10		T52	5		T64	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T51	1		T37	13		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	8		T155	12		T53	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T195	1		T198	5		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T64	11		T157	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T3	1		T48	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	1		T14	15		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T49	1		T158	1		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T46	8		T17	15		T243	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T2	10		T6	2		T14	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T155	2		T56	1		T158	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	13		T155	3		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T51	5		T164	1		T171	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T68	4		T156	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	11		T192	8		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T9	7		T46	7		T194	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T1	2		T160	1		T32	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16580	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T195	1		T254	14		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T200	7		T33	1		T243	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	13		T11	21		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T166	14		T247	12		T66	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T44	8		T52	1		T200	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	3		T156	7		T199	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T155	10		T53	5		T219	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T198	5		T241	7		T201	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T241	16		T26	2		T248	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	16		T48	13		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	12		T14	13		T199	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	10		T32	8		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T46	9		T17	5		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T14	5		T54	30		T50	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T56	10		T173	4		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	11		T155	19		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T51	3		T299	3		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T68	9		T156	8		T170	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T11	12		T170	11		T39	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T9	5		T46	2		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T160	11		T331	6		T328	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T67	4		T202	5		T281	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T254	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T170	1		T210	15		T41	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T1	2		T11	11		T192	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T11	8		T195	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T160	1		T200	12		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T14	7		T192	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T64	3		T166	12		T247	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	6		T13	1		T44	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T51	1		T37	13		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	8		T155	12		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T156	1		T195	1		T198	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T157	1		T53	12		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T161	11		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	1		T14	15		T64	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	2		T48	17		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	3		T17	15		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T14	10		T200	8		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	8		T155	2		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	13		T155	3		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T51	5		T164	1		T171	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1487	1			T2	10		T6	2		T9	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T170	1		T39	9		T34	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T170	3		T210	12		T41	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	12		T160	11		T262	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T11	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T200	7		T33	1		T243	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	13		T14	6		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T166	14		T247	12		T66	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	10		T13	5		T44	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T44	3		T167	17		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T155	10		T66	11		T122	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T156	7		T198	5		T199	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	5		T241	16		T26	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	16		T161	8		T32	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	12		T14	13		T199	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	13		T39	20		T32	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	1		T17	5		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	5		T200	3		T159	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T46	9		T56	10		T120	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	11		T155	19		T26	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	3		T173	4		T250	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T9	5		T54	30		T68	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T170	11		T39	9		T34	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5