Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25785

1

T1

28

T2

10

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22040

1

T1

4

T2

10

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3745

1

T1

24

T3

31

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19841

1

T1

4

T3

14

T5

11

auto[1]

5944

1

T1

24

T2

10

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21706

1

T1

14

T2

1

T3

31

auto[1]

4079

1

T1

14

T2

9

T9

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T263	1		T282	20		T332	1
values[0]	21	1			T195	1		T98	1		T210	4
values[1]	726	1			T3	31		T12	8		T192	8
values[2]	841	1			T46	17		T198	10		T170	4
values[3]	730	1			T11	42		T13	13		T14	13
values[4]	682	1			T44	18		T48	30		T156	15
values[5]	2963	1			T2	10		T6	2		T54	32
values[6]	718	1			T9	12		T14	43		T199	14
values[7]	691	1			T1	24		T51	8		T49	7
values[8]	712	1			T13	6		T49	1		T160	12
values[9]	1187	1			T1	4		T11	16		T37	13
minimum	16492	1			T5	11		T7	145		T8	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	954	1			T3	31		T12	8		T192	8
values[1]	811	1			T14	13		T46	17		T199	11
values[2]	650	1			T11	42		T13	13		T68	13
values[3]	3006	1			T2	10		T6	2		T54	32
values[4]	737	1			T51	1		T155	2		T64	3
values[5]	624	1			T9	12		T14	43		T155	22
values[6]	818	1			T1	24		T13	6		T51	8
values[7]	676	1			T49	1		T26	8		T34	17
values[8]	847	1			T1	2		T11	16		T37	13
values[9]	159	1			T1	2		T192	14		T64	11
minimum	16503	1			T5	11		T7	145		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

4252

1

T1

11

T3

29

T9

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T156	9		T195	1		T161	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T3	31		T12	1		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T201	14		T248	15		T173	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	7		T46	10		T199	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T68	10		T157	1		T242	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	25		T13	13		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T2	1		T6	2		T54	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T44	9		T195	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T155	1		T200	21		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	1		T64	1		T161	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	14		T199	14		T166	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	6		T14	6		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	6		T160	12		T199	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	12		T51	5		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	1		T26	6		T34	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T218	1		T166	15		T183	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T46	3		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	11		T37	1		T170	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T1	1		T244	14		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T192	1		T64	1		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16348	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T333	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T161	1		T200	7		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	7		T192	7		T53	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T201	20		T184	9		T66	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	6		T46	7		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T68	3		T242	14		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	17		T44	3		T219	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T2	9		T48	16		T64	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T44	9		T32	6		T17	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T155	1		T200	25		T158	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T64	2		T161	15		T39	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	14		T166	5		T105	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	6		T14	9		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T26	15		T173	18		T247	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	12		T51	3		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T26	2		T34	7		T219	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T166	11		T183	11		T286	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T46	6		T122	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	5		T37	12		T32	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T1	1		T244	16		T105	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T192	13		T64	10		T158	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	11		T332	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T195	1		T210	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T98	1		T333	10		T188	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T156	9		T161	7		T200	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	31		T12	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T165	1		T201	14		T173	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T46	10		T198	6		T170	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T68	10		T242	10		T248	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	25		T13	13		T14	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	14		T156	15		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T44	9		T195	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T2	1		T6	2		T54	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T51	1		T64	1		T161	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	14		T199	14		T200	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	6		T14	6		T39	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T199	13		T26	8		T173	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	12		T51	5		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	6		T49	1		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T26	1		T32	9		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T1	2		T46	3		T56	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T11	11		T37	1		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16347	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T282	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T210	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T327	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T161	1		T200	7		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	7		T192	7		T53	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T165	4		T201	20		T184	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	7		T198	4		T29	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T68	3		T242	14		T66	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	17		T14	6		T44	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T48	16		T184	7		T249	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T44	9		T32	6		T17	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T2	9		T155	1		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T64	2		T161	15		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	14		T200	25		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	6		T14	9		T39	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	15		T173	18		T40	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	12		T51	3		T49	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T219	6		T247	14		T105	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T26	1		T32	12		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T1	2		T46	6		T26	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	5		T37	12		T192	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T51	5		T37	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T156	1		T195	1		T161	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	2		T12	8		T192	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T201	22		T248	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	7		T46	8		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T68	4		T157	1		T242	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	19		T13	1		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T2	10		T6	2		T54	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T44	10		T195	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T155	2		T200	27		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	1		T64	3		T161	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	15		T199	1		T166	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	7		T14	10		T155	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T160	1		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	13		T51	5		T49	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T49	1		T26	6		T34	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T218	1		T166	12		T183	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	2		T46	7		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	6		T37	13		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T1	2		T244	17		T105	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T192	14		T64	11		T158	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16493	1			T5	11		T7	145		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T333	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T156	8		T161	6		T200	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	29		T156	7		T53	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T201	12		T248	14		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	6		T46	9		T199	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T68	9		T242	9		T314	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	23		T13	12		T44	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T54	30		T48	13		T50	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T44	8		T17	5		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T200	19		T243	8		T120	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T161	15		T39	9		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T14	13		T199	13		T166	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	5		T14	5		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	5		T160	11		T199	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	11		T51	3		T155	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	2		T34	9		T219	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T166	14		T183	11		T286	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	2		T56	10		T262	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	10		T170	11		T32	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T244	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T243	5		T193	3		T214	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T333	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T282	10		T332	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T195	1		T210	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T98	1		T333	1		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T156	1		T161	2		T200	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	2		T12	8		T192	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T165	5		T201	22		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T46	8		T198	5		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T68	4		T242	15		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	19		T13	1		T14	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	17		T156	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T44	10		T195	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	10		T6	2		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T51	1		T64	3		T161	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	15		T199	1		T200	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	7		T14	10		T39	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T199	1		T26	18		T173	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	13		T51	5		T49	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	1		T49	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	2		T32	13		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T1	4		T46	7		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T11	6		T37	13		T192	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T5	11		T7	145		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T282	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T210	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T333	9		T188	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T156	8		T161	6		T200	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	29		T156	7		T53	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T201	12		T173	4		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	9		T198	5		T170	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T68	9		T242	9		T248	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	23		T13	12		T14	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T48	13		T156	14		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T44	8		T17	5		T67	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T54	30		T50	40		T271	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T161	15		T16	1		T219	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	13		T199	13		T200	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	5		T14	5		T39	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T199	12		T26	5		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	11		T51	3		T155	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	5		T160	11		T262	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T32	8		T33	1		T166	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T46	2		T56	10		T26	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	10		T170	11		T32	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21533

1

T1

17

T2

10

T3

2

auto[1]

auto[0]

4252

1

T1

11

T3

29

T9

5