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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.22


Total test records in report: 919
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T802 /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3117213739 Jul 02 09:32:29 AM PDT 24 Jul 02 09:42:14 AM PDT 24 513321102910 ps
T354 /workspace/coverage/default/2.adc_ctrl_filters_interrupt.183522687 Jul 02 09:31:09 AM PDT 24 Jul 02 09:32:57 AM PDT 24 163837260737 ps
T36 /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1509379033 Jul 02 09:34:15 AM PDT 24 Jul 02 09:35:01 AM PDT 24 18836728507 ps
T803 /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3824224982 Jul 02 09:35:11 AM PDT 24 Jul 02 09:35:20 AM PDT 24 26903044759 ps
T804 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1687101378 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:17 AM PDT 24 358747291 ps
T72 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1646017561 Jul 02 09:50:16 AM PDT 24 Jul 02 09:50:28 AM PDT 24 4035584796 ps
T79 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.58206694 Jul 02 09:50:12 AM PDT 24 Jul 02 09:50:22 AM PDT 24 859415952 ps
T83 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2812437176 Jul 02 09:50:07 AM PDT 24 Jul 02 09:50:18 AM PDT 24 597964057 ps
T146 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1280934805 Jul 02 09:50:15 AM PDT 24 Jul 02 09:50:25 AM PDT 24 413787888 ps
T73 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.994603943 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:06 AM PDT 24 5014319633 ps
T74 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2170513539 Jul 02 09:50:23 AM PDT 24 Jul 02 09:50:33 AM PDT 24 2030887590 ps
T75 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.467429495 Jul 02 09:50:16 AM PDT 24 Jul 02 09:50:49 AM PDT 24 8154264118 ps
T147 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.449116220 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:21 AM PDT 24 4221971451 ps
T90 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.813529509 Jul 02 09:50:07 AM PDT 24 Jul 02 09:50:16 AM PDT 24 631052896 ps
T108 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4262461759 Jul 02 09:50:41 AM PDT 24 Jul 02 09:50:43 AM PDT 24 583654952 ps
T153 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3953592008 Jul 02 09:49:50 AM PDT 24 Jul 02 09:50:00 AM PDT 24 952927624 ps
T805 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2867734827 Jul 02 09:50:18 AM PDT 24 Jul 02 09:50:28 AM PDT 24 346498021 ps
T87 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.73453089 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:14 AM PDT 24 671080056 ps
T806 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2784879880 Jul 02 09:50:14 AM PDT 24 Jul 02 09:50:25 AM PDT 24 393692914 ps
T129 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.82194492 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:34 AM PDT 24 23961811490 ps
T130 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4024464150 Jul 02 09:50:22 AM PDT 24 Jul 02 09:51:21 AM PDT 24 24758538096 ps
T88 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4257808123 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:23 AM PDT 24 495267054 ps
T807 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2807336480 Jul 02 09:50:24 AM PDT 24 Jul 02 09:50:33 AM PDT 24 395948529 ps
T808 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1701453247 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:21 AM PDT 24 353154468 ps
T809 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3992802708 Jul 02 09:49:54 AM PDT 24 Jul 02 09:50:04 AM PDT 24 512134624 ps
T810 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.853262328 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:19 AM PDT 24 493182386 ps
T811 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2834971569 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:14 AM PDT 24 529438095 ps
T91 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.684810920 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:13 AM PDT 24 596262522 ps
T812 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.97359274 Jul 02 09:50:01 AM PDT 24 Jul 02 09:50:11 AM PDT 24 459442544 ps
T154 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.9493021 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:58 AM PDT 24 52648057299 ps
T84 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2486946249 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:15 AM PDT 24 720085045 ps
T148 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3103864950 Jul 02 09:50:06 AM PDT 24 Jul 02 09:50:17 AM PDT 24 2881220505 ps
T76 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2903580001 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:20 AM PDT 24 3709242243 ps
T77 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2201156324 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:30 AM PDT 24 8836246495 ps
T149 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3769407446 Jul 02 09:50:37 AM PDT 24 Jul 02 09:50:41 AM PDT 24 473698821 ps
T813 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2048428072 Jul 02 09:50:33 AM PDT 24 Jul 02 09:50:38 AM PDT 24 403609334 ps
T814 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1077712998 Jul 02 09:50:24 AM PDT 24 Jul 02 09:50:33 AM PDT 24 375656564 ps
T150 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3453331851 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:29 AM PDT 24 4135867613 ps
T815 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2774441136 Jul 02 09:50:15 AM PDT 24 Jul 02 09:50:25 AM PDT 24 397581127 ps
T816 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2658101418 Jul 02 09:50:07 AM PDT 24 Jul 02 09:50:16 AM PDT 24 564406273 ps
T85 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3594319349 Jul 02 09:50:12 AM PDT 24 Jul 02 09:50:43 AM PDT 24 8692642634 ps
T151 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4056313220 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:13 AM PDT 24 478170677 ps
T817 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1812774826 Jul 02 09:50:14 AM PDT 24 Jul 02 09:50:25 AM PDT 24 569018167 ps
T92 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3393470501 Jul 02 09:50:12 AM PDT 24 Jul 02 09:50:28 AM PDT 24 4884474928 ps
T152 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1798035906 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:22 AM PDT 24 2242941280 ps
T818 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4270315143 Jul 02 09:50:16 AM PDT 24 Jul 02 09:50:25 AM PDT 24 526900815 ps
T131 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3678890664 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:20 AM PDT 24 526212854 ps
T819 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.408677482 Jul 02 09:50:14 AM PDT 24 Jul 02 09:50:24 AM PDT 24 392557550 ps
T820 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.23720214 Jul 02 09:50:15 AM PDT 24 Jul 02 09:50:25 AM PDT 24 488936227 ps
T821 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2775609280 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:21 AM PDT 24 333199699 ps
T89 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2319216353 Jul 02 09:50:28 AM PDT 24 Jul 02 09:50:37 AM PDT 24 407309016 ps
T822 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3824066124 Jul 02 09:50:14 AM PDT 24 Jul 02 09:50:24 AM PDT 24 482929256 ps
T823 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3217292205 Jul 02 09:50:26 AM PDT 24 Jul 02 09:50:39 AM PDT 24 1932970987 ps
T824 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3279052026 Jul 02 09:50:19 AM PDT 24 Jul 02 09:50:29 AM PDT 24 497105099 ps
T825 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2248090666 Jul 02 09:50:17 AM PDT 24 Jul 02 09:50:27 AM PDT 24 441200036 ps
T93 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3567783559 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:32 AM PDT 24 4532791175 ps
T826 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1742961525 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:17 AM PDT 24 416835127 ps
T827 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1895314045 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:18 AM PDT 24 511307342 ps
T828 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2198975555 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:14 AM PDT 24 1196228546 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2615265099 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:20 AM PDT 24 479019064 ps
T830 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3846626328 Jul 02 09:49:57 AM PDT 24 Jul 02 09:50:06 AM PDT 24 476384514 ps
T831 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2431662797 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:23 AM PDT 24 316694659 ps
T832 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3311885449 Jul 02 09:50:06 AM PDT 24 Jul 02 09:50:18 AM PDT 24 4450053622 ps
T132 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2445126379 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:11 AM PDT 24 440933896 ps
T133 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.436480545 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:06 AM PDT 24 384090176 ps
T833 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.580344913 Jul 02 09:49:59 AM PDT 24 Jul 02 09:50:08 AM PDT 24 400538829 ps
T834 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1787884892 Jul 02 09:50:16 AM PDT 24 Jul 02 09:50:26 AM PDT 24 2276711189 ps
T835 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1815226256 Jul 02 09:49:58 AM PDT 24 Jul 02 09:50:07 AM PDT 24 386709000 ps
T134 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2823155865 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:13 AM PDT 24 427537480 ps
T836 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3324025819 Jul 02 09:50:07 AM PDT 24 Jul 02 09:50:17 AM PDT 24 538232220 ps
T837 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1997392210 Jul 02 09:50:15 AM PDT 24 Jul 02 09:50:26 AM PDT 24 459977894 ps
T359 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3558891432 Jul 02 09:50:19 AM PDT 24 Jul 02 09:50:34 AM PDT 24 4166301094 ps
T838 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3964370853 Jul 02 09:50:21 AM PDT 24 Jul 02 09:50:31 AM PDT 24 428098627 ps
T839 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2002376559 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:23 AM PDT 24 4665306355 ps
T840 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1377978405 Jul 02 09:49:45 AM PDT 24 Jul 02 09:49:51 AM PDT 24 1100637376 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1755498781 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:20 AM PDT 24 406724044 ps
T842 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3419659368 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:18 AM PDT 24 430638852 ps
T135 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1673999474 Jul 02 09:50:47 AM PDT 24 Jul 02 09:50:49 AM PDT 24 373635093 ps
T843 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2445809430 Jul 02 09:50:24 AM PDT 24 Jul 02 09:50:33 AM PDT 24 298543498 ps
T844 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1286122192 Jul 02 09:49:54 AM PDT 24 Jul 02 09:50:03 AM PDT 24 532375402 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2650619871 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:19 AM PDT 24 893365536 ps
T136 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.756797048 Jul 02 09:50:03 AM PDT 24 Jul 02 09:50:11 AM PDT 24 397362255 ps
T846 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.656454798 Jul 02 09:50:19 AM PDT 24 Jul 02 09:50:36 AM PDT 24 3739739464 ps
T847 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3047527303 Jul 02 09:50:20 AM PDT 24 Jul 02 09:50:30 AM PDT 24 537597891 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1436975397 Jul 02 09:50:26 AM PDT 24 Jul 02 09:50:34 AM PDT 24 447453709 ps
T849 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3117264078 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:16 AM PDT 24 8032620347 ps
T137 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.723096081 Jul 02 09:50:07 AM PDT 24 Jul 02 09:50:18 AM PDT 24 962534558 ps
T850 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3890513302 Jul 02 09:50:06 AM PDT 24 Jul 02 09:50:18 AM PDT 24 4855036316 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.392507299 Jul 02 09:50:25 AM PDT 24 Jul 02 09:50:33 AM PDT 24 289493451 ps
T852 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3639304794 Jul 02 09:50:35 AM PDT 24 Jul 02 09:50:40 AM PDT 24 1277041759 ps
T853 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3783479212 Jul 02 09:50:24 AM PDT 24 Jul 02 09:50:33 AM PDT 24 369085108 ps
T854 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4128813404 Jul 02 09:50:16 AM PDT 24 Jul 02 09:50:26 AM PDT 24 393759000 ps
T855 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1899386329 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:32 AM PDT 24 4789615933 ps
T856 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2842415016 Jul 02 09:50:19 AM PDT 24 Jul 02 09:50:30 AM PDT 24 482482384 ps
T857 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4233589907 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:21 AM PDT 24 378740238 ps
T858 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2754983829 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:22 AM PDT 24 424099957 ps
T859 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2005005022 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:08 AM PDT 24 580974112 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3026639720 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:19 AM PDT 24 354126864 ps
T138 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1024457450 Jul 02 09:50:16 AM PDT 24 Jul 02 09:50:26 AM PDT 24 1455390412 ps
T861 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1570589729 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:22 AM PDT 24 298272478 ps
T862 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2467365632 Jul 02 09:49:49 AM PDT 24 Jul 02 09:49:57 AM PDT 24 3648901692 ps
T94 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3583198850 Jul 02 09:50:12 AM PDT 24 Jul 02 09:50:41 AM PDT 24 8529533864 ps
T863 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3934622246 Jul 02 09:50:19 AM PDT 24 Jul 02 09:50:29 AM PDT 24 383163872 ps
T864 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3407514098 Jul 02 09:50:28 AM PDT 24 Jul 02 09:50:35 AM PDT 24 313180999 ps
T142 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.682573234 Jul 02 09:50:18 AM PDT 24 Jul 02 09:50:28 AM PDT 24 1029335793 ps
T865 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1574285027 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:19 AM PDT 24 4586618233 ps
T866 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.293611120 Jul 02 09:50:18 AM PDT 24 Jul 02 09:50:27 AM PDT 24 311763848 ps
T867 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4106849860 Jul 02 09:50:01 AM PDT 24 Jul 02 09:50:13 AM PDT 24 4579917716 ps
T868 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2179342115 Jul 02 09:50:19 AM PDT 24 Jul 02 09:50:29 AM PDT 24 479154322 ps
T143 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1424722760 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:14 AM PDT 24 522210808 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4040508132 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:24 AM PDT 24 718496755 ps
T870 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3994462135 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:20 AM PDT 24 358609637 ps
T871 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3514619127 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:24 AM PDT 24 4752618056 ps
T872 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1472743966 Jul 02 09:50:14 AM PDT 24 Jul 02 09:50:25 AM PDT 24 884203121 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3025960437 Jul 02 09:49:55 AM PDT 24 Jul 02 09:50:03 AM PDT 24 513322723 ps
T874 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3603486306 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:17 AM PDT 24 328593426 ps
T875 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.756003261 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:17 AM PDT 24 362405997 ps
T876 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3783753300 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:08 AM PDT 24 4355714301 ps
T139 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.691891398 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:06 AM PDT 24 808054217 ps
T877 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2181934632 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:18 AM PDT 24 454335590 ps
T878 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2159058942 Jul 02 09:49:55 AM PDT 24 Jul 02 09:50:04 AM PDT 24 788720028 ps
T360 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3229990707 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:22 AM PDT 24 8567606362 ps
T879 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2091499029 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:21 AM PDT 24 890644199 ps
T880 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.884228456 Jul 02 09:49:55 AM PDT 24 Jul 02 09:50:04 AM PDT 24 448233854 ps
T140 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2229662668 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:14 AM PDT 24 1303006417 ps
T881 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4056193045 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:24 AM PDT 24 436614760 ps
T357 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1162128370 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:40 AM PDT 24 8793775392 ps
T882 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1296743486 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:21 AM PDT 24 506991692 ps
T883 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1894780863 Jul 02 09:50:23 AM PDT 24 Jul 02 09:50:32 AM PDT 24 509426380 ps
T884 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.107388081 Jul 02 09:50:17 AM PDT 24 Jul 02 09:50:30 AM PDT 24 2334197127 ps
T885 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1477019575 Jul 02 09:50:28 AM PDT 24 Jul 02 09:50:43 AM PDT 24 2379079904 ps
T886 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.640109914 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:13 AM PDT 24 600738622 ps
T887 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.335978067 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:29 AM PDT 24 4716525789 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1051541437 Jul 02 09:49:48 AM PDT 24 Jul 02 09:50:16 AM PDT 24 8627475270 ps
T889 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3785375688 Jul 02 09:50:03 AM PDT 24 Jul 02 09:50:11 AM PDT 24 527268163 ps
T890 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3379208401 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:21 AM PDT 24 489187470 ps
T891 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1555406400 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:18 AM PDT 24 575968075 ps
T141 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3938054514 Jul 02 09:50:03 AM PDT 24 Jul 02 09:50:11 AM PDT 24 405007609 ps
T892 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1931554345 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:02 AM PDT 24 473537973 ps
T893 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.622672941 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:17 AM PDT 24 506191867 ps
T894 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2229254879 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:15 AM PDT 24 4377023882 ps
T895 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.428495528 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:19 AM PDT 24 563794711 ps
T896 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3879941560 Jul 02 09:50:32 AM PDT 24 Jul 02 09:50:37 AM PDT 24 531919663 ps
T897 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3133717981 Jul 02 09:50:30 AM PDT 24 Jul 02 09:50:38 AM PDT 24 4564176054 ps
T898 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1088795174 Jul 02 09:50:21 AM PDT 24 Jul 02 09:50:31 AM PDT 24 441951451 ps
T144 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3498316435 Jul 02 09:50:14 AM PDT 24 Jul 02 09:50:34 AM PDT 24 8189030564 ps
T899 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3436321751 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:10 AM PDT 24 818020035 ps
T900 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.459883473 Jul 02 09:50:23 AM PDT 24 Jul 02 09:50:32 AM PDT 24 505120682 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2653066081 Jul 02 09:50:31 AM PDT 24 Jul 02 09:50:37 AM PDT 24 530540030 ps
T902 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1425278259 Jul 02 09:50:17 AM PDT 24 Jul 02 09:50:27 AM PDT 24 541783953 ps
T145 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3424592830 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:09 AM PDT 24 401530660 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1418055873 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:07 AM PDT 24 839403968 ps
T904 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4258837306 Jul 02 09:50:25 AM PDT 24 Jul 02 09:50:35 AM PDT 24 642866440 ps
T905 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1953884107 Jul 02 09:50:20 AM PDT 24 Jul 02 09:50:32 AM PDT 24 700669894 ps
T906 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3942082859 Jul 02 09:50:25 AM PDT 24 Jul 02 09:50:34 AM PDT 24 412690423 ps
T907 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1095955951 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:21 AM PDT 24 8556342065 ps
T908 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2804487468 Jul 02 09:50:27 AM PDT 24 Jul 02 09:50:36 AM PDT 24 501183252 ps
T358 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3840516930 Jul 02 09:50:31 AM PDT 24 Jul 02 09:50:41 AM PDT 24 8641997708 ps
T909 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2424665437 Jul 02 09:50:18 AM PDT 24 Jul 02 09:50:33 AM PDT 24 8139327837 ps
T910 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4153824655 Jul 02 09:50:17 AM PDT 24 Jul 02 09:50:27 AM PDT 24 442103489 ps
T911 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3061877678 Jul 02 09:50:17 AM PDT 24 Jul 02 09:50:27 AM PDT 24 342257690 ps
T912 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1419938117 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:20 AM PDT 24 4712751868 ps
T913 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1054857306 Jul 02 09:50:17 AM PDT 24 Jul 02 09:50:28 AM PDT 24 528509087 ps
T914 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4137616320 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:20 AM PDT 24 530790154 ps
T915 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3387455250 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:18 AM PDT 24 494951576 ps
T916 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2060071603 Jul 02 09:50:17 AM PDT 24 Jul 02 09:50:27 AM PDT 24 453295198 ps
T917 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.251127471 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:15 AM PDT 24 425581883 ps
T918 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4223985267 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:12 AM PDT 24 524996339 ps
T919 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.584429915 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:11 AM PDT 24 376222266 ps

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3263064453
Short name T1
Test name
Test status
Simulation time 529800572846 ps
CPU time 103.51 seconds
Started Jul 02 09:37:47 AM PDT 24
Finished Jul 02 09:39:31 AM PDT 24
Peak memory 201912 kb
Host smart-5b5b62c1-000d-4f6f-8c4d-87fe037e96ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263064453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3263064453
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.254088338
Short name T7
Test name
Test status
Simulation time 112582909845 ps
CPU time 373.44 seconds
Started Jul 02 09:33:28 AM PDT 24
Finished Jul 02 09:39:42 AM PDT 24
Peak memory 202276 kb
Host smart-e71a6e87-7711-445b-81c2-9c3aad7c6b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254088338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.254088338
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3549065095
Short name T26
Test name
Test status
Simulation time 512526785324 ps
CPU time 204.26 seconds
Started Jul 02 09:36:30 AM PDT 24
Finished Jul 02 09:39:55 AM PDT 24
Peak memory 218076 kb
Host smart-0e8a8479-67a8-4f5b-8797-6ca5c494e724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549065095 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3549065095
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2496553136
Short name T11
Test name
Test status
Simulation time 488112357938 ps
CPU time 591.15 seconds
Started Jul 02 09:31:52 AM PDT 24
Finished Jul 02 09:41:44 AM PDT 24
Peak memory 202168 kb
Host smart-c5be2dc7-785d-4b58-8e39-1aee16178f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496553136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2496553136
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.546503789
Short name T16
Test name
Test status
Simulation time 16007050556 ps
CPU time 54.34 seconds
Started Jul 02 09:32:08 AM PDT 24
Finished Jul 02 09:33:02 AM PDT 24
Peak memory 210528 kb
Host smart-67fbb19b-3a38-44f2-b484-7e4ed3fe5ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546503789 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.546503789
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2696702588
Short name T14
Test name
Test status
Simulation time 492801882842 ps
CPU time 267.99 seconds
Started Jul 02 09:36:39 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 201924 kb
Host smart-2d4773ff-d1e6-4cae-b514-a3593f2b1f01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696702588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2696702588
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.4116134097
Short name T32
Test name
Test status
Simulation time 517146363759 ps
CPU time 329.11 seconds
Started Jul 02 09:34:08 AM PDT 24
Finished Jul 02 09:39:37 AM PDT 24
Peak memory 201960 kb
Host smart-20a09477-98cc-4092-b271-2d008ba46197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116134097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.4116134097
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2482051547
Short name T228
Test name
Test status
Simulation time 436821146462 ps
CPU time 793.12 seconds
Started Jul 02 09:34:25 AM PDT 24
Finished Jul 02 09:47:39 AM PDT 24
Peak memory 210372 kb
Host smart-53a04c62-d387-4112-8c80-febfc3dbf223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482051547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2482051547
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1348029015
Short name T155
Test name
Test status
Simulation time 554894726487 ps
CPU time 425.42 seconds
Started Jul 02 09:35:11 AM PDT 24
Finished Jul 02 09:42:17 AM PDT 24
Peak memory 201900 kb
Host smart-2e398ae6-87c4-41a9-bfb8-52a8a5e4f35a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348029015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1348029015
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2812437176
Short name T83
Test name
Test status
Simulation time 597964057 ps
CPU time 2.63 seconds
Started Jul 02 09:50:07 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 217764 kb
Host smart-a65c7c0c-01ea-4d21-915e-276d70f540cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812437176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2812437176
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1295848563
Short name T156
Test name
Test status
Simulation time 558393834465 ps
CPU time 148.58 seconds
Started Jul 02 09:33:15 AM PDT 24
Finished Jul 02 09:35:44 AM PDT 24
Peak memory 201944 kb
Host smart-7e12aaa0-3d58-434a-8de4-1b6abe9fe614
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295848563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1295848563
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1286185069
Short name T173
Test name
Test status
Simulation time 500882353329 ps
CPU time 199.48 seconds
Started Jul 02 09:33:14 AM PDT 24
Finished Jul 02 09:36:34 AM PDT 24
Peak memory 202112 kb
Host smart-124a9f8c-e74b-4c71-8931-acb5995d56ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286185069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1286185069
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1515395334
Short name T80
Test name
Test status
Simulation time 4836174316 ps
CPU time 1.85 seconds
Started Jul 02 09:30:55 AM PDT 24
Finished Jul 02 09:30:57 AM PDT 24
Peak memory 217140 kb
Host smart-570286d6-926e-47e1-8eb7-187798dbac1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515395334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1515395334
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3574971119
Short name T123
Test name
Test status
Simulation time 347134726576 ps
CPU time 88.81 seconds
Started Jul 02 09:35:04 AM PDT 24
Finished Jul 02 09:36:34 AM PDT 24
Peak memory 210232 kb
Host smart-2d6b51b0-6e84-4323-abd0-a9f3786ce8e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574971119 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3574971119
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2050449273
Short name T44
Test name
Test status
Simulation time 459178155238 ps
CPU time 852.33 seconds
Started Jul 02 09:32:09 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 202180 kb
Host smart-389191fe-2bcd-4efc-9a4a-75495b22e462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050449273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2050449273
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3754761509
Short name T193
Test name
Test status
Simulation time 514374130916 ps
CPU time 302.15 seconds
Started Jul 02 09:35:40 AM PDT 24
Finished Jul 02 09:40:43 AM PDT 24
Peak memory 201940 kb
Host smart-c5ebcb4d-65d2-4f08-b0be-3cc55773bc02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754761509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3754761509
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1875272896
Short name T286
Test name
Test status
Simulation time 331258234175 ps
CPU time 381.45 seconds
Started Jul 02 09:33:15 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 201912 kb
Host smart-96cbdbcd-2bbd-4a88-afa8-4a2954fc3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875272896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1875272896
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4024464150
Short name T130
Test name
Test status
Simulation time 24758538096 ps
CPU time 51.63 seconds
Started Jul 02 09:50:22 AM PDT 24
Finished Jul 02 09:51:21 AM PDT 24
Peak memory 201788 kb
Host smart-4ea8fa2d-574c-4f07-b56a-a5912e153738
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024464150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4024464150
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.931010420
Short name T9
Test name
Test status
Simulation time 169202360952 ps
CPU time 394.92 seconds
Started Jul 02 09:31:40 AM PDT 24
Finished Jul 02 09:38:16 AM PDT 24
Peak memory 202192 kb
Host smart-bd7e4367-001b-4617-a170-8fbc0e2530fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931010420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.931010420
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3117103987
Short name T242
Test name
Test status
Simulation time 348184812817 ps
CPU time 251.56 seconds
Started Jul 02 09:35:01 AM PDT 24
Finished Jul 02 09:39:13 AM PDT 24
Peak memory 201908 kb
Host smart-40d57a89-98bb-4ef2-a465-1fa669e24293
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117103987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3117103987
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.979772699
Short name T210
Test name
Test status
Simulation time 501906148833 ps
CPU time 191.82 seconds
Started Jul 02 09:37:05 AM PDT 24
Finished Jul 02 09:40:17 AM PDT 24
Peak memory 201940 kb
Host smart-bec9912d-fd0a-4a03-a5ab-8cf7b5616912
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979772699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.979772699
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3453469922
Short name T39
Test name
Test status
Simulation time 373192142949 ps
CPU time 863.64 seconds
Started Jul 02 09:35:38 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 201876 kb
Host smart-d192350a-f3bd-44de-b416-87216ab17c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453469922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3453469922
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3902036191
Short name T265
Test name
Test status
Simulation time 545561713177 ps
CPU time 341.51 seconds
Started Jul 02 09:36:44 AM PDT 24
Finished Jul 02 09:42:26 AM PDT 24
Peak memory 201932 kb
Host smart-ce41f1ab-f7ac-4b62-9f50-996a308574d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902036191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3902036191
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.817803600
Short name T34
Test name
Test status
Simulation time 334884393957 ps
CPU time 774.92 seconds
Started Jul 02 09:36:16 AM PDT 24
Finished Jul 02 09:49:11 AM PDT 24
Peak memory 201900 kb
Host smart-5c1f1a6e-eb9c-408e-9968-662d616e4749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817803600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.817803600
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2306549973
Short name T219
Test name
Test status
Simulation time 489944104906 ps
CPU time 561.44 seconds
Started Jul 02 09:37:14 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 201920 kb
Host smart-97725783-a12d-4fb3-8543-717e9df98cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306549973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2306549973
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2252114349
Short name T54
Test name
Test status
Simulation time 398977607455 ps
CPU time 942.29 seconds
Started Jul 02 09:37:14 AM PDT 24
Finished Jul 02 09:52:56 AM PDT 24
Peak memory 201912 kb
Host smart-e8cdbbe9-73ec-4003-b5b0-e20cc3ba823b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252114349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2252114349
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1012149585
Short name T53
Test name
Test status
Simulation time 88798915829 ps
CPU time 142.35 seconds
Started Jul 02 09:35:58 AM PDT 24
Finished Jul 02 09:38:21 AM PDT 24
Peak memory 211020 kb
Host smart-84062ec9-cb47-4c16-a8e2-7e1c2c32d851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012149585 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1012149585
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2732705244
Short name T184
Test name
Test status
Simulation time 333391690227 ps
CPU time 68.15 seconds
Started Jul 02 09:32:08 AM PDT 24
Finished Jul 02 09:33:16 AM PDT 24
Peak memory 201976 kb
Host smart-895fcbbd-8123-4c49-a677-59bb1f7528f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732705244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2732705244
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3480337869
Short name T281
Test name
Test status
Simulation time 525013869661 ps
CPU time 619.58 seconds
Started Jul 02 09:32:19 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 201880 kb
Host smart-f6a3e5f1-2887-4a9c-bdff-d489bffb4e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480337869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3480337869
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4051967870
Short name T41
Test name
Test status
Simulation time 661693537419 ps
CPU time 685.31 seconds
Started Jul 02 09:32:00 AM PDT 24
Finished Jul 02 09:43:26 AM PDT 24
Peak memory 201912 kb
Host smart-cc3d5c96-9f6c-4f02-ad7d-b4fb46b18ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051967870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4051967870
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3684830073
Short name T15
Test name
Test status
Simulation time 484368016 ps
CPU time 0.84 seconds
Started Jul 02 09:33:07 AM PDT 24
Finished Jul 02 09:33:08 AM PDT 24
Peak memory 201660 kb
Host smart-406df472-862f-4805-9a99-c0c00910be7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684830073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3684830073
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3832994515
Short name T290
Test name
Test status
Simulation time 541039764537 ps
CPU time 1311.06 seconds
Started Jul 02 09:35:17 AM PDT 24
Finished Jul 02 09:57:09 AM PDT 24
Peak memory 201840 kb
Host smart-53ed7413-890a-470b-9314-33fd4bf71318
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832994515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3832994515
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4197299516
Short name T294
Test name
Test status
Simulation time 325320507154 ps
CPU time 723.73 seconds
Started Jul 02 09:31:44 AM PDT 24
Finished Jul 02 09:43:48 AM PDT 24
Peak memory 201908 kb
Host smart-85145660-cdda-49c0-8b3a-67bf7951c5ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197299516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4197299516
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3393470501
Short name T92
Test name
Test status
Simulation time 4884474928 ps
CPU time 7.05 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:50:28 AM PDT 24
Peak memory 201804 kb
Host smart-5ae2ade0-4e35-481e-b202-faa1e13beb69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393470501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3393470501
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2513877685
Short name T238
Test name
Test status
Simulation time 456440093513 ps
CPU time 333.49 seconds
Started Jul 02 09:33:07 AM PDT 24
Finished Jul 02 09:38:41 AM PDT 24
Peak memory 210424 kb
Host smart-f300750d-b273-4d53-9ae0-36da31f31fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513877685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2513877685
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1391783775
Short name T327
Test name
Test status
Simulation time 493701518565 ps
CPU time 411.24 seconds
Started Jul 02 09:34:23 AM PDT 24
Finished Jul 02 09:41:15 AM PDT 24
Peak memory 201972 kb
Host smart-aa7c8b26-311b-4099-bbbf-286c65ebb453
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391783775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1391783775
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3145301142
Short name T264
Test name
Test status
Simulation time 537006901908 ps
CPU time 1248.73 seconds
Started Jul 02 09:36:23 AM PDT 24
Finished Jul 02 09:57:13 AM PDT 24
Peak memory 201984 kb
Host smart-51f022dd-fc8c-4476-8f4d-6dd5008309e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145301142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3145301142
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.147436322
Short name T277
Test name
Test status
Simulation time 238235742753 ps
CPU time 500.08 seconds
Started Jul 02 09:32:28 AM PDT 24
Finished Jul 02 09:40:48 AM PDT 24
Peak memory 201992 kb
Host smart-356fc63e-23c0-4b8c-bd4e-a0af085feaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147436322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.147436322
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.4166041371
Short name T234
Test name
Test status
Simulation time 990803903790 ps
CPU time 1128.85 seconds
Started Jul 02 09:37:05 AM PDT 24
Finished Jul 02 09:55:54 AM PDT 24
Peak memory 212284 kb
Host smart-e9e735e3-9ae4-40e3-a3c5-8e334755879d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166041371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.4166041371
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2402839962
Short name T303
Test name
Test status
Simulation time 561250890557 ps
CPU time 349.49 seconds
Started Jul 02 09:35:01 AM PDT 24
Finished Jul 02 09:40:51 AM PDT 24
Peak memory 201924 kb
Host smart-1385c87d-5fd1-4321-9652-7d6160731c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402839962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2402839962
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1461974719
Short name T20
Test name
Test status
Simulation time 756021728311 ps
CPU time 856.76 seconds
Started Jul 02 09:37:51 AM PDT 24
Finished Jul 02 09:52:08 AM PDT 24
Peak memory 210548 kb
Host smart-dbf72a37-f38c-43d6-99a6-7c40db04eea7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461974719 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1461974719
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2532316154
Short name T254
Test name
Test status
Simulation time 353624403475 ps
CPU time 791.42 seconds
Started Jul 02 09:31:57 AM PDT 24
Finished Jul 02 09:45:09 AM PDT 24
Peak memory 201916 kb
Host smart-004841ba-d720-40b5-a231-ce874a8c7802
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532316154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2532316154
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4016456113
Short name T259
Test name
Test status
Simulation time 493500731956 ps
CPU time 1162.62 seconds
Started Jul 02 09:33:01 AM PDT 24
Finished Jul 02 09:52:24 AM PDT 24
Peak memory 201880 kb
Host smart-b5348eab-f236-4982-8559-cba3029f357b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016456113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4016456113
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3369190611
Short name T301
Test name
Test status
Simulation time 67539228119 ps
CPU time 162.05 seconds
Started Jul 02 09:35:39 AM PDT 24
Finished Jul 02 09:38:21 AM PDT 24
Peak memory 218280 kb
Host smart-45f2d9cb-7ee9-4a85-84c6-21bede35137e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369190611 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3369190611
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.852050131
Short name T333
Test name
Test status
Simulation time 157842305319 ps
CPU time 339.63 seconds
Started Jul 02 09:37:32 AM PDT 24
Finished Jul 02 09:43:12 AM PDT 24
Peak memory 201884 kb
Host smart-5b163959-245e-4aea-a951-0ec154cb8336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852050131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.852050131
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.994603943
Short name T73
Test name
Test status
Simulation time 5014319633 ps
CPU time 6.03 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 201912 kb
Host smart-75cc614c-3c5f-4b34-a234-81cc3519c590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994603943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.994603943
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.104780501
Short name T302
Test name
Test status
Simulation time 637430282440 ps
CPU time 381.7 seconds
Started Jul 02 09:32:04 AM PDT 24
Finished Jul 02 09:38:26 AM PDT 24
Peak memory 201968 kb
Host smart-c756e9d6-174f-41c5-b33e-3012c581afa2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104780501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.104780501
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1134702668
Short name T279
Test name
Test status
Simulation time 658301390525 ps
CPU time 437.95 seconds
Started Jul 02 09:35:09 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 201932 kb
Host smart-d7cc8e52-e540-4ee2-8b2c-4f7139f21b46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134702668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1134702668
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.625106760
Short name T98
Test name
Test status
Simulation time 496773083460 ps
CPU time 315.2 seconds
Started Jul 02 09:37:39 AM PDT 24
Finished Jul 02 09:42:55 AM PDT 24
Peak memory 201984 kb
Host smart-02c10a2c-da0a-4165-b69c-37200d065423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625106760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.625106760
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3687647652
Short name T282
Test name
Test status
Simulation time 365610892950 ps
CPU time 220.39 seconds
Started Jul 02 09:32:14 AM PDT 24
Finished Jul 02 09:35:55 AM PDT 24
Peak memory 202096 kb
Host smart-33e17746-2f09-468d-ba89-eb4fe91bbf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687647652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3687647652
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3340608072
Short name T239
Test name
Test status
Simulation time 185905640487 ps
CPU time 90 seconds
Started Jul 02 09:33:10 AM PDT 24
Finished Jul 02 09:34:40 AM PDT 24
Peak memory 201904 kb
Host smart-560f18f5-4191-4178-ad48-8f334ac66126
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340608072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3340608072
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2559071221
Short name T274
Test name
Test status
Simulation time 322393104741 ps
CPU time 674.94 seconds
Started Jul 02 09:33:06 AM PDT 24
Finished Jul 02 09:44:22 AM PDT 24
Peak memory 202000 kb
Host smart-1470f246-9ab8-4a6b-8a51-b8ee014de706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559071221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2559071221
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2244599112
Short name T256
Test name
Test status
Simulation time 510048714081 ps
CPU time 320.04 seconds
Started Jul 02 09:34:29 AM PDT 24
Finished Jul 02 09:39:49 AM PDT 24
Peak memory 201848 kb
Host smart-fe3e0cdd-0b98-459d-bfae-70b53f242961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244599112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2244599112
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3073845482
Short name T311
Test name
Test status
Simulation time 164912375685 ps
CPU time 99.26 seconds
Started Jul 02 09:31:02 AM PDT 24
Finished Jul 02 09:32:42 AM PDT 24
Peak memory 201972 kb
Host smart-e60a4a95-31e6-4390-acf5-8234362ba425
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073845482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3073845482
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.397544482
Short name T258
Test name
Test status
Simulation time 563866159777 ps
CPU time 2002.3 seconds
Started Jul 02 09:32:56 AM PDT 24
Finished Jul 02 10:06:19 AM PDT 24
Peak memory 202216 kb
Host smart-fd532686-c2fe-4b61-8369-a0f783c86251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397544482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
397544482
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4008356767
Short name T51
Test name
Test status
Simulation time 82289355663 ps
CPU time 85.24 seconds
Started Jul 02 09:33:18 AM PDT 24
Finished Jul 02 09:34:44 AM PDT 24
Peak memory 213880 kb
Host smart-86fbf7f7-fb9d-4045-b3a5-d3619b96e6ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008356767 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4008356767
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.954091298
Short name T167
Test name
Test status
Simulation time 192078404330 ps
CPU time 139.04 seconds
Started Jul 02 09:33:43 AM PDT 24
Finished Jul 02 09:36:02 AM PDT 24
Peak memory 201988 kb
Host smart-a609dd33-c9fd-4e35-8eb4-d3438dfb45fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954091298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.954091298
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.174621342
Short name T161
Test name
Test status
Simulation time 621848559962 ps
CPU time 315.14 seconds
Started Jul 02 09:35:17 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 201872 kb
Host smart-ea40bad2-a84e-407d-b4b9-9c223b854326
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174621342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.174621342
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3476198272
Short name T276
Test name
Test status
Simulation time 336775831462 ps
CPU time 385.7 seconds
Started Jul 02 09:35:33 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 201960 kb
Host smart-3b30b3fb-347f-489f-af6a-03526d627a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476198272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3476198272
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.4274668877
Short name T267
Test name
Test status
Simulation time 510997066594 ps
CPU time 1147.87 seconds
Started Jul 02 09:37:32 AM PDT 24
Finished Jul 02 09:56:41 AM PDT 24
Peak memory 201900 kb
Host smart-f6580769-6fe3-4f0c-87c2-5d8825555111
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274668877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.4274668877
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1215448446
Short name T214
Test name
Test status
Simulation time 286468646402 ps
CPU time 151.74 seconds
Started Jul 02 09:31:40 AM PDT 24
Finished Jul 02 09:34:13 AM PDT 24
Peak memory 210224 kb
Host smart-7607afda-d034-460d-8876-c9f38397aeac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215448446 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1215448446
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.209352768
Short name T300
Test name
Test status
Simulation time 168439939391 ps
CPU time 107.15 seconds
Started Jul 02 09:31:47 AM PDT 24
Finished Jul 02 09:33:35 AM PDT 24
Peak memory 201924 kb
Host smart-13112d34-06cc-4510-a7a6-6dc631017e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209352768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.209352768
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3583198850
Short name T94
Test name
Test status
Simulation time 8529533864 ps
CPU time 20.24 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 201812 kb
Host smart-e780cff4-3b20-4560-b2b1-139c4488ea16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583198850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3583198850
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2399968462
Short name T246
Test name
Test status
Simulation time 338805910716 ps
CPU time 113.5 seconds
Started Jul 02 09:35:27 AM PDT 24
Finished Jul 02 09:37:21 AM PDT 24
Peak memory 201884 kb
Host smart-fde18429-a67d-4897-b789-47121228857b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399968462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2399968462
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3321219364
Short name T221
Test name
Test status
Simulation time 105775666955 ps
CPU time 552.79 seconds
Started Jul 02 09:32:12 AM PDT 24
Finished Jul 02 09:41:25 AM PDT 24
Peak memory 202268 kb
Host smart-1c8db2e2-d34e-497d-8e5d-1cfa21b5e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321219364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3321219364
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2417551648
Short name T194
Test name
Test status
Simulation time 487566216875 ps
CPU time 99.91 seconds
Started Jul 02 09:32:27 AM PDT 24
Finished Jul 02 09:34:07 AM PDT 24
Peak memory 201884 kb
Host smart-7ca7d17c-b5c7-4a3d-b20d-cf0e5e703fe1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417551648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2417551648
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.158479229
Short name T230
Test name
Test status
Simulation time 123684228900 ps
CPU time 390.86 seconds
Started Jul 02 09:33:20 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 202236 kb
Host smart-6ef1a73b-c0cf-49dc-8e32-5f8f25946078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158479229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.158479229
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4267680215
Short name T49
Test name
Test status
Simulation time 364252765308 ps
CPU time 752.97 seconds
Started Jul 02 09:33:18 AM PDT 24
Finished Jul 02 09:45:51 AM PDT 24
Peak memory 201912 kb
Host smart-b7730dd6-e17e-42ca-983e-10bb1a846243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267680215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4267680215
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4270794745
Short name T315
Test name
Test status
Simulation time 203352616170 ps
CPU time 28.65 seconds
Started Jul 02 09:31:12 AM PDT 24
Finished Jul 02 09:31:41 AM PDT 24
Peak memory 201984 kb
Host smart-05047a73-e876-4b7e-abdc-e21ad028114b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270794745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4270794745
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2436500924
Short name T263
Test name
Test status
Simulation time 333833215375 ps
CPU time 756.89 seconds
Started Jul 02 09:33:45 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 201912 kb
Host smart-bcfbf34a-c109-47bd-9724-7fef3cd3ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436500924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2436500924
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2775933737
Short name T223
Test name
Test status
Simulation time 122635662977 ps
CPU time 469.47 seconds
Started Jul 02 09:34:40 AM PDT 24
Finished Jul 02 09:42:29 AM PDT 24
Peak memory 202216 kb
Host smart-7fa30ee2-6648-4720-ba44-4e3b7df6f592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775933737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2775933737
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1343696623
Short name T169
Test name
Test status
Simulation time 335682925996 ps
CPU time 770.68 seconds
Started Jul 02 09:31:15 AM PDT 24
Finished Jul 02 09:44:07 AM PDT 24
Peak memory 201960 kb
Host smart-f489bd96-78b0-4abd-9c12-781bc2be593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343696623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1343696623
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2526672242
Short name T257
Test name
Test status
Simulation time 533184690191 ps
CPU time 1179.36 seconds
Started Jul 02 09:35:38 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 201924 kb
Host smart-d86b1c3e-e39c-4dfe-be62-3f5b9d6be257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526672242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2526672242
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3197957965
Short name T342
Test name
Test status
Simulation time 355507810303 ps
CPU time 823.2 seconds
Started Jul 02 09:36:15 AM PDT 24
Finished Jul 02 09:49:59 AM PDT 24
Peak memory 201900 kb
Host smart-809493b4-b170-45c2-a25b-604a6375b2e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197957965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3197957965
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.971420489
Short name T35
Test name
Test status
Simulation time 133329046278 ps
CPU time 233.01 seconds
Started Jul 02 09:31:54 AM PDT 24
Finished Jul 02 09:35:47 AM PDT 24
Peak memory 211056 kb
Host smart-810b15f5-f8b3-4ebd-93dc-1422e9a33d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971420489 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.971420489
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1377978405
Short name T840
Test name
Test status
Simulation time 1100637376 ps
CPU time 2.88 seconds
Started Jul 02 09:49:45 AM PDT 24
Finished Jul 02 09:49:51 AM PDT 24
Peak memory 211032 kb
Host smart-523842e5-1a44-4a9d-9c10-27fe24e481c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377978405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1377978405
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3840516930
Short name T358
Test name
Test status
Simulation time 8641997708 ps
CPU time 5.03 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 201820 kb
Host smart-42f1775a-5d6c-498f-84f2-69f4ec782884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840516930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3840516930
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2980948387
Short name T231
Test name
Test status
Simulation time 108777362346 ps
CPU time 444.73 seconds
Started Jul 02 09:30:52 AM PDT 24
Finished Jul 02 09:38:17 AM PDT 24
Peak memory 202244 kb
Host smart-5e9978bb-042a-49d9-bd22-8d4ce7b79c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980948387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2980948387
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.842234377
Short name T244
Test name
Test status
Simulation time 404334417474 ps
CPU time 242.39 seconds
Started Jul 02 09:31:02 AM PDT 24
Finished Jul 02 09:35:05 AM PDT 24
Peak memory 201880 kb
Host smart-34a95849-4339-45b4-831d-15e6e8867733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842234377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.842234377
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1438633362
Short name T106
Test name
Test status
Simulation time 31372169134 ps
CPU time 81.91 seconds
Started Jul 02 09:33:46 AM PDT 24
Finished Jul 02 09:35:08 AM PDT 24
Peak memory 210552 kb
Host smart-e684d40a-76aa-496d-bd23-4c12526fa175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438633362 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1438633362
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2263025717
Short name T331
Test name
Test status
Simulation time 545398083815 ps
CPU time 176.91 seconds
Started Jul 02 09:33:51 AM PDT 24
Finished Jul 02 09:36:48 AM PDT 24
Peak memory 201988 kb
Host smart-c29f32b3-a38d-4cf6-be95-33652f85a3a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263025717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2263025717
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2871122066
Short name T319
Test name
Test status
Simulation time 107013975366 ps
CPU time 153.42 seconds
Started Jul 02 09:34:39 AM PDT 24
Finished Jul 02 09:37:13 AM PDT 24
Peak memory 210416 kb
Host smart-63074427-08c5-4592-aabb-504fbaed8df3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871122066 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2871122066
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3019650869
Short name T287
Test name
Test status
Simulation time 516239330637 ps
CPU time 1031.02 seconds
Started Jul 02 09:34:47 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 201936 kb
Host smart-a86bc475-cc36-45e0-9d76-f3bbe329351c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019650869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3019650869
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.277244216
Short name T235
Test name
Test status
Simulation time 402193735414 ps
CPU time 797.95 seconds
Started Jul 02 09:36:08 AM PDT 24
Finished Jul 02 09:49:26 AM PDT 24
Peak memory 210416 kb
Host smart-20f9c201-1260-4bef-823c-7893fb972200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277244216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
277244216
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.691891398
Short name T139
Test name
Test status
Simulation time 808054217 ps
CPU time 1.73 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 201676 kb
Host smart-e8afcc39-596a-4c01-804f-02ef509d3598
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691891398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.691891398
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2198975555
Short name T828
Test name
Test status
Simulation time 1196228546 ps
CPU time 2.17 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 201512 kb
Host smart-60b70c59-f921-45cf-b204-c11090bddee5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198975555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2198975555
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1815226256
Short name T835
Test name
Test status
Simulation time 386709000 ps
CPU time 1.17 seconds
Started Jul 02 09:49:58 AM PDT 24
Finished Jul 02 09:50:07 AM PDT 24
Peak memory 201504 kb
Host smart-79e07913-1db6-4369-aac3-714de0d4e21a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815226256 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1815226256
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.436480545
Short name T133
Test name
Test status
Simulation time 384090176 ps
CPU time 1.66 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 201444 kb
Host smart-878312a6-1340-44ec-a8ce-e2280c3e9553
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436480545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.436480545
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4223985267
Short name T918
Test name
Test status
Simulation time 524996339 ps
CPU time 1.28 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:12 AM PDT 24
Peak memory 201392 kb
Host smart-7b24bd07-6935-43cb-83ba-cace1a792d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223985267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4223985267
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3117264078
Short name T849
Test name
Test status
Simulation time 8032620347 ps
CPU time 16.37 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:16 AM PDT 24
Peak memory 201868 kb
Host smart-e0c19bd1-83b7-471f-83dc-84cab37c0a57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117264078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3117264078
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3953592008
Short name T153
Test name
Test status
Simulation time 952927624 ps
CPU time 4.39 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:50:00 AM PDT 24
Peak memory 201656 kb
Host smart-55eaf71d-23e1-4f4f-9338-83f95728ab8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953592008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3953592008
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.82194492
Short name T129
Test name
Test status
Simulation time 23961811490 ps
CPU time 22.27 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 201892 kb
Host smart-4f619435-78d7-478a-a1be-0677df6a1fc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82194492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_ba
sh.82194492
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2650619871
Short name T845
Test name
Test status
Simulation time 893365536 ps
CPU time 0.98 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 201520 kb
Host smart-01d31286-7318-40ae-899f-4691f72a25c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650619871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2650619871
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3846626328
Short name T830
Test name
Test status
Simulation time 476384514 ps
CPU time 0.99 seconds
Started Jul 02 09:49:57 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 201600 kb
Host smart-e79514eb-7d67-4e4c-8528-81d4182718ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846626328 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3846626328
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3025960437
Short name T873
Test name
Test status
Simulation time 513322723 ps
CPU time 0.87 seconds
Started Jul 02 09:49:55 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 201524 kb
Host smart-50dc4f01-df08-48ad-99ce-b37552f7f52d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025960437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3025960437
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2754983829
Short name T858
Test name
Test status
Simulation time 424099957 ps
CPU time 1.56 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:22 AM PDT 24
Peak memory 201424 kb
Host smart-251253fa-fd01-4448-bdd7-7a68975711c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754983829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2754983829
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3783753300
Short name T876
Test name
Test status
Simulation time 4355714301 ps
CPU time 3.23 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:08 AM PDT 24
Peak memory 201820 kb
Host smart-306b92d1-1f38-425f-b373-6a2636747182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783753300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3783753300
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1418055873
Short name T903
Test name
Test status
Simulation time 839403968 ps
CPU time 3.06 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:07 AM PDT 24
Peak memory 210008 kb
Host smart-6dfb4692-e412-4f12-b04e-8acbfd1d9c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418055873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1418055873
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1051541437
Short name T888
Test name
Test status
Simulation time 8627475270 ps
CPU time 22.77 seconds
Started Jul 02 09:49:48 AM PDT 24
Finished Jul 02 09:50:16 AM PDT 24
Peak memory 201900 kb
Host smart-2d281135-471b-443b-b129-243fec50dbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051541437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1051541437
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2615265099
Short name T829
Test name
Test status
Simulation time 479019064 ps
CPU time 1.99 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:20 AM PDT 24
Peak memory 201572 kb
Host smart-c1cf563d-4190-4c65-8229-e00cccc5e272
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615265099 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2615265099
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2823155865
Short name T134
Test name
Test status
Simulation time 427537480 ps
CPU time 1.75 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 201732 kb
Host smart-4dc2b31b-e178-43db-94bf-d4686e6c6353
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823155865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2823155865
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.97359274
Short name T812
Test name
Test status
Simulation time 459442544 ps
CPU time 1.67 seconds
Started Jul 02 09:50:01 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 201440 kb
Host smart-1364acb5-72fe-460b-b124-78f07a624fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97359274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.97359274
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1787884892
Short name T834
Test name
Test status
Simulation time 2276711189 ps
CPU time 2.25 seconds
Started Jul 02 09:50:16 AM PDT 24
Finished Jul 02 09:50:26 AM PDT 24
Peak memory 201636 kb
Host smart-905e9b27-7eed-4c63-acc8-30116c621718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787884892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1787884892
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1555406400
Short name T891
Test name
Test status
Simulation time 575968075 ps
CPU time 1.39 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201516 kb
Host smart-f0960e80-2c3e-4387-91eb-4e2bbaaba061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555406400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1555406400
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.884228456
Short name T880
Test name
Test status
Simulation time 448233854 ps
CPU time 1.08 seconds
Started Jul 02 09:49:55 AM PDT 24
Finished Jul 02 09:50:04 AM PDT 24
Peak memory 201584 kb
Host smart-f74b3ad0-1ec0-4be8-890d-1ff052390ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884228456 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.884228456
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3424592830
Short name T145
Test name
Test status
Simulation time 401530660 ps
CPU time 1.78 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:09 AM PDT 24
Peak memory 201512 kb
Host smart-1c86cf06-b0dc-45ac-bf0e-1a5875d797c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424592830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3424592830
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2658101418
Short name T816
Test name
Test status
Simulation time 564406273 ps
CPU time 0.76 seconds
Started Jul 02 09:50:07 AM PDT 24
Finished Jul 02 09:50:16 AM PDT 24
Peak memory 201436 kb
Host smart-9c2423e9-73a7-4807-8fee-e752cd355c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658101418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2658101418
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1646017561
Short name T72
Test name
Test status
Simulation time 4035584796 ps
CPU time 3.29 seconds
Started Jul 02 09:50:16 AM PDT 24
Finished Jul 02 09:50:28 AM PDT 24
Peak memory 201864 kb
Host smart-3745f423-4509-480a-bccf-28dddd7e87e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646017561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1646017561
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2842415016
Short name T856
Test name
Test status
Simulation time 482482384 ps
CPU time 2.12 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:30 AM PDT 24
Peak memory 201724 kb
Host smart-39baf7ab-2863-40ce-8b02-a4b2607d4ae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842415016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2842415016
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2229254879
Short name T894
Test name
Test status
Simulation time 4377023882 ps
CPU time 4.03 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:15 AM PDT 24
Peak memory 201884 kb
Host smart-c41c342b-a13c-4553-91c1-0d756b367c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229254879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2229254879
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.251127471
Short name T917
Test name
Test status
Simulation time 425581883 ps
CPU time 1.88 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:15 AM PDT 24
Peak memory 201568 kb
Host smart-cea27c7d-e518-42c5-adb1-e8cc15889b30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251127471 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.251127471
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1436975397
Short name T848
Test name
Test status
Simulation time 447453709 ps
CPU time 0.8 seconds
Started Jul 02 09:50:26 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 201484 kb
Host smart-86797f98-ef10-443c-bd48-c54872f95bf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436975397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1436975397
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2248090666
Short name T825
Test name
Test status
Simulation time 441200036 ps
CPU time 1.17 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 201464 kb
Host smart-a229afa7-3d8e-483d-8c31-ec2aa375cbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248090666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2248090666
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.656454798
Short name T846
Test name
Test status
Simulation time 3739739464 ps
CPU time 8.25 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 201820 kb
Host smart-4a9b2487-513a-4150-b1f4-f579834a6219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656454798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.656454798
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4137616320
Short name T914
Test name
Test status
Simulation time 530790154 ps
CPU time 1.85 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:20 AM PDT 24
Peak memory 201784 kb
Host smart-ee9077c9-c86d-4632-bad6-086fd4021d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137616320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4137616320
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3567783559
Short name T93
Test name
Test status
Simulation time 4532791175 ps
CPU time 12.44 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:32 AM PDT 24
Peak memory 201880 kb
Host smart-8d20b2a2-bc6d-4468-a056-495e8ec71c04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567783559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3567783559
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.408677482
Short name T819
Test name
Test status
Simulation time 392557550 ps
CPU time 1.6 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 201576 kb
Host smart-d621d7bc-b658-4a09-9a41-78d9fd5a10a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408677482 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.408677482
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1425278259
Short name T902
Test name
Test status
Simulation time 541783953 ps
CPU time 0.97 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 201732 kb
Host smart-dd5e8c88-c1b9-4439-be14-cf76c6918401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425278259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1425278259
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1755498781
Short name T841
Test name
Test status
Simulation time 406724044 ps
CPU time 0.88 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:20 AM PDT 24
Peak memory 201432 kb
Host smart-19d0655a-6037-4a2d-8f3f-1248ec1cb3ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755498781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1755498781
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2002376559
Short name T839
Test name
Test status
Simulation time 4665306355 ps
CPU time 3.9 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:23 AM PDT 24
Peak memory 201860 kb
Host smart-9a11cc6d-e83a-4a5e-a562-2b600b353943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002376559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2002376559
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1570589729
Short name T861
Test name
Test status
Simulation time 298272478 ps
CPU time 1.98 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:22 AM PDT 24
Peak memory 201756 kb
Host smart-e40e15b1-40d9-4c2e-afb5-99fccc1d8449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570589729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1570589729
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.467429495
Short name T75
Test name
Test status
Simulation time 8154264118 ps
CPU time 23.08 seconds
Started Jul 02 09:50:16 AM PDT 24
Finished Jul 02 09:50:49 AM PDT 24
Peak memory 201884 kb
Host smart-c16f7958-94f5-451b-b41e-775e72584c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467429495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.467429495
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3379208401
Short name T890
Test name
Test status
Simulation time 489187470 ps
CPU time 1.98 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201504 kb
Host smart-b86057be-31d2-4b8d-b26a-a19b0298d77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379208401 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3379208401
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2048428072
Short name T813
Test name
Test status
Simulation time 403609334 ps
CPU time 1.18 seconds
Started Jul 02 09:50:33 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 201420 kb
Host smart-13d33bd7-831d-4155-9e55-2c98d9c13770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048428072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2048428072
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3387455250
Short name T915
Test name
Test status
Simulation time 494951576 ps
CPU time 1.71 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201432 kb
Host smart-be28bfc0-7f4a-428e-8910-353e09c2d3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387455250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3387455250
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1574285027
Short name T865
Test name
Test status
Simulation time 4586618233 ps
CPU time 3.29 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 201896 kb
Host smart-234168a6-5ca3-4945-9123-8b05f86bdf22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574285027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1574285027
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1472743966
Short name T872
Test name
Test status
Simulation time 884203121 ps
CPU time 2.66 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201712 kb
Host smart-c275b944-cdfe-4ae9-b0e1-999f807fad55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472743966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1472743966
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3890513302
Short name T850
Test name
Test status
Simulation time 4855036316 ps
CPU time 4.11 seconds
Started Jul 02 09:50:06 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201776 kb
Host smart-3f37b663-d259-4454-910b-471099fe9275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890513302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3890513302
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4258837306
Short name T904
Test name
Test status
Simulation time 642866440 ps
CPU time 1.64 seconds
Started Jul 02 09:50:25 AM PDT 24
Finished Jul 02 09:50:35 AM PDT 24
Peak memory 209992 kb
Host smart-bcb68b9c-f8c2-4fd9-98de-3a54e488d781
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258837306 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.4258837306
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3769407446
Short name T149
Test name
Test status
Simulation time 473698821 ps
CPU time 1.93 seconds
Started Jul 02 09:50:37 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 201420 kb
Host smart-75f78160-4d14-4339-9661-b044eba1cf0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769407446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3769407446
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2005005022
Short name T859
Test name
Test status
Simulation time 580974112 ps
CPU time 0.77 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:08 AM PDT 24
Peak memory 201412 kb
Host smart-d3b19466-39f7-477d-ac7f-247a85987e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005005022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2005005022
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3217292205
Short name T823
Test name
Test status
Simulation time 1932970987 ps
CPU time 6.42 seconds
Started Jul 02 09:50:26 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 201528 kb
Host smart-d67a725f-e949-4ae5-94aa-b9702f079481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217292205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3217292205
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2804487468
Short name T908
Test name
Test status
Simulation time 501183252 ps
CPU time 2.34 seconds
Started Jul 02 09:50:27 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 218100 kb
Host smart-ca9731b2-83e9-4e30-9c84-0b1a691348f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804487468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2804487468
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3558891432
Short name T359
Test name
Test status
Simulation time 4166301094 ps
CPU time 6.55 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 201852 kb
Host smart-ee15792d-7592-47f3-988b-257da323da27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558891432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3558891432
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3324025819
Short name T836
Test name
Test status
Simulation time 538232220 ps
CPU time 2.1 seconds
Started Jul 02 09:50:07 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 201584 kb
Host smart-9df972c6-56e5-4feb-9829-dd6362ee43ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324025819 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3324025819
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3938054514
Short name T141
Test name
Test status
Simulation time 405007609 ps
CPU time 0.93 seconds
Started Jul 02 09:50:03 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 201504 kb
Host smart-004d844d-3ea3-4678-815a-0d221486b0ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938054514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3938054514
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2867734827
Short name T805
Test name
Test status
Simulation time 346498021 ps
CPU time 1.47 seconds
Started Jul 02 09:50:18 AM PDT 24
Finished Jul 02 09:50:28 AM PDT 24
Peak memory 201456 kb
Host smart-47c99750-db8d-4a71-815a-93c9d4f4e59a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867734827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2867734827
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2170513539
Short name T74
Test name
Test status
Simulation time 2030887590 ps
CPU time 1.94 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 201524 kb
Host smart-128006bc-54b1-4d91-97cf-726703682d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170513539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2170513539
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2486946249
Short name T84
Test name
Test status
Simulation time 720085045 ps
CPU time 2.59 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:15 AM PDT 24
Peak memory 201804 kb
Host smart-72e27150-c2f6-468a-926d-8c1d309b373f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486946249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2486946249
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3879941560
Short name T896
Test name
Test status
Simulation time 531919663 ps
CPU time 1.33 seconds
Started Jul 02 09:50:32 AM PDT 24
Finished Jul 02 09:50:37 AM PDT 24
Peak memory 201524 kb
Host smart-5bc43118-0b47-47fc-b141-c6ed875e2405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879941560 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3879941560
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2445126379
Short name T132
Test name
Test status
Simulation time 440933896 ps
CPU time 1.79 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 201540 kb
Host smart-78d31de9-9af7-42e4-bea1-4fd159e65bac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445126379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2445126379
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3603486306
Short name T874
Test name
Test status
Simulation time 328593426 ps
CPU time 1 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 201428 kb
Host smart-22830f94-4e78-49c8-b8d6-e1df48466800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603486306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3603486306
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.449116220
Short name T147
Test name
Test status
Simulation time 4221971451 ps
CPU time 4.81 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201748 kb
Host smart-74a4df6e-f342-4789-b622-f74644dbdae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449116220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.449116220
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1088795174
Short name T898
Test name
Test status
Simulation time 441951451 ps
CPU time 2.25 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:50:31 AM PDT 24
Peak memory 201804 kb
Host smart-2bb18c95-cdbe-42fb-8851-b62dc12a488d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088795174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1088795174
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1899386329
Short name T855
Test name
Test status
Simulation time 4789615933 ps
CPU time 11.91 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:32 AM PDT 24
Peak memory 201848 kb
Host smart-5b35b0cf-608e-4af3-b037-47b7840c6d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899386329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1899386329
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4262461759
Short name T108
Test name
Test status
Simulation time 583654952 ps
CPU time 1.11 seconds
Started Jul 02 09:50:41 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 201520 kb
Host smart-94a0274a-2d05-40d2-8956-d9eb52f25298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262461759 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.4262461759
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1673999474
Short name T135
Test name
Test status
Simulation time 373635093 ps
CPU time 1.01 seconds
Started Jul 02 09:50:47 AM PDT 24
Finished Jul 02 09:50:49 AM PDT 24
Peak memory 201504 kb
Host smart-ead05133-559c-40f9-928a-8c4c6389def6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673999474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1673999474
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2653066081
Short name T901
Test name
Test status
Simulation time 530540030 ps
CPU time 0.93 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:50:37 AM PDT 24
Peak memory 201424 kb
Host smart-59645b10-9b87-4fec-a1c2-377fe7977094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653066081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2653066081
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1477019575
Short name T885
Test name
Test status
Simulation time 2379079904 ps
CPU time 9.3 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 201628 kb
Host smart-0c8b8f84-9a61-4c13-a17d-0eeb6506980a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477019575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1477019575
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2319216353
Short name T89
Test name
Test status
Simulation time 407309016 ps
CPU time 3.33 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:37 AM PDT 24
Peak memory 201716 kb
Host smart-e1d9a6f4-27d4-4f7c-91d9-874f8b051524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319216353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2319216353
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1419938117
Short name T912
Test name
Test status
Simulation time 4712751868 ps
CPU time 2.17 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:20 AM PDT 24
Peak memory 201880 kb
Host smart-0e0544f2-9b26-4b71-9889-d0dc77cea1df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419938117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1419938117
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.58206694
Short name T79
Test name
Test status
Simulation time 859415952 ps
CPU time 0.92 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:50:22 AM PDT 24
Peak memory 201552 kb
Host smart-b2f44546-144b-4ae9-8823-05bc84e83718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58206694 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.58206694
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1280934805
Short name T146
Test name
Test status
Simulation time 413787888 ps
CPU time 1.02 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201496 kb
Host smart-4148abcd-080e-4448-ba61-51aede958cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280934805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1280934805
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.459883473
Short name T900
Test name
Test status
Simulation time 505120682 ps
CPU time 1.66 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:50:32 AM PDT 24
Peak memory 201460 kb
Host smart-91be68f6-926c-4bd0-8683-7e0b33fa959b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459883473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.459883473
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.107388081
Short name T884
Test name
Test status
Simulation time 2334197127 ps
CPU time 4.99 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:30 AM PDT 24
Peak memory 201580 kb
Host smart-457a7365-8300-43ff-8fb5-3cff388fd1b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107388081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.107388081
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1953884107
Short name T905
Test name
Test status
Simulation time 700669894 ps
CPU time 2.83 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:32 AM PDT 24
Peak memory 211052 kb
Host smart-3c9b106c-ef80-4baf-a242-fac9ab7d804e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953884107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1953884107
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2201156324
Short name T77
Test name
Test status
Simulation time 8836246495 ps
CPU time 12.11 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:30 AM PDT 24
Peak memory 201872 kb
Host smart-5de6b643-cd9c-4253-b9d9-7903e61528aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201156324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2201156324
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3436321751
Short name T899
Test name
Test status
Simulation time 818020035 ps
CPU time 2.03 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:10 AM PDT 24
Peak memory 201708 kb
Host smart-0268c868-852b-4a00-9161-69d165dcf16f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436321751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3436321751
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2229662668
Short name T140
Test name
Test status
Simulation time 1303006417 ps
CPU time 6.47 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 201732 kb
Host smart-0f2d5649-b566-4f03-a331-c080c5d4ae75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229662668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2229662668
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1024457450
Short name T138
Test name
Test status
Simulation time 1455390412 ps
CPU time 1.65 seconds
Started Jul 02 09:50:16 AM PDT 24
Finished Jul 02 09:50:26 AM PDT 24
Peak memory 201492 kb
Host smart-e09928a0-82c7-4c10-a9ee-4291d4192613
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024457450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1024457450
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.640109914
Short name T886
Test name
Test status
Simulation time 600738622 ps
CPU time 1.12 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 201580 kb
Host smart-ea68d409-cb67-49c4-b52d-eab2b086d507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640109914 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.640109914
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1424722760
Short name T143
Test name
Test status
Simulation time 522210808 ps
CPU time 1.27 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 201732 kb
Host smart-ef3c57a8-3451-4d52-a837-1bde9e8c7997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424722760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1424722760
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2834971569
Short name T811
Test name
Test status
Simulation time 529438095 ps
CPU time 0.8 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 201464 kb
Host smart-9010b5fd-2785-45cb-b7ad-626e2955bbe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834971569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2834971569
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2467365632
Short name T862
Test name
Test status
Simulation time 3648901692 ps
CPU time 3.05 seconds
Started Jul 02 09:49:49 AM PDT 24
Finished Jul 02 09:49:57 AM PDT 24
Peak memory 201788 kb
Host smart-bc9c926d-8783-4808-ba93-19bd2004a616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467365632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2467365632
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3026639720
Short name T860
Test name
Test status
Simulation time 354126864 ps
CPU time 1.91 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 201800 kb
Host smart-54ab0756-0972-480e-83f9-3e24f1b286c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026639720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3026639720
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3229990707
Short name T360
Test name
Test status
Simulation time 8567606362 ps
CPU time 12.25 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:22 AM PDT 24
Peak memory 201728 kb
Host smart-35f7e2b9-3746-4d05-b893-2e5545b156a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229990707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3229990707
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3061877678
Short name T911
Test name
Test status
Simulation time 342257690 ps
CPU time 1.29 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 201404 kb
Host smart-eae12cd0-9fbc-4caa-bd59-e393cfa2a380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061877678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3061877678
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4056193045
Short name T881
Test name
Test status
Simulation time 436614760 ps
CPU time 1.62 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 201412 kb
Host smart-742e20ff-8e53-4b55-a5c5-a6aeab6c1931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056193045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4056193045
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.756003261
Short name T875
Test name
Test status
Simulation time 362405997 ps
CPU time 1.5 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 201456 kb
Host smart-bcfaf5fb-b387-4ea1-b1f2-c10c18013446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756003261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.756003261
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4270315143
Short name T818
Test name
Test status
Simulation time 526900815 ps
CPU time 0.95 seconds
Started Jul 02 09:50:16 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201404 kb
Host smart-d57dcead-c93d-4e50-b902-ea86fc2a6df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270315143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4270315143
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2179342115
Short name T868
Test name
Test status
Simulation time 479154322 ps
CPU time 1.73 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 201440 kb
Host smart-aa959713-c6e8-4f4a-82f2-2fae3542ccb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179342115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2179342115
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.853262328
Short name T810
Test name
Test status
Simulation time 493182386 ps
CPU time 1.2 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 201432 kb
Host smart-0be64453-d23a-4e2f-9ef0-0aac6a05db87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853262328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.853262328
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2181934632
Short name T877
Test name
Test status
Simulation time 454335590 ps
CPU time 1.72 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201444 kb
Host smart-3b719181-1bb8-459c-9afa-acd0a9e05a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181934632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2181934632
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2060071603
Short name T916
Test name
Test status
Simulation time 453295198 ps
CPU time 1.69 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 201420 kb
Host smart-08b1147b-b57a-4dd7-98d0-e94c7660ad64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060071603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2060071603
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.293611120
Short name T866
Test name
Test status
Simulation time 311763848 ps
CPU time 1.32 seconds
Started Jul 02 09:50:18 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 201456 kb
Host smart-74f7877a-9311-4df0-94b5-31bd54ac573d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293611120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.293611120
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3934622246
Short name T863
Test name
Test status
Simulation time 383163872 ps
CPU time 1.08 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 201464 kb
Host smart-9c85a016-83f6-4690-93b1-e369899bab0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934622246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3934622246
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3639304794
Short name T852
Test name
Test status
Simulation time 1277041759 ps
CPU time 1.73 seconds
Started Jul 02 09:50:35 AM PDT 24
Finished Jul 02 09:50:40 AM PDT 24
Peak memory 201632 kb
Host smart-8fd3664a-00c9-4c8c-a0ef-20e3ca63f04f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639304794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3639304794
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3498316435
Short name T144
Test name
Test status
Simulation time 8189030564 ps
CPU time 11.17 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 201796 kb
Host smart-f5fbe992-97db-41b2-9936-b3b973c5c0cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498316435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3498316435
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.682573234
Short name T142
Test name
Test status
Simulation time 1029335793 ps
CPU time 0.93 seconds
Started Jul 02 09:50:18 AM PDT 24
Finished Jul 02 09:50:28 AM PDT 24
Peak memory 201484 kb
Host smart-3797fdcb-9e64-48b0-93a7-d9110e46fe3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682573234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.682573234
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.684810920
Short name T91
Test name
Test status
Simulation time 596262522 ps
CPU time 2.26 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 201528 kb
Host smart-4d9021d4-e7cc-4477-a822-a310e3a52060
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684810920 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.684810920
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3942082859
Short name T906
Test name
Test status
Simulation time 412690423 ps
CPU time 1.38 seconds
Started Jul 02 09:50:25 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 201544 kb
Host smart-ab11b7a4-2df8-449d-97d2-1d4fad87c838
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942082859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3942082859
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2807336480
Short name T807
Test name
Test status
Simulation time 395948529 ps
CPU time 1.57 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 201424 kb
Host smart-41652c3d-ec82-41bf-bcce-5c7de2682ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807336480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2807336480
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4106849860
Short name T867
Test name
Test status
Simulation time 4579917716 ps
CPU time 3.95 seconds
Started Jul 02 09:50:01 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 201848 kb
Host smart-8fa28d9b-8af5-4da5-88a6-4e5ed5bbddcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106849860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4106849860
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2159058942
Short name T878
Test name
Test status
Simulation time 788720028 ps
CPU time 1.64 seconds
Started Jul 02 09:49:55 AM PDT 24
Finished Jul 02 09:50:04 AM PDT 24
Peak memory 201812 kb
Host smart-a5cb7092-763e-4f51-884c-38486371f963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159058942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2159058942
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3594319349
Short name T85
Test name
Test status
Simulation time 8692642634 ps
CPU time 22.36 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 201868 kb
Host smart-6be6d2c8-da21-4091-a68e-340ad142f553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594319349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3594319349
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4233589907
Short name T857
Test name
Test status
Simulation time 378740238 ps
CPU time 0.78 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201432 kb
Host smart-66156eab-fd7f-4e39-9efa-9c8ed89b5ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233589907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4233589907
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2445809430
Short name T843
Test name
Test status
Simulation time 298543498 ps
CPU time 1.3 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 201428 kb
Host smart-949c2809-d018-4272-9750-88d120d89adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445809430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2445809430
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1077712998
Short name T814
Test name
Test status
Simulation time 375656564 ps
CPU time 1.57 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 201452 kb
Host smart-ce3a073c-be1d-42cc-91ab-e29c5cfd7e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077712998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1077712998
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2775609280
Short name T821
Test name
Test status
Simulation time 333199699 ps
CPU time 1.4 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201380 kb
Host smart-cb221ac7-efeb-4969-898f-3c746eadc1c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775609280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2775609280
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.622672941
Short name T893
Test name
Test status
Simulation time 506191867 ps
CPU time 1.35 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 201364 kb
Host smart-2c33a21a-9641-47bb-a062-d96a0b8f8371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622672941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.622672941
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2784879880
Short name T806
Test name
Test status
Simulation time 393692914 ps
CPU time 1.55 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201452 kb
Host smart-853a3fe4-0fa9-478b-98a5-5ae4c22a4229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784879880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2784879880
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3785375688
Short name T889
Test name
Test status
Simulation time 527268163 ps
CPU time 0.9 seconds
Started Jul 02 09:50:03 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 201448 kb
Host smart-14398e3a-da6f-4510-b010-3cd3644e5135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785375688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3785375688
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3783479212
Short name T853
Test name
Test status
Simulation time 369085108 ps
CPU time 1.43 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 201464 kb
Host smart-320c2e47-9b2f-4f4d-84c7-9f9a1d88c8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783479212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3783479212
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1701453247
Short name T808
Test name
Test status
Simulation time 353154468 ps
CPU time 0.76 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201456 kb
Host smart-0155faab-09d1-4aca-91d8-9b5c7ebe4470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701453247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1701453247
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2774441136
Short name T815
Test name
Test status
Simulation time 397581127 ps
CPU time 1.59 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201460 kb
Host smart-425be402-4eda-4873-b91b-a90fadad4708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774441136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2774441136
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.723096081
Short name T137
Test name
Test status
Simulation time 962534558 ps
CPU time 3.39 seconds
Started Jul 02 09:50:07 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201740 kb
Host smart-a702cd4e-9a15-4fa7-8e9f-752866b9fb03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723096081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.723096081
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.9493021
Short name T154
Test name
Test status
Simulation time 52648057299 ps
CPU time 35.88 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 201828 kb
Host smart-463dfc03-cda3-4d10-a78b-1ffbc177e227
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9493021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bas
h.9493021
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4040508132
Short name T869
Test name
Test status
Simulation time 718496755 ps
CPU time 2.39 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 201532 kb
Host smart-7cb10ad5-284f-40bd-a161-ebc4e0287b24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040508132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4040508132
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1054857306
Short name T913
Test name
Test status
Simulation time 528509087 ps
CPU time 1.93 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:28 AM PDT 24
Peak memory 201556 kb
Host smart-31a777d6-8bd1-4771-a464-e480686452f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054857306 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1054857306
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.756797048
Short name T136
Test name
Test status
Simulation time 397362255 ps
CPU time 1.03 seconds
Started Jul 02 09:50:03 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 201484 kb
Host smart-e118c786-879f-4099-9a8d-af49e876de45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756797048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.756797048
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.392507299
Short name T851
Test name
Test status
Simulation time 289493451 ps
CPU time 1.23 seconds
Started Jul 02 09:50:25 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 201344 kb
Host smart-d68077d3-62da-4ddb-b960-2eb8b5d7129b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392507299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.392507299
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.335978067
Short name T887
Test name
Test status
Simulation time 4716525789 ps
CPU time 11.66 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 201872 kb
Host smart-71c59002-7437-4274-8c2b-bee6f0066207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335978067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.335978067
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.580344913
Short name T833
Test name
Test status
Simulation time 400538829 ps
CPU time 2.12 seconds
Started Jul 02 09:49:59 AM PDT 24
Finished Jul 02 09:50:08 AM PDT 24
Peak memory 201752 kb
Host smart-59c76728-94d6-4b30-a156-3545c8977815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580344913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.580344913
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2903580001
Short name T76
Test name
Test status
Simulation time 3709242243 ps
CPU time 10.64 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:20 AM PDT 24
Peak memory 201896 kb
Host smart-5ac733d2-1d65-48a9-aea6-0dcf354f8e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903580001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2903580001
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3964370853
Short name T838
Test name
Test status
Simulation time 428098627 ps
CPU time 1.64 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:50:31 AM PDT 24
Peak memory 201420 kb
Host smart-ac586aff-fe81-4bc2-9859-54322b431f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964370853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3964370853
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4153824655
Short name T910
Test name
Test status
Simulation time 442103489 ps
CPU time 1.13 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 201452 kb
Host smart-902d9be1-d822-42ae-a647-8861eca91792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153824655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4153824655
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3407514098
Short name T864
Test name
Test status
Simulation time 313180999 ps
CPU time 1.35 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:35 AM PDT 24
Peak memory 201448 kb
Host smart-fb4cdde8-216f-400f-ae53-fbd9fa2ae2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407514098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3407514098
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3994462135
Short name T870
Test name
Test status
Simulation time 358609637 ps
CPU time 1.11 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:20 AM PDT 24
Peak memory 201416 kb
Host smart-c69fec90-b778-4614-91df-b96bd29d2021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994462135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3994462135
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3824066124
Short name T822
Test name
Test status
Simulation time 482929256 ps
CPU time 0.81 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 201416 kb
Host smart-70e89a57-9a3d-48e5-b9a9-ee1dd8fc361d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824066124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3824066124
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2431662797
Short name T831
Test name
Test status
Simulation time 316694659 ps
CPU time 1.3 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:23 AM PDT 24
Peak memory 201440 kb
Host smart-5dad362c-f306-4de4-b9cf-a28e25f8a138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431662797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2431662797
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1687101378
Short name T804
Test name
Test status
Simulation time 358747291 ps
CPU time 0.98 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 201452 kb
Host smart-f647ccbe-2e5a-4b00-bc8c-fc0b89797ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687101378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1687101378
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3047527303
Short name T847
Test name
Test status
Simulation time 537597891 ps
CPU time 1.23 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:30 AM PDT 24
Peak memory 201452 kb
Host smart-cc7f4d38-a4ec-427c-88c3-0433a68bc6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047527303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3047527303
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1296743486
Short name T882
Test name
Test status
Simulation time 506991692 ps
CPU time 1.78 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201452 kb
Host smart-1e7378d4-d092-45a6-99e7-ebee9a3c0c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296743486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1296743486
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3279052026
Short name T824
Test name
Test status
Simulation time 497105099 ps
CPU time 0.87 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 201456 kb
Host smart-b361fc1f-6e87-4901-95bb-d965c87fc40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279052026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3279052026
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.73453089
Short name T87
Test name
Test status
Simulation time 671080056 ps
CPU time 1.66 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 201752 kb
Host smart-eab384a4-3d60-4c42-a1df-bac5fd56a478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73453089 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.73453089
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3678890664
Short name T131
Test name
Test status
Simulation time 526212854 ps
CPU time 1.98 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:20 AM PDT 24
Peak memory 201504 kb
Host smart-8aacfbc9-51da-480e-8fb5-2b3470fd3edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678890664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3678890664
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3992802708
Short name T809
Test name
Test status
Simulation time 512134624 ps
CPU time 1.72 seconds
Started Jul 02 09:49:54 AM PDT 24
Finished Jul 02 09:50:04 AM PDT 24
Peak memory 201424 kb
Host smart-bf7b686d-c72d-44c1-a736-933793fb3379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992802708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3992802708
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3133717981
Short name T897
Test name
Test status
Simulation time 4564176054 ps
CPU time 2.4 seconds
Started Jul 02 09:50:30 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 201880 kb
Host smart-176ef999-f069-456a-a82e-1dcd46d7e261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133717981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3133717981
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1742961525
Short name T826
Test name
Test status
Simulation time 416835127 ps
CPU time 1.48 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 201780 kb
Host smart-17766710-27b6-4eee-a456-96ae26b877d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742961525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1742961525
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2424665437
Short name T909
Test name
Test status
Simulation time 8139327837 ps
CPU time 7.22 seconds
Started Jul 02 09:50:18 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 201748 kb
Host smart-37a31f7e-8b62-4bcb-b939-c681715cef7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424665437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2424665437
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1931554345
Short name T892
Test name
Test status
Simulation time 473537973 ps
CPU time 1.94 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:02 AM PDT 24
Peak memory 201592 kb
Host smart-cc4be424-65e5-4902-a376-8e73958032a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931554345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1931554345
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4056313220
Short name T151
Test name
Test status
Simulation time 478170677 ps
CPU time 1.83 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 201472 kb
Host smart-1735576d-038a-4f61-984e-72664644b790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056313220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4056313220
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4128813404
Short name T854
Test name
Test status
Simulation time 393759000 ps
CPU time 1.59 seconds
Started Jul 02 09:50:16 AM PDT 24
Finished Jul 02 09:50:26 AM PDT 24
Peak memory 201412 kb
Host smart-3b221a02-e95b-4eb6-b7f2-a08e4201806a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128813404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4128813404
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1798035906
Short name T152
Test name
Test status
Simulation time 2242941280 ps
CPU time 5.55 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:22 AM PDT 24
Peak memory 201652 kb
Host smart-7c1130ca-c63c-44a2-9e46-367cfae33a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798035906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1798035906
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3311885449
Short name T832
Test name
Test status
Simulation time 4450053622 ps
CPU time 4.19 seconds
Started Jul 02 09:50:06 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201860 kb
Host smart-a5596d2c-2b00-4d03-827e-58fa55f0910a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311885449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3311885449
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.813529509
Short name T90
Test name
Test status
Simulation time 631052896 ps
CPU time 0.93 seconds
Started Jul 02 09:50:07 AM PDT 24
Finished Jul 02 09:50:16 AM PDT 24
Peak memory 201576 kb
Host smart-0c30bb8c-2daa-4214-869d-bf508b57f2ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813529509 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.813529509
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1894780863
Short name T883
Test name
Test status
Simulation time 509426380 ps
CPU time 1.38 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:50:32 AM PDT 24
Peak memory 201480 kb
Host smart-ecca65c8-0604-449c-9b0a-05c77f1b23da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894780863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1894780863
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.23720214
Short name T820
Test name
Test status
Simulation time 488936227 ps
CPU time 1.73 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201436 kb
Host smart-00945b4c-9e83-4145-81e0-78a7b63d3f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23720214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.23720214
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3514619127
Short name T871
Test name
Test status
Simulation time 4752618056 ps
CPU time 5.88 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 201724 kb
Host smart-dd7ddb77-c76d-4043-a1b0-5817492be7ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514619127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3514619127
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4257808123
Short name T88
Test name
Test status
Simulation time 495267054 ps
CPU time 1.58 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:23 AM PDT 24
Peak memory 201776 kb
Host smart-e0c70549-e47b-4dbb-91c8-b0a3d392dae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257808123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4257808123
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1095955951
Short name T907
Test name
Test status
Simulation time 8556342065 ps
CPU time 4.86 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201848 kb
Host smart-e25cbbfd-5888-4eec-9ddf-9034cd796ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095955951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1095955951
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1286122192
Short name T844
Test name
Test status
Simulation time 532375402 ps
CPU time 1.87 seconds
Started Jul 02 09:49:54 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 201568 kb
Host smart-984cda13-a683-43b9-ab16-c68d762a8c5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286122192 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1286122192
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.584429915
Short name T919
Test name
Test status
Simulation time 376222266 ps
CPU time 1.63 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 201532 kb
Host smart-5129ca89-e062-407f-a76c-3ff01b3e8718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584429915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.584429915
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3419659368
Short name T842
Test name
Test status
Simulation time 430638852 ps
CPU time 1.61 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201432 kb
Host smart-2c14ad00-955c-48d3-b484-6578151de6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419659368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3419659368
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3453331851
Short name T150
Test name
Test status
Simulation time 4135867613 ps
CPU time 16.06 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 201864 kb
Host smart-0d7de0cd-9acf-4618-b374-d2928ef903c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453331851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3453331851
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2091499029
Short name T879
Test name
Test status
Simulation time 890644199 ps
CPU time 2.11 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 201764 kb
Host smart-73d6a1cd-a239-4c11-8162-f03f06a7439e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091499029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2091499029
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1812774826
Short name T817
Test name
Test status
Simulation time 569018167 ps
CPU time 1.67 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201564 kb
Host smart-02b5407f-8855-43f1-a07e-6d0b01358539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812774826 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1812774826
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.428495528
Short name T895
Test name
Test status
Simulation time 563794711 ps
CPU time 1.02 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 201508 kb
Host smart-052d513c-dd20-4787-9914-5648fb17d1ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428495528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.428495528
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1895314045
Short name T827
Test name
Test status
Simulation time 511307342 ps
CPU time 0.86 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:18 AM PDT 24
Peak memory 201412 kb
Host smart-f155a932-76a6-4473-9f0b-029082c4834c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895314045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1895314045
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3103864950
Short name T148
Test name
Test status
Simulation time 2881220505 ps
CPU time 3.7 seconds
Started Jul 02 09:50:06 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 201652 kb
Host smart-2d5683d7-47fa-48b7-91db-e0f8031debe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103864950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3103864950
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1997392210
Short name T837
Test name
Test status
Simulation time 459977894 ps
CPU time 2.13 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:26 AM PDT 24
Peak memory 201772 kb
Host smart-ceec6f40-1c35-497c-964a-214f90d1915c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997392210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1997392210
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1162128370
Short name T357
Test name
Test status
Simulation time 8793775392 ps
CPU time 21.53 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:40 AM PDT 24
Peak memory 201820 kb
Host smart-fac1ebc9-b7c9-46e0-9f1e-e5319b63f1af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162128370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1162128370
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2988925043
Short name T696
Test name
Test status
Simulation time 341767656 ps
CPU time 1.43 seconds
Started Jul 02 09:30:56 AM PDT 24
Finished Jul 02 09:30:58 AM PDT 24
Peak memory 201596 kb
Host smart-88cc1e10-9c41-48b6-9ea5-ca77c49b067e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988925043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2988925043
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.788558173
Short name T356
Test name
Test status
Simulation time 376862597652 ps
CPU time 811.07 seconds
Started Jul 02 09:30:47 AM PDT 24
Finished Jul 02 09:44:19 AM PDT 24
Peak memory 201944 kb
Host smart-761798bd-73ef-4ba3-93b6-9714a41225b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788558173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.788558173
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2012427163
Short name T159
Test name
Test status
Simulation time 172561668519 ps
CPU time 192.29 seconds
Started Jul 02 09:30:47 AM PDT 24
Finished Jul 02 09:34:00 AM PDT 24
Peak memory 201900 kb
Host smart-4ee2b897-7f6e-48eb-a251-f8a4b747201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012427163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2012427163
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3472469326
Short name T336
Test name
Test status
Simulation time 492148268840 ps
CPU time 1167.64 seconds
Started Jul 02 09:30:43 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 201884 kb
Host smart-23a73bc6-512a-451d-80de-fab077d5701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472469326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3472469326
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1130677819
Short name T775
Test name
Test status
Simulation time 168261147591 ps
CPU time 25.52 seconds
Started Jul 02 09:30:42 AM PDT 24
Finished Jul 02 09:31:08 AM PDT 24
Peak memory 201904 kb
Host smart-65ec6ddd-d26b-45c7-b4ef-c4ed36e63730
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130677819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1130677819
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1000610765
Short name T411
Test name
Test status
Simulation time 171782345099 ps
CPU time 98.54 seconds
Started Jul 02 09:30:47 AM PDT 24
Finished Jul 02 09:32:26 AM PDT 24
Peak memory 201988 kb
Host smart-859b6d0a-72cd-4522-8e7b-2a38b6c1bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000610765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1000610765
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.760754910
Short name T556
Test name
Test status
Simulation time 333344221598 ps
CPU time 166.53 seconds
Started Jul 02 09:30:44 AM PDT 24
Finished Jul 02 09:33:30 AM PDT 24
Peak memory 201896 kb
Host smart-1e278d82-35f9-4bd7-b233-de0ac2987905
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=760754910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.760754910
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.532521529
Short name T170
Test name
Test status
Simulation time 364767197743 ps
CPU time 128.28 seconds
Started Jul 02 09:30:47 AM PDT 24
Finished Jul 02 09:32:55 AM PDT 24
Peak memory 201880 kb
Host smart-a2c7f0bd-2572-4b0c-aabe-a302acd53e14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532521529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.532521529
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.50327981
Short name T451
Test name
Test status
Simulation time 412151614958 ps
CPU time 876.9 seconds
Started Jul 02 09:30:47 AM PDT 24
Finished Jul 02 09:45:24 AM PDT 24
Peak memory 201788 kb
Host smart-03a304a1-ecc0-475e-beca-f1aaab53bb0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50327981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.50327981
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1099735023
Short name T110
Test name
Test status
Simulation time 38085443161 ps
CPU time 83.32 seconds
Started Jul 02 09:30:52 AM PDT 24
Finished Jul 02 09:32:16 AM PDT 24
Peak memory 201708 kb
Host smart-b400c1ad-3011-40a8-8c0a-ad8e58b7215c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099735023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1099735023
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2266668044
Short name T668
Test name
Test status
Simulation time 3255014902 ps
CPU time 2.18 seconds
Started Jul 02 09:30:51 AM PDT 24
Finished Jul 02 09:30:54 AM PDT 24
Peak memory 201748 kb
Host smart-92aa4962-ff92-430e-a7aa-54cfc2fbb61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266668044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2266668044
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3472110916
Short name T374
Test name
Test status
Simulation time 5575775767 ps
CPU time 13.38 seconds
Started Jul 02 09:30:47 AM PDT 24
Finished Jul 02 09:31:01 AM PDT 24
Peak memory 201716 kb
Host smart-39b3ba2e-ec3a-48d5-b30d-a827a3874402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472110916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3472110916
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1495371032
Short name T515
Test name
Test status
Simulation time 330813907709 ps
CPU time 205.21 seconds
Started Jul 02 09:30:55 AM PDT 24
Finished Jul 02 09:34:20 AM PDT 24
Peak memory 201928 kb
Host smart-5fd04693-601e-42db-9773-7dc27b29120f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495371032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1495371032
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3979936341
Short name T545
Test name
Test status
Simulation time 217186636235 ps
CPU time 396.41 seconds
Started Jul 02 09:30:52 AM PDT 24
Finished Jul 02 09:37:28 AM PDT 24
Peak memory 210548 kb
Host smart-a00a69ad-29b3-4bdb-815c-29618bddfa4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979936341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3979936341
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.875473311
Short name T649
Test name
Test status
Simulation time 401818820 ps
CPU time 1.1 seconds
Started Jul 02 09:31:07 AM PDT 24
Finished Jul 02 09:31:08 AM PDT 24
Peak memory 201668 kb
Host smart-cfa8145a-37dc-429f-9bed-48c938829d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875473311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.875473311
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1343983428
Short name T747
Test name
Test status
Simulation time 379911725291 ps
CPU time 210.03 seconds
Started Jul 02 09:31:04 AM PDT 24
Finished Jul 02 09:34:35 AM PDT 24
Peak memory 201908 kb
Host smart-b8d354ec-2a87-45d5-aca8-235b0593bc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343983428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1343983428
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.209791498
Short name T579
Test name
Test status
Simulation time 158678120155 ps
CPU time 346.57 seconds
Started Jul 02 09:30:59 AM PDT 24
Finished Jul 02 09:36:46 AM PDT 24
Peak memory 201916 kb
Host smart-2e6e3b10-0ebe-43d4-b626-134c047277e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209791498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.209791498
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3321962998
Short name T2
Test name
Test status
Simulation time 165201942164 ps
CPU time 185.54 seconds
Started Jul 02 09:30:59 AM PDT 24
Finished Jul 02 09:34:05 AM PDT 24
Peak memory 201900 kb
Host smart-376da78c-110e-4ba3-8065-7fd35746451d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321962998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3321962998
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.933702123
Short name T350
Test name
Test status
Simulation time 330966413745 ps
CPU time 182.66 seconds
Started Jul 02 09:30:53 AM PDT 24
Finished Jul 02 09:33:56 AM PDT 24
Peak memory 201972 kb
Host smart-d2231e25-a85d-414d-8e7e-66fa48ab3ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933702123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.933702123
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2016127537
Short name T58
Test name
Test status
Simulation time 324390549478 ps
CPU time 748.22 seconds
Started Jul 02 09:30:58 AM PDT 24
Finished Jul 02 09:43:26 AM PDT 24
Peak memory 201896 kb
Host smart-188a17e9-f49e-4b41-b6a4-e6b371006163
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016127537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2016127537
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1131793936
Short name T56
Test name
Test status
Simulation time 184048286926 ps
CPU time 84.99 seconds
Started Jul 02 09:31:01 AM PDT 24
Finished Jul 02 09:32:27 AM PDT 24
Peak memory 201996 kb
Host smart-1084d95d-cc70-42b0-921f-9186695ad303
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131793936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1131793936
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2813554162
Short name T691
Test name
Test status
Simulation time 394562409856 ps
CPU time 927.39 seconds
Started Jul 02 09:30:58 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 201868 kb
Host smart-42e228a6-0cd4-44ec-bd29-851ef6e97392
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813554162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2813554162
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3409738154
Short name T446
Test name
Test status
Simulation time 124143805811 ps
CPU time 440.27 seconds
Started Jul 02 09:31:04 AM PDT 24
Finished Jul 02 09:38:25 AM PDT 24
Peak memory 202184 kb
Host smart-da030c58-ce09-4f38-b586-3c6705afe767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409738154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3409738154
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4119532921
Short name T479
Test name
Test status
Simulation time 32105535073 ps
CPU time 18.35 seconds
Started Jul 02 09:31:03 AM PDT 24
Finished Jul 02 09:31:22 AM PDT 24
Peak memory 201648 kb
Host smart-19fe49ed-a81d-46fc-ad0c-6f960b87f0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119532921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4119532921
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3762300862
Short name T752
Test name
Test status
Simulation time 3742402457 ps
CPU time 2.81 seconds
Started Jul 02 09:31:04 AM PDT 24
Finished Jul 02 09:31:07 AM PDT 24
Peak memory 201696 kb
Host smart-43cf0447-96d1-4a78-8551-58466f3b3cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762300862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3762300862
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1612241356
Short name T81
Test name
Test status
Simulation time 4179125342 ps
CPU time 10.85 seconds
Started Jul 02 09:31:06 AM PDT 24
Finished Jul 02 09:31:17 AM PDT 24
Peak memory 217072 kb
Host smart-41b3ff80-726d-47c9-81a3-3bed2dd364d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612241356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1612241356
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2206849733
Short name T635
Test name
Test status
Simulation time 5716292947 ps
CPU time 3.37 seconds
Started Jul 02 09:30:55 AM PDT 24
Finished Jul 02 09:30:59 AM PDT 24
Peak memory 201720 kb
Host smart-fcd17cbe-fe16-4820-8475-b372a2c15679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206849733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2206849733
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4266189347
Short name T280
Test name
Test status
Simulation time 18295294040 ps
CPU time 32.47 seconds
Started Jul 02 09:31:03 AM PDT 24
Finished Jul 02 09:31:36 AM PDT 24
Peak memory 202076 kb
Host smart-ba969616-3a70-4748-b8ee-22fdbcac9dce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266189347 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.4266189347
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2804711693
Short name T468
Test name
Test status
Simulation time 306454753 ps
CPU time 1.29 seconds
Started Jul 02 09:32:09 AM PDT 24
Finished Jul 02 09:32:10 AM PDT 24
Peak memory 201676 kb
Host smart-91cc4a8c-bfa2-4796-a40f-0144cbd94b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804711693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2804711693
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2246793556
Short name T624
Test name
Test status
Simulation time 209662193574 ps
CPU time 242.05 seconds
Started Jul 02 09:32:05 AM PDT 24
Finished Jul 02 09:36:07 AM PDT 24
Peak memory 202120 kb
Host smart-27d0f40a-fa10-423a-940f-f6f9964e9d8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246793556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2246793556
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3243700473
Short name T723
Test name
Test status
Simulation time 201433935074 ps
CPU time 426.76 seconds
Started Jul 02 09:32:09 AM PDT 24
Finished Jul 02 09:39:16 AM PDT 24
Peak memory 201988 kb
Host smart-3a7bcb22-41a6-46fd-8557-e571b59f9619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243700473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3243700473
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1321457974
Short name T606
Test name
Test status
Simulation time 162987588466 ps
CPU time 185.66 seconds
Started Jul 02 09:32:04 AM PDT 24
Finished Jul 02 09:35:10 AM PDT 24
Peak memory 201884 kb
Host smart-d4203c8d-6dc4-429a-b248-a797c4b8008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321457974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1321457974
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4237238113
Short name T742
Test name
Test status
Simulation time 500828568198 ps
CPU time 1208.28 seconds
Started Jul 02 09:32:04 AM PDT 24
Finished Jul 02 09:52:12 AM PDT 24
Peak memory 201872 kb
Host smart-51ffd345-2ede-4896-b7fa-9ef91241d504
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237238113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4237238113
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.245760628
Short name T733
Test name
Test status
Simulation time 329230388907 ps
CPU time 420.24 seconds
Started Jul 02 09:32:06 AM PDT 24
Finished Jul 02 09:39:06 AM PDT 24
Peak memory 201988 kb
Host smart-0cdee471-c863-4227-a0a9-a2b82996cbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245760628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.245760628
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1192663458
Short name T397
Test name
Test status
Simulation time 332166167607 ps
CPU time 824.91 seconds
Started Jul 02 09:32:04 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 201948 kb
Host smart-5d9133c6-2200-42e9-934b-6291645f1ff0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192663458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1192663458
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.4115170036
Short name T271
Test name
Test status
Simulation time 191897884914 ps
CPU time 432.5 seconds
Started Jul 02 09:32:05 AM PDT 24
Finished Jul 02 09:39:17 AM PDT 24
Peak memory 201868 kb
Host smart-b6a303fc-d69a-4fbe-b356-9daefcb3fef8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115170036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.4115170036
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.956211455
Short name T522
Test name
Test status
Simulation time 98270667690 ps
CPU time 560.3 seconds
Started Jul 02 09:32:09 AM PDT 24
Finished Jul 02 09:41:29 AM PDT 24
Peak memory 202284 kb
Host smart-e5474be0-bda4-4fbe-ac9a-427b31ea5e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956211455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.956211455
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1062779410
Short name T395
Test name
Test status
Simulation time 36738854179 ps
CPU time 23.43 seconds
Started Jul 02 09:32:10 AM PDT 24
Finished Jul 02 09:32:33 AM PDT 24
Peak memory 201732 kb
Host smart-74764b36-07d2-46df-82bc-060187fd9262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062779410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1062779410
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.359709565
Short name T746
Test name
Test status
Simulation time 2993555395 ps
CPU time 2.31 seconds
Started Jul 02 09:32:10 AM PDT 24
Finished Jul 02 09:32:13 AM PDT 24
Peak memory 201740 kb
Host smart-5803d8c2-1c1d-424c-b9f3-094e9ef2e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359709565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.359709565
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.624811249
Short name T724
Test name
Test status
Simulation time 5625882800 ps
CPU time 12.48 seconds
Started Jul 02 09:32:00 AM PDT 24
Finished Jul 02 09:32:13 AM PDT 24
Peak memory 201648 kb
Host smart-f84a1ecd-65f8-461f-a589-11de08afc0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624811249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.624811249
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2004003737
Short name T562
Test name
Test status
Simulation time 326888954 ps
CPU time 1.36 seconds
Started Jul 02 09:32:11 AM PDT 24
Finished Jul 02 09:32:13 AM PDT 24
Peak memory 201668 kb
Host smart-448bdf59-6e68-4fae-a40c-4284445204f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004003737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2004003737
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.492047205
Short name T330
Test name
Test status
Simulation time 395355147948 ps
CPU time 178.52 seconds
Started Jul 02 09:32:12 AM PDT 24
Finished Jul 02 09:35:11 AM PDT 24
Peak memory 201908 kb
Host smart-c076fabd-f255-4612-9474-dbc0915a872d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492047205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.492047205
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2596451232
Short name T179
Test name
Test status
Simulation time 359966237182 ps
CPU time 208.93 seconds
Started Jul 02 09:32:15 AM PDT 24
Finished Jul 02 09:35:45 AM PDT 24
Peak memory 201920 kb
Host smart-cf26a500-30c9-4315-9a72-fe01d4ef2be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596451232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2596451232
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3272470990
Short name T503
Test name
Test status
Simulation time 166031793973 ps
CPU time 192.88 seconds
Started Jul 02 09:32:13 AM PDT 24
Finished Jul 02 09:35:26 AM PDT 24
Peak memory 201840 kb
Host smart-2cec4639-c1ff-484d-89dd-d0434a6f5b39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272470990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3272470990
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.808733944
Short name T750
Test name
Test status
Simulation time 328209953781 ps
CPU time 365.62 seconds
Started Jul 02 09:32:08 AM PDT 24
Finished Jul 02 09:38:14 AM PDT 24
Peak memory 201936 kb
Host smart-0e7fb627-ee35-4e01-a76f-321422627807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808733944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.808733944
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2498722969
Short name T398
Test name
Test status
Simulation time 484237309837 ps
CPU time 542.15 seconds
Started Jul 02 09:32:10 AM PDT 24
Finished Jul 02 09:41:12 AM PDT 24
Peak memory 201892 kb
Host smart-cb0554c9-754e-4cc7-91b5-70d9211ca920
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498722969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2498722969
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2342874775
Short name T188
Test name
Test status
Simulation time 542887859143 ps
CPU time 324.64 seconds
Started Jul 02 09:32:12 AM PDT 24
Finished Jul 02 09:37:37 AM PDT 24
Peak memory 201976 kb
Host smart-48b800bb-5667-4748-a433-3d5bf1bfaede
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342874775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2342874775
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1987870266
Short name T789
Test name
Test status
Simulation time 607929833098 ps
CPU time 1281.47 seconds
Started Jul 02 09:32:11 AM PDT 24
Finished Jul 02 09:53:33 AM PDT 24
Peak memory 201860 kb
Host smart-d46d4bd7-ed9a-4ac4-ab48-47612d8f1425
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987870266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1987870266
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3853785649
Short name T196
Test name
Test status
Simulation time 25998284701 ps
CPU time 30.61 seconds
Started Jul 02 09:32:12 AM PDT 24
Finished Jul 02 09:32:43 AM PDT 24
Peak memory 201720 kb
Host smart-93838f16-05a1-4c09-880a-00beea783cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853785649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3853785649
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1512066053
Short name T450
Test name
Test status
Simulation time 3876810439 ps
CPU time 3.07 seconds
Started Jul 02 09:32:13 AM PDT 24
Finished Jul 02 09:32:17 AM PDT 24
Peak memory 201712 kb
Host smart-b1def372-c351-4e9f-a22a-ead6e9eea789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512066053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1512066053
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1947396340
Short name T438
Test name
Test status
Simulation time 6102645651 ps
CPU time 2.7 seconds
Started Jul 02 09:32:08 AM PDT 24
Finished Jul 02 09:32:11 AM PDT 24
Peak memory 201712 kb
Host smart-bafdfb43-c448-4502-8a2e-764d50d37d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947396340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1947396340
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2083481872
Short name T771
Test name
Test status
Simulation time 744580595108 ps
CPU time 295.53 seconds
Started Jul 02 09:32:12 AM PDT 24
Finished Jul 02 09:37:08 AM PDT 24
Peak memory 218036 kb
Host smart-cea6f987-b603-4efc-87a7-32e8a1da1c35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083481872 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2083481872
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3417424158
Short name T86
Test name
Test status
Simulation time 527009447 ps
CPU time 1.89 seconds
Started Jul 02 09:32:24 AM PDT 24
Finished Jul 02 09:32:26 AM PDT 24
Peak memory 201628 kb
Host smart-d201a7db-fb6a-4d60-b0c5-42af7160ecad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417424158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3417424158
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2877916310
Short name T304
Test name
Test status
Simulation time 181687339986 ps
CPU time 75.13 seconds
Started Jul 02 09:32:20 AM PDT 24
Finished Jul 02 09:33:35 AM PDT 24
Peak memory 201908 kb
Host smart-ddf5a637-add1-4fab-82b0-66d970feacb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877916310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2877916310
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2575699303
Short name T353
Test name
Test status
Simulation time 494840844880 ps
CPU time 1090.19 seconds
Started Jul 02 09:32:14 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 201916 kb
Host smart-7e577c19-014b-45e9-8950-7488aac93ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575699303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2575699303
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2185536953
Short name T403
Test name
Test status
Simulation time 157848278025 ps
CPU time 114.08 seconds
Started Jul 02 09:32:20 AM PDT 24
Finished Jul 02 09:34:14 AM PDT 24
Peak memory 201880 kb
Host smart-5b27ac30-28f4-4d80-9231-b76217488b17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185536953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2185536953
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1456137376
Short name T689
Test name
Test status
Simulation time 488154805736 ps
CPU time 1099.19 seconds
Started Jul 02 09:32:17 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 202004 kb
Host smart-2d120375-dcec-4fe7-95fd-ef0f8b4239ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456137376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1456137376
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3816208159
Short name T776
Test name
Test status
Simulation time 493362699854 ps
CPU time 281.79 seconds
Started Jul 02 09:32:16 AM PDT 24
Finished Jul 02 09:36:58 AM PDT 24
Peak memory 201868 kb
Host smart-896815a3-893c-40f7-af45-c1c21703aee2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816208159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3816208159
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3589721141
Short name T795
Test name
Test status
Simulation time 170535238906 ps
CPU time 387.36 seconds
Started Jul 02 09:32:18 AM PDT 24
Finished Jul 02 09:38:46 AM PDT 24
Peak memory 201964 kb
Host smart-6838bbe9-a49a-4c6c-adda-f50e84f20332
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589721141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3589721141
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2615842598
Short name T220
Test name
Test status
Simulation time 616883780572 ps
CPU time 1102.07 seconds
Started Jul 02 09:32:19 AM PDT 24
Finished Jul 02 09:50:42 AM PDT 24
Peak memory 201828 kb
Host smart-3e59fb6e-8bce-4868-8d17-68dd1b8c9177
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615842598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2615842598
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.711609754
Short name T63
Test name
Test status
Simulation time 118670096446 ps
CPU time 398.78 seconds
Started Jul 02 09:32:23 AM PDT 24
Finished Jul 02 09:39:02 AM PDT 24
Peak memory 202184 kb
Host smart-09e6ac40-0b3d-4a40-bf22-8fde0a82a28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711609754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.711609754
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3092265454
Short name T441
Test name
Test status
Simulation time 38272768049 ps
CPU time 5.56 seconds
Started Jul 02 09:32:22 AM PDT 24
Finished Jul 02 09:32:28 AM PDT 24
Peak memory 201696 kb
Host smart-93ea65fb-c0d0-4c97-9950-bbde84994197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092265454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3092265454
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3108060119
Short name T373
Test name
Test status
Simulation time 5034315075 ps
CPU time 13.38 seconds
Started Jul 02 09:32:18 AM PDT 24
Finished Jul 02 09:32:32 AM PDT 24
Peak memory 201728 kb
Host smart-77f028da-533d-4195-8c88-6a70e7f34e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108060119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3108060119
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1845632177
Short name T380
Test name
Test status
Simulation time 6172872693 ps
CPU time 2.04 seconds
Started Jul 02 09:32:13 AM PDT 24
Finished Jul 02 09:32:16 AM PDT 24
Peak memory 201668 kb
Host smart-d752bbcb-3402-4fc2-a1dc-4fb78082f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845632177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1845632177
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2130439151
Short name T681
Test name
Test status
Simulation time 489150488665 ps
CPU time 1108.08 seconds
Started Jul 02 09:32:25 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 201908 kb
Host smart-02fadaf0-2be0-46f4-846f-9c8bbc0b0fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130439151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2130439151
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.869910940
Short name T638
Test name
Test status
Simulation time 232012725014 ps
CPU time 152.45 seconds
Started Jul 02 09:32:25 AM PDT 24
Finished Jul 02 09:34:57 AM PDT 24
Peak memory 210308 kb
Host smart-48b8a957-fd59-45b1-9bae-c8d22a7e4423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869910940 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.869910940
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1426232216
Short name T735
Test name
Test status
Simulation time 495620930 ps
CPU time 1.73 seconds
Started Jul 02 09:32:28 AM PDT 24
Finished Jul 02 09:32:30 AM PDT 24
Peak memory 201664 kb
Host smart-5b5095eb-5b5e-4c1b-a962-1ef8767d6876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426232216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1426232216
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1458643035
Short name T64
Test name
Test status
Simulation time 484765496465 ps
CPU time 291.5 seconds
Started Jul 02 09:32:29 AM PDT 24
Finished Jul 02 09:37:21 AM PDT 24
Peak memory 201908 kb
Host smart-57d80593-bc14-4173-86e0-6649d0363b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458643035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1458643035
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3479777667
Short name T587
Test name
Test status
Simulation time 327841083192 ps
CPU time 739.38 seconds
Started Jul 02 09:32:27 AM PDT 24
Finished Jul 02 09:44:47 AM PDT 24
Peak memory 201872 kb
Host smart-edd78584-0ec6-43df-97c1-c1c1951015a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479777667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3479777667
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.951778818
Short name T666
Test name
Test status
Simulation time 160951209675 ps
CPU time 186.74 seconds
Started Jul 02 09:32:30 AM PDT 24
Finished Jul 02 09:35:37 AM PDT 24
Peak memory 201912 kb
Host smart-2fee0f7b-12ea-4c8e-ae7e-085ea08d0b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951778818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.951778818
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1226945435
Short name T796
Test name
Test status
Simulation time 329430572690 ps
CPU time 375.01 seconds
Started Jul 02 09:32:28 AM PDT 24
Finished Jul 02 09:38:43 AM PDT 24
Peak memory 201900 kb
Host smart-e2e349fd-9d69-4c0d-8940-d0a90333caa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226945435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1226945435
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3117213739
Short name T802
Test name
Test status
Simulation time 513321102910 ps
CPU time 585.24 seconds
Started Jul 02 09:32:29 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 201352 kb
Host smart-a8eed7de-111c-4a69-bf8d-87bdebe0261c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117213739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3117213739
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.219708406
Short name T457
Test name
Test status
Simulation time 380940064956 ps
CPU time 791.32 seconds
Started Jul 02 09:32:28 AM PDT 24
Finished Jul 02 09:45:40 AM PDT 24
Peak memory 201864 kb
Host smart-7a73b62f-f63e-467d-87dc-4d2cc49a1d5b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219708406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.219708406
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1498753712
Short name T448
Test name
Test status
Simulation time 72473231346 ps
CPU time 365.31 seconds
Started Jul 02 09:32:28 AM PDT 24
Finished Jul 02 09:38:34 AM PDT 24
Peak memory 202272 kb
Host smart-58237738-c009-4ae5-b460-65315e5f1181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498753712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1498753712
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2403449605
Short name T566
Test name
Test status
Simulation time 28701312404 ps
CPU time 31.71 seconds
Started Jul 02 09:32:29 AM PDT 24
Finished Jul 02 09:33:01 AM PDT 24
Peak memory 201184 kb
Host smart-b3e0cd51-1e51-4284-85a1-c694ea3ed019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403449605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2403449605
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3563061632
Short name T432
Test name
Test status
Simulation time 4484159017 ps
CPU time 2.75 seconds
Started Jul 02 09:32:30 AM PDT 24
Finished Jul 02 09:32:33 AM PDT 24
Peak memory 201712 kb
Host smart-68e46dbe-3053-419a-98b2-24f1bff92bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563061632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3563061632
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1012442815
Short name T514
Test name
Test status
Simulation time 6111834791 ps
CPU time 4.25 seconds
Started Jul 02 09:32:25 AM PDT 24
Finished Jul 02 09:32:30 AM PDT 24
Peak memory 201712 kb
Host smart-df553f4f-64d8-4394-bc82-78a281dda4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012442815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1012442815
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1136316972
Short name T178
Test name
Test status
Simulation time 686626499660 ps
CPU time 1465.88 seconds
Started Jul 02 09:32:31 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 201892 kb
Host smart-224055cb-e65c-4597-9198-65c89e837eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136316972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1136316972
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3358309731
Short name T785
Test name
Test status
Simulation time 41716166038 ps
CPU time 47.95 seconds
Started Jul 02 09:32:29 AM PDT 24
Finished Jul 02 09:33:17 AM PDT 24
Peak memory 210240 kb
Host smart-c521ea34-f6c8-417b-bde9-b00ac6e76753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358309731 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3358309731
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2559342232
Short name T435
Test name
Test status
Simulation time 481205892 ps
CPU time 1.59 seconds
Started Jul 02 09:32:38 AM PDT 24
Finished Jul 02 09:32:40 AM PDT 24
Peak memory 201684 kb
Host smart-83bc7f49-0fec-42bc-8468-9d547e41986e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559342232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2559342232
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2348609620
Short name T758
Test name
Test status
Simulation time 173874818993 ps
CPU time 183.87 seconds
Started Jul 02 09:32:35 AM PDT 24
Finished Jul 02 09:35:39 AM PDT 24
Peak memory 201872 kb
Host smart-8887ebbb-732e-4dcb-ae78-b6693b25c600
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348609620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2348609620
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.741661552
Short name T493
Test name
Test status
Simulation time 167992290252 ps
CPU time 30.52 seconds
Started Jul 02 09:32:35 AM PDT 24
Finished Jul 02 09:33:06 AM PDT 24
Peak memory 201928 kb
Host smart-878cde9d-91d8-48bc-a11e-16a7fc67eaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741661552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.741661552
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3386687363
Short name T794
Test name
Test status
Simulation time 163827234896 ps
CPU time 339.92 seconds
Started Jul 02 09:32:32 AM PDT 24
Finished Jul 02 09:38:13 AM PDT 24
Peak memory 201884 kb
Host smart-c9636f42-95ec-4f31-9e93-f4124089e89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386687363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3386687363
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.807921027
Short name T571
Test name
Test status
Simulation time 325959230939 ps
CPU time 364.93 seconds
Started Jul 02 09:32:30 AM PDT 24
Finished Jul 02 09:38:36 AM PDT 24
Peak memory 201884 kb
Host smart-bc43e59a-d90b-4272-b032-90068e46348d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=807921027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.807921027
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1520705535
Short name T347
Test name
Test status
Simulation time 162777969809 ps
CPU time 344.27 seconds
Started Jul 02 09:32:30 AM PDT 24
Finished Jul 02 09:38:15 AM PDT 24
Peak memory 201980 kb
Host smart-500db297-4b74-4b4c-b5ee-4ddaed751e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520705535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1520705535
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.541043034
Short name T447
Test name
Test status
Simulation time 493377230890 ps
CPU time 232.94 seconds
Started Jul 02 09:32:31 AM PDT 24
Finished Jul 02 09:36:25 AM PDT 24
Peak memory 201872 kb
Host smart-c8d15e97-c667-49a7-8ba0-0cc986a1868b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=541043034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.541043034
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1745391288
Short name T324
Test name
Test status
Simulation time 568014744956 ps
CPU time 1227.61 seconds
Started Jul 02 09:32:35 AM PDT 24
Finished Jul 02 09:53:03 AM PDT 24
Peak memory 201972 kb
Host smart-ea361c3d-6bca-4d6e-99f2-9b33a79dcb4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745391288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1745391288
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1533831069
Short name T501
Test name
Test status
Simulation time 396558389351 ps
CPU time 883.76 seconds
Started Jul 02 09:32:33 AM PDT 24
Finished Jul 02 09:47:17 AM PDT 24
Peak memory 201924 kb
Host smart-f17cafbf-0132-4498-b64a-fa44d3620fd0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533831069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1533831069
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1323358051
Short name T361
Test name
Test status
Simulation time 66336433805 ps
CPU time 384.73 seconds
Started Jul 02 09:32:39 AM PDT 24
Finished Jul 02 09:39:04 AM PDT 24
Peak memory 202464 kb
Host smart-79af0428-3f05-4f70-8d3c-01fb2f8136da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323358051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1323358051
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1927546291
Short name T762
Test name
Test status
Simulation time 27917676146 ps
CPU time 27.85 seconds
Started Jul 02 09:32:39 AM PDT 24
Finished Jul 02 09:33:08 AM PDT 24
Peak memory 201712 kb
Host smart-aa5315de-6bb8-477b-927e-ab6c41072a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927546291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1927546291
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2841049189
Short name T454
Test name
Test status
Simulation time 4084771381 ps
CPU time 5.05 seconds
Started Jul 02 09:32:39 AM PDT 24
Finished Jul 02 09:32:45 AM PDT 24
Peak memory 201636 kb
Host smart-5aee537e-2782-4d99-b9bf-27d01da8aed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841049189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2841049189
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4151663167
Short name T449
Test name
Test status
Simulation time 5743124507 ps
CPU time 1.56 seconds
Started Jul 02 09:32:31 AM PDT 24
Finished Jul 02 09:32:33 AM PDT 24
Peak memory 201700 kb
Host smart-a34b967d-45ac-43da-9ee4-8fdcdf4cb313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151663167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4151663167
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.972673203
Short name T745
Test name
Test status
Simulation time 375195147298 ps
CPU time 148.92 seconds
Started Jul 02 09:32:39 AM PDT 24
Finished Jul 02 09:35:08 AM PDT 24
Peak memory 201904 kb
Host smart-463f8406-4ccb-4e66-a91e-7035bec496ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972673203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
972673203
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2282537114
Short name T662
Test name
Test status
Simulation time 185139039149 ps
CPU time 104.35 seconds
Started Jul 02 09:32:39 AM PDT 24
Finished Jul 02 09:34:24 AM PDT 24
Peak memory 210244 kb
Host smart-b97f56f8-363a-46e0-932d-7e23ec82ec53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282537114 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2282537114
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3192582266
Short name T597
Test name
Test status
Simulation time 515721119 ps
CPU time 1.69 seconds
Started Jul 02 09:32:47 AM PDT 24
Finished Jul 02 09:32:49 AM PDT 24
Peak memory 201676 kb
Host smart-22f9cce9-818e-4689-bc04-1e789afb2efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192582266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3192582266
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1910537189
Short name T268
Test name
Test status
Simulation time 522820370366 ps
CPU time 527.68 seconds
Started Jul 02 09:32:43 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 201908 kb
Host smart-543117b1-8adf-48a1-9a92-dbba38b6892f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910537189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1910537189
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4215196649
Short name T778
Test name
Test status
Simulation time 508668973232 ps
CPU time 1105.54 seconds
Started Jul 02 09:32:44 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 201844 kb
Host smart-2bb6d78e-8d8a-493a-823c-ce9312052aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215196649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4215196649
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3976226413
Short name T766
Test name
Test status
Simulation time 493426634050 ps
CPU time 270.39 seconds
Started Jul 02 09:32:42 AM PDT 24
Finished Jul 02 09:37:13 AM PDT 24
Peak memory 201876 kb
Host smart-d1cfaf49-e02e-4aef-a822-21b1432cf7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976226413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3976226413
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1532746321
Short name T530
Test name
Test status
Simulation time 481314203504 ps
CPU time 220.84 seconds
Started Jul 02 09:32:41 AM PDT 24
Finished Jul 02 09:36:23 AM PDT 24
Peak memory 201872 kb
Host smart-c3d383d1-0128-45ca-bbb2-2c3ed895a98c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532746321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1532746321
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3077166378
Short name T317
Test name
Test status
Simulation time 319897303154 ps
CPU time 350.74 seconds
Started Jul 02 09:32:41 AM PDT 24
Finished Jul 02 09:38:32 AM PDT 24
Peak memory 201924 kb
Host smart-54711213-bab3-48ed-ad23-30b90f935d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077166378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3077166378
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.747588229
Short name T458
Test name
Test status
Simulation time 167823241861 ps
CPU time 363.49 seconds
Started Jul 02 09:32:43 AM PDT 24
Finished Jul 02 09:38:47 AM PDT 24
Peak memory 201892 kb
Host smart-8281d9b1-77ed-4111-b110-746d3a724aa3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=747588229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.747588229
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3500997863
Short name T248
Test name
Test status
Simulation time 175759758064 ps
CPU time 369.42 seconds
Started Jul 02 09:32:45 AM PDT 24
Finished Jul 02 09:38:54 AM PDT 24
Peak memory 201924 kb
Host smart-d1e3580f-c63c-4c16-b945-290873f4f4d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500997863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3500997863
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.107489215
Short name T444
Test name
Test status
Simulation time 599802315106 ps
CPU time 1310.48 seconds
Started Jul 02 09:32:42 AM PDT 24
Finished Jul 02 09:54:33 AM PDT 24
Peak memory 201856 kb
Host smart-76d7695f-939a-4462-b972-1d008975f8d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107489215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.107489215
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2591671251
Short name T633
Test name
Test status
Simulation time 100496622162 ps
CPU time 467.47 seconds
Started Jul 02 09:32:46 AM PDT 24
Finished Jul 02 09:40:34 AM PDT 24
Peak memory 202160 kb
Host smart-66c1a120-1cb1-4fb2-a853-8b72a7518fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591671251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2591671251
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3257253209
Short name T10
Test name
Test status
Simulation time 21879051734 ps
CPU time 24.16 seconds
Started Jul 02 09:32:42 AM PDT 24
Finished Jul 02 09:33:07 AM PDT 24
Peak memory 201716 kb
Host smart-fd5fe057-720d-4256-a5b3-e7d4204f9c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257253209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3257253209
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2441736548
Short name T28
Test name
Test status
Simulation time 3465781682 ps
CPU time 7.63 seconds
Started Jul 02 09:32:43 AM PDT 24
Finished Jul 02 09:32:51 AM PDT 24
Peak memory 201728 kb
Host smart-29d29435-72d5-40f1-9efc-9128f37b23f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441736548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2441736548
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3386175149
Short name T42
Test name
Test status
Simulation time 6038385118 ps
CPU time 12.69 seconds
Started Jul 02 09:32:43 AM PDT 24
Finished Jul 02 09:32:56 AM PDT 24
Peak memory 201636 kb
Host smart-7b478b8d-4edc-4c9c-8c2e-bb98d295344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386175149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3386175149
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3566599154
Short name T639
Test name
Test status
Simulation time 407102971155 ps
CPU time 883.21 seconds
Started Jul 02 09:32:45 AM PDT 24
Finished Jul 02 09:47:29 AM PDT 24
Peak memory 201904 kb
Host smart-89803613-c1f2-4b4e-90d4-21bfa6a19c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566599154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3566599154
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3256699372
Short name T684
Test name
Test status
Simulation time 97790703263 ps
CPU time 53.02 seconds
Started Jul 02 09:32:46 AM PDT 24
Finished Jul 02 09:33:39 AM PDT 24
Peak memory 210248 kb
Host smart-b59f3e24-ee14-4d7e-a217-02903299660a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256699372 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3256699372
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1820476723
Short name T502
Test name
Test status
Simulation time 410937519 ps
CPU time 0.73 seconds
Started Jul 02 09:32:56 AM PDT 24
Finished Jul 02 09:32:57 AM PDT 24
Peak memory 201652 kb
Host smart-bf444971-b29d-4443-baf3-62f6b7503b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820476723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1820476723
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2152042648
Short name T278
Test name
Test status
Simulation time 551184925872 ps
CPU time 460.62 seconds
Started Jul 02 09:32:51 AM PDT 24
Finished Jul 02 09:40:32 AM PDT 24
Peak memory 201916 kb
Host smart-05763c81-569a-4cf6-9729-24744406b8d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152042648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2152042648
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3666650266
Short name T744
Test name
Test status
Simulation time 167126374759 ps
CPU time 106.11 seconds
Started Jul 02 09:32:55 AM PDT 24
Finished Jul 02 09:34:41 AM PDT 24
Peak memory 201960 kb
Host smart-f169c142-94bf-46f2-937d-e837c36594b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666650266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3666650266
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.957333980
Short name T799
Test name
Test status
Simulation time 165843539686 ps
CPU time 67.1 seconds
Started Jul 02 09:32:50 AM PDT 24
Finished Jul 02 09:33:58 AM PDT 24
Peak memory 201904 kb
Host smart-354aa39f-a58e-4287-8d49-fa0c2c74ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957333980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.957333980
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2468112699
Short name T474
Test name
Test status
Simulation time 165855483831 ps
CPU time 363.81 seconds
Started Jul 02 09:32:51 AM PDT 24
Finished Jul 02 09:38:55 AM PDT 24
Peak memory 201884 kb
Host smart-29923d33-7530-4d25-a1cf-6a57c26099ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468112699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2468112699
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3559273705
Short name T195
Test name
Test status
Simulation time 328197113766 ps
CPU time 195.08 seconds
Started Jul 02 09:32:45 AM PDT 24
Finished Jul 02 09:36:00 AM PDT 24
Peak memory 201956 kb
Host smart-55bdf68a-3db1-4860-a07a-71ce065de901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559273705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3559273705
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3671835387
Short name T564
Test name
Test status
Simulation time 488728730833 ps
CPU time 570.66 seconds
Started Jul 02 09:32:45 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 201808 kb
Host smart-93aa5fcf-6e42-4714-bb9b-6aff1725eed7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671835387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3671835387
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1654957771
Short name T13
Test name
Test status
Simulation time 380680675945 ps
CPU time 206.59 seconds
Started Jul 02 09:32:51 AM PDT 24
Finished Jul 02 09:36:18 AM PDT 24
Peak memory 201884 kb
Host smart-4a7ad5f2-cc8c-405d-8607-1201ec065a99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654957771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1654957771
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.196425151
Short name T543
Test name
Test status
Simulation time 597300101430 ps
CPU time 1278.69 seconds
Started Jul 02 09:32:51 AM PDT 24
Finished Jul 02 09:54:10 AM PDT 24
Peak memory 201888 kb
Host smart-89bd7e73-6199-4fa2-8e99-3f4f6f8e1e1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196425151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.196425151
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1207231149
Short name T376
Test name
Test status
Simulation time 96014254418 ps
CPU time 330.13 seconds
Started Jul 02 09:32:54 AM PDT 24
Finished Jul 02 09:38:25 AM PDT 24
Peak memory 202244 kb
Host smart-564c1dc9-8fdf-49aa-8be5-a0f65b1f463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207231149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1207231149
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.349955858
Short name T30
Test name
Test status
Simulation time 29692025603 ps
CPU time 70.34 seconds
Started Jul 02 09:32:55 AM PDT 24
Finished Jul 02 09:34:05 AM PDT 24
Peak memory 201720 kb
Host smart-5571046b-2d0f-4a6c-a634-a608f45b4c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349955858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.349955858
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.98040932
Short name T612
Test name
Test status
Simulation time 4357041667 ps
CPU time 12.18 seconds
Started Jul 02 09:32:56 AM PDT 24
Finished Jul 02 09:33:08 AM PDT 24
Peak memory 201728 kb
Host smart-0a771913-3df5-44c7-b061-f8c9211ab137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98040932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.98040932
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2643209927
Short name T516
Test name
Test status
Simulation time 6075856578 ps
CPU time 13.16 seconds
Started Jul 02 09:32:45 AM PDT 24
Finished Jul 02 09:32:58 AM PDT 24
Peak memory 201716 kb
Host smart-b33d544b-bdc2-4881-a179-d24a5c649452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643209927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2643209927
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2688178877
Short name T19
Test name
Test status
Simulation time 110182143453 ps
CPU time 94.2 seconds
Started Jul 02 09:32:54 AM PDT 24
Finished Jul 02 09:34:29 AM PDT 24
Peak memory 210472 kb
Host smart-296569e3-d4af-4298-938e-ae79e6db4cbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688178877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2688178877
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3899651315
Short name T452
Test name
Test status
Simulation time 165707605525 ps
CPU time 98.12 seconds
Started Jul 02 09:33:02 AM PDT 24
Finished Jul 02 09:34:40 AM PDT 24
Peak memory 201876 kb
Host smart-f8439704-5571-4a2d-95d6-a8bfb3088f7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899651315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3899651315
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.955527434
Short name T605
Test name
Test status
Simulation time 358574086625 ps
CPU time 424.95 seconds
Started Jul 02 09:33:02 AM PDT 24
Finished Jul 02 09:40:08 AM PDT 24
Peak memory 201984 kb
Host smart-04920e70-b014-430e-804d-21edc5a65449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955527434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.955527434
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3489149754
Short name T425
Test name
Test status
Simulation time 495977338591 ps
CPU time 1056.53 seconds
Started Jul 02 09:32:58 AM PDT 24
Finished Jul 02 09:50:35 AM PDT 24
Peak memory 201892 kb
Host smart-f9824e78-d1a2-4eb2-95c4-def9c9bf30ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489149754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3489149754
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.4080263042
Short name T630
Test name
Test status
Simulation time 485802273913 ps
CPU time 881.98 seconds
Started Jul 02 09:32:59 AM PDT 24
Finished Jul 02 09:47:41 AM PDT 24
Peak memory 201884 kb
Host smart-91bf34a6-b596-46a3-bdb0-f33f263cddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080263042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.4080263042
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.283868573
Short name T383
Test name
Test status
Simulation time 163600949439 ps
CPU time 393.11 seconds
Started Jul 02 09:32:59 AM PDT 24
Finished Jul 02 09:39:33 AM PDT 24
Peak memory 201812 kb
Host smart-739cbb2b-31c5-4a7d-93b6-87233d9f3d11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=283868573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.283868573
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4005245304
Short name T554
Test name
Test status
Simulation time 198862010643 ps
CPU time 206.14 seconds
Started Jul 02 09:33:00 AM PDT 24
Finished Jul 02 09:36:26 AM PDT 24
Peak memory 201936 kb
Host smart-238092c3-9a4f-468b-b6c5-aed1755adbee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005245304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4005245304
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4092470001
Short name T710
Test name
Test status
Simulation time 200678662428 ps
CPU time 117.23 seconds
Started Jul 02 09:32:58 AM PDT 24
Finished Jul 02 09:34:55 AM PDT 24
Peak memory 201896 kb
Host smart-76b789d8-3de3-4b95-a715-7adb2dd3b47e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092470001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.4092470001
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2256395195
Short name T711
Test name
Test status
Simulation time 135158693138 ps
CPU time 661.11 seconds
Started Jul 02 09:33:01 AM PDT 24
Finished Jul 02 09:44:03 AM PDT 24
Peak memory 202252 kb
Host smart-c53f1dcd-4ad9-4a6b-9c65-0286bbebec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256395195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2256395195
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2518010963
Short name T113
Test name
Test status
Simulation time 31166962962 ps
CPU time 13.9 seconds
Started Jul 02 09:33:03 AM PDT 24
Finished Jul 02 09:33:17 AM PDT 24
Peak memory 201688 kb
Host smart-2c3dc21d-3105-4b00-8403-8c0342da5014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518010963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2518010963
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3815771556
Short name T400
Test name
Test status
Simulation time 4734447754 ps
CPU time 3.59 seconds
Started Jul 02 09:33:03 AM PDT 24
Finished Jul 02 09:33:07 AM PDT 24
Peak memory 201732 kb
Host smart-53248e55-9753-4034-9e2c-4405328c6c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815771556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3815771556
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.146421001
Short name T620
Test name
Test status
Simulation time 6092734591 ps
CPU time 7.31 seconds
Started Jul 02 09:32:54 AM PDT 24
Finished Jul 02 09:33:02 AM PDT 24
Peak memory 201648 kb
Host smart-80cb83e4-74c3-445e-ab46-6db3750d05fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146421001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.146421001
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.967870710
Short name T107
Test name
Test status
Simulation time 115484816150 ps
CPU time 262.59 seconds
Started Jul 02 09:33:07 AM PDT 24
Finished Jul 02 09:37:30 AM PDT 24
Peak memory 218064 kb
Host smart-3a120db7-64d7-430b-80d9-aa00f9b28e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967870710 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.967870710
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3924977954
Short name T4
Test name
Test status
Simulation time 533503131 ps
CPU time 0.9 seconds
Started Jul 02 09:33:11 AM PDT 24
Finished Jul 02 09:33:12 AM PDT 24
Peak memory 201680 kb
Host smart-636fc41e-0f2e-4603-bc6f-5e05bbabe1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924977954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3924977954
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2479205715
Short name T343
Test name
Test status
Simulation time 517872907957 ps
CPU time 1143.62 seconds
Started Jul 02 09:33:10 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 201912 kb
Host smart-4b417178-4223-4400-8b1e-0e0b60993160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479205715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2479205715
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.731769809
Short name T341
Test name
Test status
Simulation time 163314779950 ps
CPU time 364.92 seconds
Started Jul 02 09:33:06 AM PDT 24
Finished Jul 02 09:39:11 AM PDT 24
Peak memory 201916 kb
Host smart-5b77513d-051d-4d39-b89f-91926fafd7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731769809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.731769809
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1624340248
Short name T609
Test name
Test status
Simulation time 164943312140 ps
CPU time 351.55 seconds
Started Jul 02 09:33:09 AM PDT 24
Finished Jul 02 09:39:01 AM PDT 24
Peak memory 201888 kb
Host smart-f4c5dcde-92fc-4361-bb7c-32041f7b4e27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624340248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1624340248
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2474575636
Short name T568
Test name
Test status
Simulation time 328351480245 ps
CPU time 40.51 seconds
Started Jul 02 09:33:07 AM PDT 24
Finished Jul 02 09:33:48 AM PDT 24
Peak memory 201880 kb
Host smart-c918e3e3-a30d-4201-9709-0c979dec5f03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474575636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2474575636
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1237767905
Short name T3
Test name
Test status
Simulation time 355048658996 ps
CPU time 830.15 seconds
Started Jul 02 09:33:07 AM PDT 24
Finished Jul 02 09:46:57 AM PDT 24
Peak memory 201988 kb
Host smart-f825f94d-d594-48bc-8c70-08ae7686cd9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237767905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1237767905
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2790408083
Short name T172
Test name
Test status
Simulation time 197874480503 ps
CPU time 75.57 seconds
Started Jul 02 09:33:09 AM PDT 24
Finished Jul 02 09:34:25 AM PDT 24
Peak memory 201900 kb
Host smart-56b75d5e-82c4-4492-91eb-d9abd652916c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790408083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2790408083
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3572735086
Short name T578
Test name
Test status
Simulation time 74496973954 ps
CPU time 299.45 seconds
Started Jul 02 09:33:09 AM PDT 24
Finished Jul 02 09:38:09 AM PDT 24
Peak memory 202272 kb
Host smart-c1ceb84e-a1bd-4f4b-a330-e4d59f317ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572735086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3572735086
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1625676490
Short name T377
Test name
Test status
Simulation time 29912881329 ps
CPU time 16.42 seconds
Started Jul 02 09:33:10 AM PDT 24
Finished Jul 02 09:33:27 AM PDT 24
Peak memory 201728 kb
Host smart-d40f5d8f-759c-4698-b72c-4fa2ca876874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625676490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1625676490
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2725448135
Short name T548
Test name
Test status
Simulation time 5154750868 ps
CPU time 3.71 seconds
Started Jul 02 09:33:10 AM PDT 24
Finished Jul 02 09:33:14 AM PDT 24
Peak memory 201716 kb
Host smart-30d6d1a7-73f2-41c6-b6cf-45d927dd8aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725448135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2725448135
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1386338739
Short name T748
Test name
Test status
Simulation time 5943909280 ps
CPU time 3.96 seconds
Started Jul 02 09:33:06 AM PDT 24
Finished Jul 02 09:33:10 AM PDT 24
Peak memory 201692 kb
Host smart-869f3a2a-8e17-4d8e-994d-d97850fbf8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386338739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1386338739
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4113060570
Short name T291
Test name
Test status
Simulation time 499242240737 ps
CPU time 706.51 seconds
Started Jul 02 09:33:10 AM PDT 24
Finished Jul 02 09:44:57 AM PDT 24
Peak memory 201920 kb
Host smart-8665402d-3ad4-46e9-b75d-09d13681801e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113060570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4113060570
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2718488128
Short name T67
Test name
Test status
Simulation time 104629236947 ps
CPU time 220.64 seconds
Started Jul 02 09:33:09 AM PDT 24
Finished Jul 02 09:36:50 AM PDT 24
Peak memory 210236 kb
Host smart-750f1fc5-bb8a-4ce2-b431-5e61c1c9882c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718488128 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2718488128
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3810325489
Short name T670
Test name
Test status
Simulation time 355457982 ps
CPU time 1.06 seconds
Started Jul 02 09:33:19 AM PDT 24
Finished Jul 02 09:33:21 AM PDT 24
Peak memory 201588 kb
Host smart-747349ba-d36a-4250-8732-6307e70c9e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810325489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3810325489
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.518025804
Short name T355
Test name
Test status
Simulation time 163100989247 ps
CPU time 355.86 seconds
Started Jul 02 09:33:13 AM PDT 24
Finished Jul 02 09:39:10 AM PDT 24
Peak memory 201984 kb
Host smart-5c5cf735-c99c-45c0-9c2a-e4c3f1b16bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518025804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.518025804
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3027527661
Short name T434
Test name
Test status
Simulation time 170131942664 ps
CPU time 107.06 seconds
Started Jul 02 09:33:16 AM PDT 24
Finished Jul 02 09:35:03 AM PDT 24
Peak memory 201892 kb
Host smart-bc0bf943-df48-4e90-af24-88a1fd28c039
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027527661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3027527661
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1500085888
Short name T472
Test name
Test status
Simulation time 325764714348 ps
CPU time 675.18 seconds
Started Jul 02 09:33:13 AM PDT 24
Finished Jul 02 09:44:29 AM PDT 24
Peak memory 201980 kb
Host smart-0cd9bb6b-b137-4c1c-8287-dbebd35e25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500085888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1500085888
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3603828054
Short name T405
Test name
Test status
Simulation time 497978003038 ps
CPU time 255.34 seconds
Started Jul 02 09:33:13 AM PDT 24
Finished Jul 02 09:37:29 AM PDT 24
Peak memory 201848 kb
Host smart-46ea0f7d-112c-4b36-8956-86c4eea000c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603828054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3603828054
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3949182579
Short name T665
Test name
Test status
Simulation time 404837246910 ps
CPU time 80.66 seconds
Started Jul 02 09:33:16 AM PDT 24
Finished Jul 02 09:34:37 AM PDT 24
Peak memory 201916 kb
Host smart-912c3649-97e4-47a8-aea6-5f59c803c88b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949182579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3949182579
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4154476367
Short name T535
Test name
Test status
Simulation time 28012019907 ps
CPU time 68.01 seconds
Started Jul 02 09:33:19 AM PDT 24
Finished Jul 02 09:34:27 AM PDT 24
Peak memory 201672 kb
Host smart-803d6c0d-2a43-45c2-8c1f-d888c69d826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154476367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4154476367
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1395076808
Short name T384
Test name
Test status
Simulation time 4177514317 ps
CPU time 5.62 seconds
Started Jul 02 09:33:19 AM PDT 24
Finished Jul 02 09:33:25 AM PDT 24
Peak memory 201712 kb
Host smart-6330ea25-5b79-4f1b-b6a9-962f6874efb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395076808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1395076808
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.389198114
Short name T204
Test name
Test status
Simulation time 5872822637 ps
CPU time 14.24 seconds
Started Jul 02 09:33:14 AM PDT 24
Finished Jul 02 09:33:29 AM PDT 24
Peak memory 201696 kb
Host smart-fd194b8c-5edb-42a3-8a98-e86db64383b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389198114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.389198114
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.256437939
Short name T437
Test name
Test status
Simulation time 379682991 ps
CPU time 0.89 seconds
Started Jul 02 09:31:18 AM PDT 24
Finished Jul 02 09:31:19 AM PDT 24
Peak memory 201656 kb
Host smart-fb24a242-d0f2-40a2-92f9-c0a8ef13b1ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256437939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.256437939
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1663959907
Short name T337
Test name
Test status
Simulation time 166134890886 ps
CPU time 350.63 seconds
Started Jul 02 09:31:10 AM PDT 24
Finished Jul 02 09:37:01 AM PDT 24
Peak memory 201952 kb
Host smart-894c69e9-25fa-45ad-9cbd-5d2fe2030105
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663959907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1663959907
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.973706583
Short name T201
Test name
Test status
Simulation time 333624315551 ps
CPU time 106.79 seconds
Started Jul 02 09:31:13 AM PDT 24
Finished Jul 02 09:33:00 AM PDT 24
Peak memory 201892 kb
Host smart-ca86929a-d704-403d-ae9f-666dfbaead9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973706583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.973706583
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.183522687
Short name T354
Test name
Test status
Simulation time 163837260737 ps
CPU time 108.38 seconds
Started Jul 02 09:31:09 AM PDT 24
Finished Jul 02 09:32:57 AM PDT 24
Peak memory 201896 kb
Host smart-cb1bd524-3264-47ff-af75-a830aacb00c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183522687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.183522687
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1981574226
Short name T529
Test name
Test status
Simulation time 327558718679 ps
CPU time 743.12 seconds
Started Jul 02 09:31:07 AM PDT 24
Finished Jul 02 09:43:31 AM PDT 24
Peak memory 201908 kb
Host smart-202437f4-8eba-4c90-8e37-6c5574c69589
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981574226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1981574226
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3914820133
Short name T695
Test name
Test status
Simulation time 162392803787 ps
CPU time 170.77 seconds
Started Jul 02 09:31:07 AM PDT 24
Finished Jul 02 09:33:58 AM PDT 24
Peak memory 201968 kb
Host smart-e75f59f4-e0d4-48b0-968d-0a38a02708bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914820133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3914820133
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2586696123
Short name T124
Test name
Test status
Simulation time 333564520787 ps
CPU time 389.86 seconds
Started Jul 02 09:31:06 AM PDT 24
Finished Jul 02 09:37:36 AM PDT 24
Peak memory 201824 kb
Host smart-5e6775fd-c07e-4646-a1b0-ed60763f6b9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586696123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2586696123
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1126545788
Short name T471
Test name
Test status
Simulation time 401389147924 ps
CPU time 501.88 seconds
Started Jul 02 09:31:10 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 201884 kb
Host smart-9f77e96d-d209-45c8-a8fc-ee61a7bb71d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126545788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1126545788
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2745564970
Short name T367
Test name
Test status
Simulation time 105597427901 ps
CPU time 548.49 seconds
Started Jul 02 09:31:16 AM PDT 24
Finished Jul 02 09:40:25 AM PDT 24
Peak memory 202272 kb
Host smart-955e8a94-33b8-4c49-bf32-a0ed77f467e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745564970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2745564970
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.930890525
Short name T656
Test name
Test status
Simulation time 29611188438 ps
CPU time 47.94 seconds
Started Jul 02 09:31:12 AM PDT 24
Finished Jul 02 09:32:01 AM PDT 24
Peak memory 201716 kb
Host smart-8ede5b30-0c1a-4fbe-8afc-461f0f26a0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930890525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.930890525
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3417617153
Short name T623
Test name
Test status
Simulation time 2857729262 ps
CPU time 3.76 seconds
Started Jul 02 09:31:10 AM PDT 24
Finished Jul 02 09:31:14 AM PDT 24
Peak memory 201748 kb
Host smart-ac0a973f-347c-4a97-a858-721ac65b8694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417617153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3417617153
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.532911038
Short name T97
Test name
Test status
Simulation time 4407644386 ps
CPU time 5.29 seconds
Started Jul 02 09:31:15 AM PDT 24
Finished Jul 02 09:31:20 AM PDT 24
Peak memory 217156 kb
Host smart-a2385177-0e1e-478e-9149-8f553f77b308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532911038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.532911038
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3983724138
Short name T655
Test name
Test status
Simulation time 5821736704 ps
CPU time 14.75 seconds
Started Jul 02 09:31:08 AM PDT 24
Finished Jul 02 09:31:23 AM PDT 24
Peak memory 201720 kb
Host smart-097371b1-8d00-4b07-8526-7703fcc0f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983724138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3983724138
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.410817803
Short name T40
Test name
Test status
Simulation time 364156932729 ps
CPU time 395.28 seconds
Started Jul 02 09:31:13 AM PDT 24
Finished Jul 02 09:37:49 AM PDT 24
Peak memory 201856 kb
Host smart-f8ff6962-4888-4d6d-a8f8-495be883a918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410817803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.410817803
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1344198721
Short name T541
Test name
Test status
Simulation time 238389399429 ps
CPU time 129.85 seconds
Started Jul 02 09:31:16 AM PDT 24
Finished Jul 02 09:33:27 AM PDT 24
Peak memory 210212 kb
Host smart-ede31456-3d45-426b-a599-22db891fa3e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344198721 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1344198721
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2372806877
Short name T718
Test name
Test status
Simulation time 384388185 ps
CPU time 0.95 seconds
Started Jul 02 09:33:30 AM PDT 24
Finished Jul 02 09:33:32 AM PDT 24
Peak memory 201636 kb
Host smart-5ad45f62-3d54-41cf-ae46-87a82a2b8e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372806877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2372806877
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.890531874
Short name T751
Test name
Test status
Simulation time 176196242265 ps
CPU time 370.17 seconds
Started Jul 02 09:33:22 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 202120 kb
Host smart-7210072d-626f-4c04-8f0c-a595831b2f46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890531874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.890531874
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.192795728
Short name T253
Test name
Test status
Simulation time 177120878623 ps
CPU time 184.84 seconds
Started Jul 02 09:33:26 AM PDT 24
Finished Jul 02 09:36:31 AM PDT 24
Peak memory 201976 kb
Host smart-e75fa0b4-3b1a-4f8f-958c-e512b876a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192795728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.192795728
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2499514333
Short name T348
Test name
Test status
Simulation time 323231203124 ps
CPU time 220.9 seconds
Started Jul 02 09:33:26 AM PDT 24
Finished Jul 02 09:37:07 AM PDT 24
Peak memory 201956 kb
Host smart-1f514e3f-6f0a-4713-b37e-6e45f0893f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499514333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2499514333
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2466077203
Short name T709
Test name
Test status
Simulation time 506756883570 ps
CPU time 1068.46 seconds
Started Jul 02 09:33:27 AM PDT 24
Finished Jul 02 09:51:16 AM PDT 24
Peak memory 201880 kb
Host smart-a4e744d3-a07c-4572-8a5f-f7d4bc8c661a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466077203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2466077203
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1938856889
Short name T164
Test name
Test status
Simulation time 333525336197 ps
CPU time 204.35 seconds
Started Jul 02 09:33:17 AM PDT 24
Finished Jul 02 09:36:42 AM PDT 24
Peak memory 201924 kb
Host smart-e6ad89c3-124c-457a-a5a5-9e898c31a1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938856889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1938856889
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1891942191
Short name T561
Test name
Test status
Simulation time 165197884166 ps
CPU time 194.45 seconds
Started Jul 02 09:33:19 AM PDT 24
Finished Jul 02 09:36:34 AM PDT 24
Peak memory 201896 kb
Host smart-4bc093de-3692-4977-8f56-cedd53351bd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891942191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1891942191
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1860985254
Short name T660
Test name
Test status
Simulation time 525810893110 ps
CPU time 464.3 seconds
Started Jul 02 09:33:22 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 201936 kb
Host smart-0456c7f8-ac21-4003-bff5-63b6bfc33747
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860985254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1860985254
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3903155720
Short name T690
Test name
Test status
Simulation time 574640794449 ps
CPU time 1344.22 seconds
Started Jul 02 09:33:24 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 202076 kb
Host smart-19dfa180-849f-404c-a53f-3dce2b2d6dc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903155720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3903155720
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3678655535
Short name T31
Test name
Test status
Simulation time 27849139199 ps
CPU time 11.97 seconds
Started Jul 02 09:33:28 AM PDT 24
Finished Jul 02 09:33:40 AM PDT 24
Peak memory 201712 kb
Host smart-8dac5f6c-ea41-4c54-8086-2ce4004990ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678655535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3678655535
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2814082710
Short name T499
Test name
Test status
Simulation time 4731265153 ps
CPU time 3.53 seconds
Started Jul 02 09:33:29 AM PDT 24
Finished Jul 02 09:33:33 AM PDT 24
Peak memory 201732 kb
Host smart-58b9a1e8-5855-4cb5-919f-362085fd5ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814082710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2814082710
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2290966853
Short name T512
Test name
Test status
Simulation time 5909240519 ps
CPU time 12.89 seconds
Started Jul 02 09:33:19 AM PDT 24
Finished Jul 02 09:33:32 AM PDT 24
Peak memory 201716 kb
Host smart-213043b8-be54-4a01-bef0-5a6d8122534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290966853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2290966853
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1737303134
Short name T38
Test name
Test status
Simulation time 119853733512 ps
CPU time 569.05 seconds
Started Jul 02 09:33:30 AM PDT 24
Finished Jul 02 09:43:00 AM PDT 24
Peak memory 202216 kb
Host smart-c1115dae-33b6-4f19-9f74-264af86ac1ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737303134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1737303134
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.441934619
Short name T245
Test name
Test status
Simulation time 49442972663 ps
CPU time 102.92 seconds
Started Jul 02 09:33:27 AM PDT 24
Finished Jul 02 09:35:11 AM PDT 24
Peak memory 202052 kb
Host smart-3f118052-5410-40e7-a22e-f3775369f35f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441934619 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.441934619
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2416233467
Short name T729
Test name
Test status
Simulation time 448666259 ps
CPU time 0.89 seconds
Started Jul 02 09:33:38 AM PDT 24
Finished Jul 02 09:33:39 AM PDT 24
Peak memory 201640 kb
Host smart-47334711-054a-477e-ba96-617492519a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416233467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2416233467
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.4261852499
Short name T177
Test name
Test status
Simulation time 513833706442 ps
CPU time 254.71 seconds
Started Jul 02 09:33:33 AM PDT 24
Finished Jul 02 09:37:49 AM PDT 24
Peak memory 201908 kb
Host smart-d155ef29-5345-4b9b-bcb6-7a535d2c3ee5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261852499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.4261852499
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2237226400
Short name T583
Test name
Test status
Simulation time 330372552569 ps
CPU time 774.82 seconds
Started Jul 02 09:33:34 AM PDT 24
Finished Jul 02 09:46:29 AM PDT 24
Peak memory 201884 kb
Host smart-d27f4c6b-4a3f-4e7a-a926-700bbb8552be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237226400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2237226400
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.543405991
Short name T105
Test name
Test status
Simulation time 489880296609 ps
CPU time 546.42 seconds
Started Jul 02 09:33:30 AM PDT 24
Finished Jul 02 09:42:36 AM PDT 24
Peak memory 201892 kb
Host smart-64766ec5-bf6f-4a67-9960-667353c6ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543405991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.543405991
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3192760373
Short name T703
Test name
Test status
Simulation time 487103781020 ps
CPU time 69.69 seconds
Started Jul 02 09:33:35 AM PDT 24
Finished Jul 02 09:34:45 AM PDT 24
Peak memory 201852 kb
Host smart-5f9a2137-40af-4a08-9aed-35076b2061b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192760373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3192760373
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2262968239
Short name T682
Test name
Test status
Simulation time 495095063857 ps
CPU time 293.07 seconds
Started Jul 02 09:33:33 AM PDT 24
Finished Jul 02 09:38:27 AM PDT 24
Peak memory 201936 kb
Host smart-e7a21723-c932-462f-92dd-a4178ee4e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262968239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2262968239
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.74544402
Short name T783
Test name
Test status
Simulation time 483335882272 ps
CPU time 224.59 seconds
Started Jul 02 09:33:30 AM PDT 24
Finished Jul 02 09:37:15 AM PDT 24
Peak memory 201812 kb
Host smart-034d38b5-acfc-447b-997d-66d61bb9b995
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74544402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed
.74544402
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1948404839
Short name T316
Test name
Test status
Simulation time 556035770432 ps
CPU time 1187.98 seconds
Started Jul 02 09:33:34 AM PDT 24
Finished Jul 02 09:53:23 AM PDT 24
Peak memory 201924 kb
Host smart-effd94a8-5add-4ed0-804d-15d262761dc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948404839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1948404839
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3270270851
Short name T611
Test name
Test status
Simulation time 213006716223 ps
CPU time 249.19 seconds
Started Jul 02 09:33:34 AM PDT 24
Finished Jul 02 09:37:43 AM PDT 24
Peak memory 201896 kb
Host smart-564c4aa6-6ea4-4ed8-8642-b6ca85cc3e84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270270851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3270270851
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2266478738
Short name T225
Test name
Test status
Simulation time 132513892848 ps
CPU time 659.18 seconds
Started Jul 02 09:33:38 AM PDT 24
Finished Jul 02 09:44:38 AM PDT 24
Peak memory 202144 kb
Host smart-a62bba5f-17ee-4d62-93b7-9b979410fd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266478738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2266478738
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3270632647
Short name T617
Test name
Test status
Simulation time 30260141603 ps
CPU time 18.02 seconds
Started Jul 02 09:33:40 AM PDT 24
Finished Jul 02 09:33:59 AM PDT 24
Peak memory 201700 kb
Host smart-c9e5310f-0bbd-4e77-a321-4e8a2a27506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270632647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3270632647
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2856572693
Short name T791
Test name
Test status
Simulation time 3879749722 ps
CPU time 5.25 seconds
Started Jul 02 09:33:34 AM PDT 24
Finished Jul 02 09:33:39 AM PDT 24
Peak memory 201636 kb
Host smart-0950c6ac-7d50-458c-8119-269c7673544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856572693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2856572693
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.680574597
Short name T407
Test name
Test status
Simulation time 6021049785 ps
CPU time 3.29 seconds
Started Jul 02 09:33:32 AM PDT 24
Finished Jul 02 09:33:36 AM PDT 24
Peak memory 201712 kb
Host smart-4b090bd3-167a-4f6c-a2f1-f992082d5172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680574597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.680574597
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.409644900
Short name T322
Test name
Test status
Simulation time 594160289296 ps
CPU time 1209.59 seconds
Started Jul 02 09:33:38 AM PDT 24
Finished Jul 02 09:53:48 AM PDT 24
Peak memory 201836 kb
Host smart-a7c2d5dd-9ad8-4c5a-adab-ef5bf0411a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409644900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
409644900
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1736150135
Short name T78
Test name
Test status
Simulation time 252148736633 ps
CPU time 453.31 seconds
Started Jul 02 09:33:39 AM PDT 24
Finished Jul 02 09:41:13 AM PDT 24
Peak memory 210724 kb
Host smart-20feca46-e734-4b3b-a912-53315728dc8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736150135 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1736150135
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2521873880
Short name T663
Test name
Test status
Simulation time 447939689 ps
CPU time 0.78 seconds
Started Jul 02 09:33:47 AM PDT 24
Finished Jul 02 09:33:48 AM PDT 24
Peak memory 201632 kb
Host smart-9f67e7ec-792b-4637-8ab9-7895c705c844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521873880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2521873880
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3783341042
Short name T202
Test name
Test status
Simulation time 496274081697 ps
CPU time 294.01 seconds
Started Jul 02 09:33:44 AM PDT 24
Finished Jul 02 09:38:39 AM PDT 24
Peak memory 201928 kb
Host smart-fd2790c7-4383-44a0-a530-c2a7cac27002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783341042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3783341042
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1370148115
Short name T647
Test name
Test status
Simulation time 329048043017 ps
CPU time 230.99 seconds
Started Jul 02 09:33:38 AM PDT 24
Finished Jul 02 09:37:30 AM PDT 24
Peak memory 201928 kb
Host smart-6f79f8c4-ffe5-4efe-87b5-e40d3e750e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370148115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1370148115
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.680237082
Short name T460
Test name
Test status
Simulation time 161364501017 ps
CPU time 91.56 seconds
Started Jul 02 09:33:43 AM PDT 24
Finished Jul 02 09:35:15 AM PDT 24
Peak memory 201852 kb
Host smart-1c860197-37d8-4d2c-be6a-bc6700b6cc8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=680237082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.680237082
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.516528371
Short name T128
Test name
Test status
Simulation time 485454849166 ps
CPU time 273.52 seconds
Started Jul 02 09:33:40 AM PDT 24
Finished Jul 02 09:38:14 AM PDT 24
Peak memory 201924 kb
Host smart-9d3a058c-43d9-40d0-a967-ba5a13fcd4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516528371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.516528371
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3208122717
Short name T677
Test name
Test status
Simulation time 164597435197 ps
CPU time 188.99 seconds
Started Jul 02 09:33:38 AM PDT 24
Finished Jul 02 09:36:48 AM PDT 24
Peak memory 201872 kb
Host smart-2c94ad8a-7ed7-4146-bf3f-4af8e44da7d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208122717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3208122717
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1153197261
Short name T325
Test name
Test status
Simulation time 543695492827 ps
CPU time 1278.29 seconds
Started Jul 02 09:33:43 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 201940 kb
Host smart-e3a65405-8309-451f-b51c-f3628e0f5a4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153197261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1153197261
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.450851830
Short name T488
Test name
Test status
Simulation time 198065185654 ps
CPU time 433.81 seconds
Started Jul 02 09:33:42 AM PDT 24
Finished Jul 02 09:40:56 AM PDT 24
Peak memory 201908 kb
Host smart-fd1893a1-9892-4cd6-add4-5c0a7771a98f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450851830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.450851830
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.441810376
Short name T598
Test name
Test status
Simulation time 107854105156 ps
CPU time 349.58 seconds
Started Jul 02 09:33:47 AM PDT 24
Finished Jul 02 09:39:37 AM PDT 24
Peak memory 202220 kb
Host smart-9ba1be94-07ad-4af9-ab06-0d876bbfaa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441810376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.441810376
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.893201560
Short name T504
Test name
Test status
Simulation time 29007130123 ps
CPU time 4.14 seconds
Started Jul 02 09:33:44 AM PDT 24
Finished Jul 02 09:33:49 AM PDT 24
Peak memory 201716 kb
Host smart-e08c3108-f10e-4618-bc74-584c201dd866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893201560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.893201560
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.434738224
Short name T423
Test name
Test status
Simulation time 4066698010 ps
CPU time 3.62 seconds
Started Jul 02 09:33:45 AM PDT 24
Finished Jul 02 09:33:49 AM PDT 24
Peak memory 201732 kb
Host smart-a669e111-d3ad-4b0e-86e3-0b9f8f560a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434738224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.434738224
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.4294854492
Short name T417
Test name
Test status
Simulation time 5947065435 ps
CPU time 14.01 seconds
Started Jul 02 09:33:40 AM PDT 24
Finished Jul 02 09:33:55 AM PDT 24
Peak memory 201704 kb
Host smart-59729fc5-d453-4aba-b396-7dca33d08493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294854492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4294854492
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.168578366
Short name T542
Test name
Test status
Simulation time 41025984174 ps
CPU time 94.53 seconds
Started Jul 02 09:33:45 AM PDT 24
Finished Jul 02 09:35:20 AM PDT 24
Peak memory 201692 kb
Host smart-d813d62c-472d-4714-82a7-d6a1bf2284de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168578366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
168578366
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.233397902
Short name T619
Test name
Test status
Simulation time 494869733 ps
CPU time 1.75 seconds
Started Jul 02 09:33:58 AM PDT 24
Finished Jul 02 09:34:00 AM PDT 24
Peak memory 201664 kb
Host smart-38264680-d251-4d89-8e19-3114d9270f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233397902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.233397902
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.564653593
Short name T200
Test name
Test status
Simulation time 513513550488 ps
CPU time 1103.98 seconds
Started Jul 02 09:33:54 AM PDT 24
Finished Jul 02 09:52:18 AM PDT 24
Peak memory 201900 kb
Host smart-adeaf49b-bca1-4db6-b9af-413753027e97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564653593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.564653593
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1804916721
Short name T174
Test name
Test status
Simulation time 404748120141 ps
CPU time 254.57 seconds
Started Jul 02 09:33:55 AM PDT 24
Finished Jul 02 09:38:10 AM PDT 24
Peak memory 201908 kb
Host smart-6f7e7758-3109-4a56-ab4b-d66b70516d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804916721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1804916721
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3212231287
Short name T455
Test name
Test status
Simulation time 167018467217 ps
CPU time 392.61 seconds
Started Jul 02 09:33:49 AM PDT 24
Finished Jul 02 09:40:22 AM PDT 24
Peak memory 201904 kb
Host smart-955e4047-3407-46ca-8b46-7662f7ae14c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212231287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3212231287
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.930643608
Short name T378
Test name
Test status
Simulation time 502579793281 ps
CPU time 541.7 seconds
Started Jul 02 09:33:50 AM PDT 24
Finished Jul 02 09:42:52 AM PDT 24
Peak memory 201896 kb
Host smart-7bd40fb1-2f57-4c89-8b96-008e818652e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930643608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.930643608
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2255032108
Short name T513
Test name
Test status
Simulation time 164460742221 ps
CPU time 99.95 seconds
Started Jul 02 09:33:47 AM PDT 24
Finished Jul 02 09:35:27 AM PDT 24
Peak memory 201944 kb
Host smart-328c75dd-58cb-4c21-a8e1-7cd8dbb43da1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255032108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2255032108
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.22806064
Short name T736
Test name
Test status
Simulation time 394275156555 ps
CPU time 465.77 seconds
Started Jul 02 09:33:50 AM PDT 24
Finished Jul 02 09:41:37 AM PDT 24
Peak memory 201784 kb
Host smart-4411046a-6683-4d7e-85c2-36cc60bed0fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22806064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.a
dc_ctrl_filters_wakeup_fixed.22806064
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.169766233
Short name T125
Test name
Test status
Simulation time 73433143019 ps
CPU time 259.27 seconds
Started Jul 02 09:33:54 AM PDT 24
Finished Jul 02 09:38:14 AM PDT 24
Peak memory 202292 kb
Host smart-9034c189-9b06-4c98-b20d-28baafe76eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169766233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.169766233
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.812852678
Short name T506
Test name
Test status
Simulation time 45164980003 ps
CPU time 108.67 seconds
Started Jul 02 09:33:55 AM PDT 24
Finished Jul 02 09:35:44 AM PDT 24
Peak memory 201708 kb
Host smart-fb76dbbe-578c-4b8f-a4f2-a143d6b942b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812852678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.812852678
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1565579697
Short name T445
Test name
Test status
Simulation time 4058291820 ps
CPU time 3.41 seconds
Started Jul 02 09:33:54 AM PDT 24
Finished Jul 02 09:33:58 AM PDT 24
Peak memory 201684 kb
Host smart-f7e9051c-0324-41f1-86c9-255ce9618bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565579697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1565579697
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3541090785
Short name T759
Test name
Test status
Simulation time 5671545835 ps
CPU time 13.11 seconds
Started Jul 02 09:33:46 AM PDT 24
Finished Jul 02 09:34:00 AM PDT 24
Peak memory 201728 kb
Host smart-3a7c3612-0574-47e7-a722-9d2f9bc173dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541090785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3541090785
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.418048629
Short name T715
Test name
Test status
Simulation time 421951924881 ps
CPU time 454.93 seconds
Started Jul 02 09:34:01 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 210436 kb
Host smart-e1340a4a-44c1-4dcb-bc05-b79f3d20ad22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418048629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
418048629
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2042735991
Short name T680
Test name
Test status
Simulation time 16346049621 ps
CPU time 37.34 seconds
Started Jul 02 09:34:00 AM PDT 24
Finished Jul 02 09:34:38 AM PDT 24
Peak memory 210288 kb
Host smart-9c9162d5-b9d8-4b94-8174-fd7e2c550a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042735991 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2042735991
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2067199084
Short name T95
Test name
Test status
Simulation time 335939665 ps
CPU time 0.8 seconds
Started Jul 02 09:34:01 AM PDT 24
Finished Jul 02 09:34:02 AM PDT 24
Peak memory 201676 kb
Host smart-f3ca3039-a68e-495b-9976-fade168e6046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067199084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2067199084
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3471294858
Short name T198
Test name
Test status
Simulation time 195645276062 ps
CPU time 106.58 seconds
Started Jul 02 09:34:08 AM PDT 24
Finished Jul 02 09:35:55 AM PDT 24
Peak memory 201956 kb
Host smart-51f4f6d3-3447-450e-9cd1-7711d41f5e91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471294858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3471294858
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1503341299
Short name T565
Test name
Test status
Simulation time 168025648349 ps
CPU time 377.38 seconds
Started Jul 02 09:34:02 AM PDT 24
Finished Jul 02 09:40:20 AM PDT 24
Peak memory 201924 kb
Host smart-1c1cf847-40e6-465e-9a25-62aa96651fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503341299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1503341299
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2481694752
Short name T318
Test name
Test status
Simulation time 492259171203 ps
CPU time 1102.24 seconds
Started Jul 02 09:33:59 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 201908 kb
Host smart-f4e68ce1-1db0-4699-bb90-d1f26bb8a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481694752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2481694752
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4177644042
Short name T396
Test name
Test status
Simulation time 326804558777 ps
CPU time 172.79 seconds
Started Jul 02 09:34:02 AM PDT 24
Finished Jul 02 09:36:55 AM PDT 24
Peak memory 201876 kb
Host smart-2b9ddb75-8076-4901-9c7f-ec69f1d1d492
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177644042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.4177644042
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2349067321
Short name T560
Test name
Test status
Simulation time 167308458073 ps
CPU time 350.58 seconds
Started Jul 02 09:34:00 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 201852 kb
Host smart-ecd3193d-3c17-49bd-9c54-daa89e7c2144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349067321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2349067321
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3832500282
Short name T6
Test name
Test status
Simulation time 322379432651 ps
CPU time 128.06 seconds
Started Jul 02 09:33:59 AM PDT 24
Finished Jul 02 09:36:08 AM PDT 24
Peak memory 201892 kb
Host smart-f8776dc6-de48-4e55-beb2-7739b23bcd5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832500282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3832500282
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.241430672
Short name T524
Test name
Test status
Simulation time 565478875057 ps
CPU time 1336.16 seconds
Started Jul 02 09:34:08 AM PDT 24
Finished Jul 02 09:56:24 AM PDT 24
Peak memory 201980 kb
Host smart-8fd3f796-acca-4747-980d-b704c3b0158e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241430672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.241430672
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.901609411
Short name T648
Test name
Test status
Simulation time 596201478881 ps
CPU time 357.56 seconds
Started Jul 02 09:34:03 AM PDT 24
Finished Jul 02 09:40:01 AM PDT 24
Peak memory 201812 kb
Host smart-5c8b48d7-d115-4737-81b7-31019d0684e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901609411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.901609411
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3446846364
Short name T60
Test name
Test status
Simulation time 78442137190 ps
CPU time 389.45 seconds
Started Jul 02 09:34:01 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 202232 kb
Host smart-bcda32fa-02b3-4313-8473-50510b6f9d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446846364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3446846364
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1266773756
Short name T538
Test name
Test status
Simulation time 31640499869 ps
CPU time 36.39 seconds
Started Jul 02 09:34:09 AM PDT 24
Finished Jul 02 09:34:45 AM PDT 24
Peak memory 201700 kb
Host smart-6e1f2f82-b595-4ab7-8538-100120f944e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266773756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1266773756
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2216585819
Short name T782
Test name
Test status
Simulation time 5053631734 ps
CPU time 13.08 seconds
Started Jul 02 09:34:08 AM PDT 24
Finished Jul 02 09:34:22 AM PDT 24
Peak memory 201700 kb
Host smart-ad1be2c7-4cec-4715-b5af-9f538e1a35e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216585819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2216585819
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2271321493
Short name T539
Test name
Test status
Simulation time 5514960312 ps
CPU time 7.26 seconds
Started Jul 02 09:34:00 AM PDT 24
Finished Jul 02 09:34:08 AM PDT 24
Peak memory 201636 kb
Host smart-80a7cf37-c517-4c51-8f14-64d21572a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271321493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2271321493
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2148219040
Short name T692
Test name
Test status
Simulation time 164144443233 ps
CPU time 26.73 seconds
Started Jul 02 09:34:03 AM PDT 24
Finished Jul 02 09:34:30 AM PDT 24
Peak memory 201820 kb
Host smart-4a753500-5100-4881-9e5a-7e6ad3d46713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148219040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2148219040
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2191623063
Short name T269
Test name
Test status
Simulation time 67626260811 ps
CPU time 136.27 seconds
Started Jul 02 09:34:09 AM PDT 24
Finished Jul 02 09:36:25 AM PDT 24
Peak memory 211248 kb
Host smart-c626c1f9-8d8c-469f-a679-96ac864d934e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191623063 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2191623063
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.211921
Short name T607
Test name
Test status
Simulation time 442714566 ps
CPU time 1.49 seconds
Started Jul 02 09:34:18 AM PDT 24
Finished Jul 02 09:34:20 AM PDT 24
Peak memory 201664 kb
Host smart-4f521057-67a3-48ee-9907-adb54796bdd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.211921
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.963133174
Short name T211
Test name
Test status
Simulation time 353511974176 ps
CPU time 168.38 seconds
Started Jul 02 09:34:09 AM PDT 24
Finished Jul 02 09:36:58 AM PDT 24
Peak memory 201892 kb
Host smart-f55b8981-9cdc-46dd-a65b-1f7dd61a74d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963133174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.963133174
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.627498304
Short name T261
Test name
Test status
Simulation time 487470061487 ps
CPU time 1083.83 seconds
Started Jul 02 09:34:07 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 201924 kb
Host smart-14032c70-e572-4363-a510-07800d9a5277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627498304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.627498304
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3015798500
Short name T461
Test name
Test status
Simulation time 496358065651 ps
CPU time 578.11 seconds
Started Jul 02 09:34:06 AM PDT 24
Finished Jul 02 09:43:45 AM PDT 24
Peak memory 201900 kb
Host smart-732f7811-2a42-45a9-8a4a-00563fd0be09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015798500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3015798500
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.4196291753
Short name T275
Test name
Test status
Simulation time 326835508213 ps
CPU time 91.84 seconds
Started Jul 02 09:34:06 AM PDT 24
Finished Jul 02 09:35:38 AM PDT 24
Peak memory 201928 kb
Host smart-28391ad9-d371-4af6-85bd-072bb77a4e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196291753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4196291753
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.289822732
Short name T486
Test name
Test status
Simulation time 321461474561 ps
CPU time 698.66 seconds
Started Jul 02 09:34:05 AM PDT 24
Finished Jul 02 09:45:44 AM PDT 24
Peak memory 201800 kb
Host smart-c2f3a9d5-a7b5-47ce-b6b0-25824f7d7d64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=289822732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.289822732
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1959508566
Short name T199
Test name
Test status
Simulation time 540228709605 ps
CPU time 599.93 seconds
Started Jul 02 09:34:10 AM PDT 24
Finished Jul 02 09:44:10 AM PDT 24
Peak memory 201964 kb
Host smart-9c03d6be-3144-4b23-8bb8-44cdc7714372
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959508566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1959508566
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.4028804965
Short name T592
Test name
Test status
Simulation time 204101125345 ps
CPU time 141.77 seconds
Started Jul 02 09:34:09 AM PDT 24
Finished Jul 02 09:36:31 AM PDT 24
Peak memory 201900 kb
Host smart-5545e665-f65a-4cde-befd-c7e6a1dab182
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028804965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.4028804965
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.127410380
Short name T418
Test name
Test status
Simulation time 82103651415 ps
CPU time 295.67 seconds
Started Jul 02 09:34:14 AM PDT 24
Finished Jul 02 09:39:10 AM PDT 24
Peak memory 202244 kb
Host smart-c57f9591-3e4a-4843-9e40-b3f120b791f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127410380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.127410380
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3463870986
Short name T427
Test name
Test status
Simulation time 37040043168 ps
CPU time 10.69 seconds
Started Jul 02 09:34:11 AM PDT 24
Finished Jul 02 09:34:22 AM PDT 24
Peak memory 201688 kb
Host smart-b32e81b6-a634-4ee0-b455-a366a045a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463870986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3463870986
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1009533206
Short name T71
Test name
Test status
Simulation time 3562422201 ps
CPU time 2.86 seconds
Started Jul 02 09:34:11 AM PDT 24
Finished Jul 02 09:34:14 AM PDT 24
Peak memory 201692 kb
Host smart-1954067c-88fe-44f7-9ad5-a96258b93cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009533206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1009533206
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.432771037
Short name T640
Test name
Test status
Simulation time 6034879607 ps
CPU time 14.03 seconds
Started Jul 02 09:34:04 AM PDT 24
Finished Jul 02 09:34:18 AM PDT 24
Peak memory 201720 kb
Host smart-f622f894-be4f-42f5-bab2-3ceaa54a38fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432771037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.432771037
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2659479050
Short name T366
Test name
Test status
Simulation time 207867969686 ps
CPU time 621.15 seconds
Started Jul 02 09:34:13 AM PDT 24
Finished Jul 02 09:44:34 AM PDT 24
Peak memory 202248 kb
Host smart-d111e421-20e8-4cc7-9324-27597eafda7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659479050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2659479050
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1509379033
Short name T36
Test name
Test status
Simulation time 18836728507 ps
CPU time 45.38 seconds
Started Jul 02 09:34:15 AM PDT 24
Finished Jul 02 09:35:01 AM PDT 24
Peak memory 202024 kb
Host smart-e09b6654-a32d-4143-80a6-901450033c24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509379033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1509379033
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1427733243
Short name T754
Test name
Test status
Simulation time 500119088 ps
CPU time 0.7 seconds
Started Jul 02 09:34:28 AM PDT 24
Finished Jul 02 09:34:29 AM PDT 24
Peak memory 201588 kb
Host smart-99d74574-8739-4db0-95d3-ab7065da88fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427733243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1427733243
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2861641357
Short name T270
Test name
Test status
Simulation time 179131985715 ps
CPU time 305.97 seconds
Started Jul 02 09:34:21 AM PDT 24
Finished Jul 02 09:39:27 AM PDT 24
Peak memory 201960 kb
Host smart-660a50c2-8251-479f-9bb1-aad8d1142c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861641357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2861641357
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3202235974
Short name T335
Test name
Test status
Simulation time 487478701619 ps
CPU time 1124.57 seconds
Started Jul 02 09:34:18 AM PDT 24
Finished Jul 02 09:53:03 AM PDT 24
Peak memory 201884 kb
Host smart-c79f01f6-c8bc-46fc-8d8e-a62d12186cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202235974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3202235974
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.908547531
Short name T485
Test name
Test status
Simulation time 162212966338 ps
CPU time 27.24 seconds
Started Jul 02 09:34:21 AM PDT 24
Finished Jul 02 09:34:49 AM PDT 24
Peak memory 201948 kb
Host smart-959aa9de-ea87-4738-8062-8bbfb8c6842d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=908547531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.908547531
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.514906179
Short name T180
Test name
Test status
Simulation time 493911907839 ps
CPU time 275.2 seconds
Started Jul 02 09:34:20 AM PDT 24
Finished Jul 02 09:38:56 AM PDT 24
Peak memory 201892 kb
Host smart-347b9899-adfd-42ba-9a7f-3694601c06c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514906179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.514906179
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1495919108
Short name T599
Test name
Test status
Simulation time 319961607746 ps
CPU time 358.97 seconds
Started Jul 02 09:34:18 AM PDT 24
Finished Jul 02 09:40:17 AM PDT 24
Peak memory 201896 kb
Host smart-17c63649-adb8-462a-96d6-86c2811ca186
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495919108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1495919108
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1050477307
Short name T616
Test name
Test status
Simulation time 278741090614 ps
CPU time 129.22 seconds
Started Jul 02 09:34:21 AM PDT 24
Finished Jul 02 09:36:31 AM PDT 24
Peak memory 201880 kb
Host smart-b2d463ca-3277-43d1-9a1f-df814863695a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050477307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1050477307
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2112659338
Short name T756
Test name
Test status
Simulation time 197812805194 ps
CPU time 201.64 seconds
Started Jul 02 09:34:25 AM PDT 24
Finished Jul 02 09:37:47 AM PDT 24
Peak memory 201896 kb
Host smart-e5b8ab14-27dc-46e1-9c62-33200330915d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112659338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2112659338
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2983882275
Short name T226
Test name
Test status
Simulation time 104868710728 ps
CPU time 510.06 seconds
Started Jul 02 09:34:27 AM PDT 24
Finished Jul 02 09:42:57 AM PDT 24
Peak memory 202304 kb
Host smart-bd54ffe5-d193-487c-be04-7f55a4804ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983882275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2983882275
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2311330939
Short name T589
Test name
Test status
Simulation time 31411463827 ps
CPU time 46.34 seconds
Started Jul 02 09:34:23 AM PDT 24
Finished Jul 02 09:35:10 AM PDT 24
Peak memory 201708 kb
Host smart-a0f99e78-ab73-4939-85a2-6bea390fd2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311330939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2311330939
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3940746674
Short name T653
Test name
Test status
Simulation time 2969970015 ps
CPU time 2.38 seconds
Started Jul 02 09:34:23 AM PDT 24
Finished Jul 02 09:34:26 AM PDT 24
Peak memory 201708 kb
Host smart-07377bd1-66c8-4274-91de-337425e07124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940746674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3940746674
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3473420314
Short name T389
Test name
Test status
Simulation time 6112112602 ps
CPU time 4.16 seconds
Started Jul 02 09:34:16 AM PDT 24
Finished Jul 02 09:34:21 AM PDT 24
Peak memory 201696 kb
Host smart-0df1fcba-4d91-4c05-ab11-534b48a349f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473420314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3473420314
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.20715280
Short name T66
Test name
Test status
Simulation time 451184702967 ps
CPU time 245.85 seconds
Started Jul 02 09:34:26 AM PDT 24
Finished Jul 02 09:38:32 AM PDT 24
Peak memory 210604 kb
Host smart-d7f5966c-c94a-4abc-9077-93ddcc40b42e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715280 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.20715280
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2226525058
Short name T683
Test name
Test status
Simulation time 502710018 ps
CPU time 1.19 seconds
Started Jul 02 09:34:32 AM PDT 24
Finished Jul 02 09:34:34 AM PDT 24
Peak memory 201624 kb
Host smart-203da0a0-411f-4b5b-ba20-64d9b020167a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226525058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2226525058
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1754890145
Short name T283
Test name
Test status
Simulation time 571668151580 ps
CPU time 338.78 seconds
Started Jul 02 09:34:28 AM PDT 24
Finished Jul 02 09:40:07 AM PDT 24
Peak memory 201916 kb
Host smart-69a9dc90-96e8-474c-81ef-3c4c0f1b038d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754890145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1754890145
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1071863309
Short name T588
Test name
Test status
Simulation time 161032921656 ps
CPU time 334.78 seconds
Started Jul 02 09:34:29 AM PDT 24
Finished Jul 02 09:40:04 AM PDT 24
Peak memory 201912 kb
Host smart-8b136f4d-f8c3-4591-a6f8-f7c2ec22dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071863309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1071863309
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3214696092
Short name T413
Test name
Test status
Simulation time 167821713540 ps
CPU time 193.07 seconds
Started Jul 02 09:34:33 AM PDT 24
Finished Jul 02 09:37:46 AM PDT 24
Peak memory 201880 kb
Host smart-048776de-9064-4953-8244-f79ad6132653
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214696092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3214696092
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3963764204
Short name T459
Test name
Test status
Simulation time 328889994839 ps
CPU time 755.22 seconds
Started Jul 02 09:34:26 AM PDT 24
Finished Jul 02 09:47:02 AM PDT 24
Peak memory 201992 kb
Host smart-1546c077-4c18-44d7-82f8-82f0b94b117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963764204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3963764204
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.646229265
Short name T632
Test name
Test status
Simulation time 334280488271 ps
CPU time 200.08 seconds
Started Jul 02 09:34:28 AM PDT 24
Finished Jul 02 09:37:48 AM PDT 24
Peak memory 201900 kb
Host smart-04dd014b-ceb7-4797-afea-ff0464710ffd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646229265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.646229265
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1055820879
Short name T642
Test name
Test status
Simulation time 182930895045 ps
CPU time 415.34 seconds
Started Jul 02 09:34:31 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 201840 kb
Host smart-31dbc6f4-bc92-42da-a974-b8a67095f2f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055820879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1055820879
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1580687653
Short name T406
Test name
Test status
Simulation time 593128385243 ps
CPU time 1148.66 seconds
Started Jul 02 09:34:28 AM PDT 24
Finished Jul 02 09:53:38 AM PDT 24
Peak memory 201888 kb
Host smart-7944fe8a-97be-47e3-844e-7aa4dd9713b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580687653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1580687653
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.444316904
Short name T114
Test name
Test status
Simulation time 85688719442 ps
CPU time 373.79 seconds
Started Jul 02 09:34:33 AM PDT 24
Finished Jul 02 09:40:47 AM PDT 24
Peak memory 202288 kb
Host smart-0b7fa77c-2de9-452d-8093-202ec8bc3e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444316904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.444316904
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2826767626
Short name T102
Test name
Test status
Simulation time 26847665853 ps
CPU time 12.41 seconds
Started Jul 02 09:34:36 AM PDT 24
Finished Jul 02 09:34:49 AM PDT 24
Peak memory 201696 kb
Host smart-b3014e5b-c38e-448f-8ec4-b4bc4bf00f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826767626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2826767626
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3866182479
Short name T659
Test name
Test status
Simulation time 3406654937 ps
CPU time 7.77 seconds
Started Jul 02 09:34:33 AM PDT 24
Finished Jul 02 09:34:41 AM PDT 24
Peak memory 201672 kb
Host smart-5a84ae4b-1fcc-42b3-b831-ef80cca71197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866182479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3866182479
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2793098281
Short name T645
Test name
Test status
Simulation time 5564845707 ps
CPU time 3.92 seconds
Started Jul 02 09:34:24 AM PDT 24
Finished Jul 02 09:34:29 AM PDT 24
Peak memory 201716 kb
Host smart-588169ba-5d94-4660-bc0d-a8d200c84fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793098281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2793098281
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.462296186
Short name T700
Test name
Test status
Simulation time 229507085406 ps
CPU time 500.88 seconds
Started Jul 02 09:34:32 AM PDT 24
Finished Jul 02 09:42:54 AM PDT 24
Peak memory 201980 kb
Host smart-05a207c9-c2da-452c-97d6-a731ac378d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462296186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
462296186
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3176258628
Short name T727
Test name
Test status
Simulation time 472234620187 ps
CPU time 252.54 seconds
Started Jul 02 09:34:34 AM PDT 24
Finished Jul 02 09:38:47 AM PDT 24
Peak memory 210492 kb
Host smart-8d15c79f-2f93-4398-9bd9-7ef9af7821d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176258628 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3176258628
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.20900852
Short name T537
Test name
Test status
Simulation time 347871557 ps
CPU time 1.38 seconds
Started Jul 02 09:34:40 AM PDT 24
Finished Jul 02 09:34:41 AM PDT 24
Peak memory 201676 kb
Host smart-c8ab86c4-7612-44a8-9e86-968bdd63ae43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20900852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.20900852
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.4148752234
Short name T351
Test name
Test status
Simulation time 164786959071 ps
CPU time 355.8 seconds
Started Jul 02 09:34:36 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 201888 kb
Host smart-0b6362cc-84d8-4e4f-bf57-e3fb879f76f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148752234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.4148752234
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3046976954
Short name T801
Test name
Test status
Simulation time 173612282323 ps
CPU time 292.31 seconds
Started Jul 02 09:34:38 AM PDT 24
Finished Jul 02 09:39:30 AM PDT 24
Peak memory 201920 kb
Host smart-5434afab-e505-42dd-b906-ce59c7d728fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046976954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3046976954
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4032824692
Short name T165
Test name
Test status
Simulation time 483812568723 ps
CPU time 1076.33 seconds
Started Jul 02 09:34:37 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 201880 kb
Host smart-3720c620-a529-496d-bf28-6b8052e0ed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032824692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4032824692
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2721882586
Short name T567
Test name
Test status
Simulation time 169447628260 ps
CPU time 208.4 seconds
Started Jul 02 09:34:37 AM PDT 24
Finished Jul 02 09:38:06 AM PDT 24
Peak memory 201896 kb
Host smart-7a0eed51-737c-4f98-8744-9d6fe2a01e8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721882586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2721882586
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1985234018
Short name T346
Test name
Test status
Simulation time 330974785585 ps
CPU time 204.36 seconds
Started Jul 02 09:34:38 AM PDT 24
Finished Jul 02 09:38:03 AM PDT 24
Peak memory 201944 kb
Host smart-eeb2e8ca-49a2-415e-9a59-de72e8e63f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985234018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1985234018
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1872787748
Short name T379
Test name
Test status
Simulation time 327830966122 ps
CPU time 746.26 seconds
Started Jul 02 09:34:38 AM PDT 24
Finished Jul 02 09:47:05 AM PDT 24
Peak memory 201884 kb
Host smart-4c2cbe6a-b34f-457d-bf05-4de4e5ee6147
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872787748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1872787748
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3884923639
Short name T250
Test name
Test status
Simulation time 361465763288 ps
CPU time 199.46 seconds
Started Jul 02 09:34:38 AM PDT 24
Finished Jul 02 09:37:58 AM PDT 24
Peak memory 201972 kb
Host smart-b6cf103e-ffd6-4265-809e-34c5cfd2e388
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884923639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3884923639
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2961711170
Short name T661
Test name
Test status
Simulation time 208873510973 ps
CPU time 124.16 seconds
Started Jul 02 09:34:37 AM PDT 24
Finished Jul 02 09:36:41 AM PDT 24
Peak memory 201880 kb
Host smart-d415bba6-d388-434a-b21f-97193a327ee3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961711170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2961711170
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1050829820
Short name T575
Test name
Test status
Simulation time 40200825044 ps
CPU time 46.97 seconds
Started Jul 02 09:34:41 AM PDT 24
Finished Jul 02 09:35:28 AM PDT 24
Peak memory 201708 kb
Host smart-017a4c7d-1a00-414a-afdd-dad306874d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050829820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1050829820
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1092463822
Short name T371
Test name
Test status
Simulation time 3674839285 ps
CPU time 8.6 seconds
Started Jul 02 09:34:41 AM PDT 24
Finished Jul 02 09:34:50 AM PDT 24
Peak memory 201636 kb
Host smart-c12f69a6-71e7-4a40-80af-aa6d1a3f14da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092463822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1092463822
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.930236702
Short name T487
Test name
Test status
Simulation time 5694042057 ps
CPU time 6.78 seconds
Started Jul 02 09:34:32 AM PDT 24
Finished Jul 02 09:34:39 AM PDT 24
Peak memory 201712 kb
Host smart-60eca1e8-341b-417a-ba8a-11aaded1378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930236702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.930236702
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3011528212
Short name T255
Test name
Test status
Simulation time 469413725432 ps
CPU time 703.1 seconds
Started Jul 02 09:34:42 AM PDT 24
Finished Jul 02 09:46:26 AM PDT 24
Peak memory 218560 kb
Host smart-02cc27f0-f925-43f6-947e-7039cd768cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011528212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3011528212
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.601695517
Short name T59
Test name
Test status
Simulation time 332818598 ps
CPU time 0.81 seconds
Started Jul 02 09:35:00 AM PDT 24
Finished Jul 02 09:35:01 AM PDT 24
Peak memory 201632 kb
Host smart-2279cd8a-5143-45e8-b00d-9329c787f4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601695517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.601695517
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3249476914
Short name T310
Test name
Test status
Simulation time 185123454222 ps
CPU time 49.56 seconds
Started Jul 02 09:34:53 AM PDT 24
Finished Jul 02 09:35:43 AM PDT 24
Peak memory 201920 kb
Host smart-f45b17f4-6522-402a-b5c0-858f8cc52ec2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249476914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3249476914
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2099874039
Short name T122
Test name
Test status
Simulation time 366384403309 ps
CPU time 804.82 seconds
Started Jul 02 09:34:52 AM PDT 24
Finished Jul 02 09:48:17 AM PDT 24
Peak memory 201908 kb
Host smart-a265b92a-462a-4b6e-8d71-a98cc022b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099874039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2099874039
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4193738371
Short name T613
Test name
Test status
Simulation time 328709783426 ps
CPU time 643.07 seconds
Started Jul 02 09:34:45 AM PDT 24
Finished Jul 02 09:45:28 AM PDT 24
Peak memory 201836 kb
Host smart-04af6668-c4c8-4379-bcca-fab539e12a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193738371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4193738371
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3086330306
Short name T760
Test name
Test status
Simulation time 486855522877 ps
CPU time 1193.96 seconds
Started Jul 02 09:34:50 AM PDT 24
Finished Jul 02 09:54:44 AM PDT 24
Peak memory 201920 kb
Host smart-b6f485b1-b9b7-46ad-b756-fba5ff357982
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086330306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3086330306
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1238000080
Short name T186
Test name
Test status
Simulation time 491032070412 ps
CPU time 224.43 seconds
Started Jul 02 09:34:46 AM PDT 24
Finished Jul 02 09:38:30 AM PDT 24
Peak memory 201920 kb
Host smart-833df725-81b9-4f8b-b6a5-ab3a1089d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238000080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1238000080
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3013135781
Short name T673
Test name
Test status
Simulation time 484791063213 ps
CPU time 1052.21 seconds
Started Jul 02 09:34:47 AM PDT 24
Finished Jul 02 09:52:19 AM PDT 24
Peak memory 201892 kb
Host smart-e709f9e7-1d8c-4a89-98f3-d6007b632546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013135781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3013135781
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.851742761
Short name T657
Test name
Test status
Simulation time 394914031880 ps
CPU time 958.04 seconds
Started Jul 02 09:34:49 AM PDT 24
Finished Jul 02 09:50:47 AM PDT 24
Peak memory 201828 kb
Host smart-a0362b0d-aef9-492f-b42b-356b8433fbda
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851742761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.851742761
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3098420818
Short name T798
Test name
Test status
Simulation time 137434821269 ps
CPU time 450.28 seconds
Started Jul 02 09:34:52 AM PDT 24
Finished Jul 02 09:42:23 AM PDT 24
Peak memory 202276 kb
Host smart-5afbaa20-8e04-4589-ae73-736a3d42c9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098420818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3098420818
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2361392255
Short name T773
Test name
Test status
Simulation time 37129915146 ps
CPU time 43.57 seconds
Started Jul 02 09:34:52 AM PDT 24
Finished Jul 02 09:35:36 AM PDT 24
Peak memory 201720 kb
Host smart-082085c7-a81a-4901-b8eb-7c8508594c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361392255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2361392255
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.834413853
Short name T720
Test name
Test status
Simulation time 2932882917 ps
CPU time 3.56 seconds
Started Jul 02 09:34:53 AM PDT 24
Finished Jul 02 09:34:57 AM PDT 24
Peak memory 201744 kb
Host smart-59432915-9bad-40f8-bb24-590edd927232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834413853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.834413853
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2870263364
Short name T408
Test name
Test status
Simulation time 5913601671 ps
CPU time 4.29 seconds
Started Jul 02 09:34:40 AM PDT 24
Finished Jul 02 09:34:45 AM PDT 24
Peak memory 201724 kb
Host smart-54e349bb-0a8e-4918-a8bc-360a739431c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870263364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2870263364
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1889005342
Short name T189
Test name
Test status
Simulation time 337653170030 ps
CPU time 786.05 seconds
Started Jul 02 09:34:58 AM PDT 24
Finished Jul 02 09:48:05 AM PDT 24
Peak memory 201892 kb
Host smart-8d2bf359-f718-4a88-9fb3-5af28df70b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889005342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1889005342
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2685403046
Short name T18
Test name
Test status
Simulation time 282141450210 ps
CPU time 186.89 seconds
Started Jul 02 09:35:00 AM PDT 24
Finished Jul 02 09:38:07 AM PDT 24
Peak memory 210844 kb
Host smart-eb4c9645-3b7e-4865-8e74-1df7efc20ee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685403046 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2685403046
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2015425808
Short name T636
Test name
Test status
Simulation time 385719694 ps
CPU time 1.12 seconds
Started Jul 02 09:31:26 AM PDT 24
Finished Jul 02 09:31:28 AM PDT 24
Peak memory 201668 kb
Host smart-85d62079-44aa-4ebe-8c41-8f2df20a6b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015425808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2015425808
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2885775347
Short name T183
Test name
Test status
Simulation time 177896516061 ps
CPU time 89.89 seconds
Started Jul 02 09:31:18 AM PDT 24
Finished Jul 02 09:32:49 AM PDT 24
Peak memory 201824 kb
Host smart-3d459811-7939-4a7e-9315-b9c69dc4cd3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885775347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2885775347
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2725213444
Short name T674
Test name
Test status
Simulation time 166562548784 ps
CPU time 396.29 seconds
Started Jul 02 09:31:19 AM PDT 24
Finished Jul 02 09:37:56 AM PDT 24
Peak memory 201924 kb
Host smart-dad84a9f-705f-4ad6-a643-4d739e29272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725213444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2725213444
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.119693952
Short name T312
Test name
Test status
Simulation time 480720492853 ps
CPU time 1014.95 seconds
Started Jul 02 09:31:15 AM PDT 24
Finished Jul 02 09:48:10 AM PDT 24
Peak memory 201892 kb
Host smart-4f35656c-b094-4d91-aecc-88e9c374bda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119693952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.119693952
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1419070238
Short name T610
Test name
Test status
Simulation time 165167481541 ps
CPU time 349.2 seconds
Started Jul 02 09:31:17 AM PDT 24
Finished Jul 02 09:37:06 AM PDT 24
Peak memory 201872 kb
Host smart-6efc95d3-d5ff-49d0-a848-0f45998ca8b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419070238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1419070238
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.432639059
Short name T510
Test name
Test status
Simulation time 329418029925 ps
CPU time 360.57 seconds
Started Jul 02 09:31:15 AM PDT 24
Finished Jul 02 09:37:16 AM PDT 24
Peak memory 201904 kb
Host smart-82603853-e550-4e9a-bfa9-972a24cb24ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=432639059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.432639059
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3370050695
Short name T482
Test name
Test status
Simulation time 181610248838 ps
CPU time 211.51 seconds
Started Jul 02 09:31:17 AM PDT 24
Finished Jul 02 09:34:49 AM PDT 24
Peak memory 201896 kb
Host smart-4e1c0db4-1da0-43fd-88f0-efe2fe35c04a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370050695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3370050695
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2168621721
Short name T722
Test name
Test status
Simulation time 201913391192 ps
CPU time 160.79 seconds
Started Jul 02 09:31:16 AM PDT 24
Finished Jul 02 09:33:57 AM PDT 24
Peak memory 201868 kb
Host smart-0c49f391-ca4a-4e02-bcc0-1ab1c01ad62c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168621721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2168621721
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1389741309
Short name T740
Test name
Test status
Simulation time 69503468603 ps
CPU time 364.64 seconds
Started Jul 02 09:31:20 AM PDT 24
Finished Jul 02 09:37:25 AM PDT 24
Peak memory 202232 kb
Host smart-5eead086-9b12-4b63-8a56-949f2b6b525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389741309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1389741309
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2715800196
Short name T442
Test name
Test status
Simulation time 42328871208 ps
CPU time 96.86 seconds
Started Jul 02 09:31:20 AM PDT 24
Finished Jul 02 09:32:57 AM PDT 24
Peak memory 201716 kb
Host smart-da9edc85-699f-4e2c-b301-448795d00908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715800196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2715800196
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2070410095
Short name T505
Test name
Test status
Simulation time 4451329420 ps
CPU time 3.08 seconds
Started Jul 02 09:31:18 AM PDT 24
Finished Jul 02 09:31:21 AM PDT 24
Peak memory 201652 kb
Host smart-1238725a-e7df-4dbf-9035-2dd72c8a7ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070410095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2070410095
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2568955953
Short name T82
Test name
Test status
Simulation time 8651425088 ps
CPU time 5.44 seconds
Started Jul 02 09:31:21 AM PDT 24
Finished Jul 02 09:31:26 AM PDT 24
Peak memory 218220 kb
Host smart-7df9de4a-0c79-423a-af9a-62fb4c3530b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568955953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2568955953
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.4232707199
Short name T390
Test name
Test status
Simulation time 5923025033 ps
CPU time 5.27 seconds
Started Jul 02 09:31:15 AM PDT 24
Finished Jul 02 09:31:21 AM PDT 24
Peak memory 201708 kb
Host smart-8029a82d-6f18-42b2-9936-e84b1d639104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232707199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4232707199
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1107752562
Short name T531
Test name
Test status
Simulation time 498500447154 ps
CPU time 261.86 seconds
Started Jul 02 09:31:22 AM PDT 24
Finished Jul 02 09:35:44 AM PDT 24
Peak memory 201836 kb
Host smart-b4f2dcfa-1863-4367-b419-2ff3f3ba88b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107752562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1107752562
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4013012656
Short name T33
Test name
Test status
Simulation time 33675275428 ps
CPU time 74.24 seconds
Started Jul 02 09:31:21 AM PDT 24
Finished Jul 02 09:32:36 AM PDT 24
Peak memory 210548 kb
Host smart-d84254c3-3849-4c4b-9fca-bad43a77fa05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013012656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4013012656
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.832655788
Short name T520
Test name
Test status
Simulation time 459047110 ps
CPU time 0.73 seconds
Started Jul 02 09:35:04 AM PDT 24
Finished Jul 02 09:35:05 AM PDT 24
Peak memory 201588 kb
Host smart-5213f330-2a67-440e-9453-8c252e82ea7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832655788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.832655788
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.177339170
Short name T466
Test name
Test status
Simulation time 331957686008 ps
CPU time 809.53 seconds
Started Jul 02 09:35:01 AM PDT 24
Finished Jul 02 09:48:31 AM PDT 24
Peak memory 201960 kb
Host smart-b5ae86b0-0893-4495-a032-ebcf38951285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177339170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.177339170
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3579402349
Short name T104
Test name
Test status
Simulation time 168235439270 ps
CPU time 105.14 seconds
Started Jul 02 09:35:02 AM PDT 24
Finished Jul 02 09:36:48 AM PDT 24
Peak memory 201828 kb
Host smart-170e331c-6a92-4f1f-ad9a-36ba3f4eabce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579402349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3579402349
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2400872830
Short name T321
Test name
Test status
Simulation time 167968347513 ps
CPU time 200.13 seconds
Started Jul 02 09:34:56 AM PDT 24
Finished Jul 02 09:38:16 AM PDT 24
Peak memory 201940 kb
Host smart-bd2d08b8-4bfc-4c6d-bda2-7cd1bf9801a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400872830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2400872830
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3838238856
Short name T197
Test name
Test status
Simulation time 167267604466 ps
CPU time 92.47 seconds
Started Jul 02 09:35:02 AM PDT 24
Finished Jul 02 09:36:34 AM PDT 24
Peak memory 201956 kb
Host smart-9e7c3cde-4cc4-43a0-8953-20a60e3b6b83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838238856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3838238856
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1585291348
Short name T241
Test name
Test status
Simulation time 393025547604 ps
CPU time 175.83 seconds
Started Jul 02 09:35:02 AM PDT 24
Finished Jul 02 09:37:58 AM PDT 24
Peak memory 201944 kb
Host smart-f1232527-eb91-4070-bcdd-234fd612d88f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585291348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1585291348
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.572219637
Short name T719
Test name
Test status
Simulation time 204400842018 ps
CPU time 419.26 seconds
Started Jul 02 09:34:59 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 201876 kb
Host smart-0d8fc311-ac10-43df-8c2f-8533e96bfae6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572219637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.572219637
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.4034263070
Short name T222
Test name
Test status
Simulation time 107548003879 ps
CPU time 389.9 seconds
Started Jul 02 09:35:06 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 202300 kb
Host smart-dd77b312-d4ce-467e-885e-065e85a2074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034263070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.4034263070
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3237601582
Short name T555
Test name
Test status
Simulation time 27842400965 ps
CPU time 15.21 seconds
Started Jul 02 09:35:06 AM PDT 24
Finished Jul 02 09:35:21 AM PDT 24
Peak memory 201728 kb
Host smart-f0fde873-0109-4378-83db-d341b373e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237601582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3237601582
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3055504779
Short name T388
Test name
Test status
Simulation time 3251530834 ps
CPU time 1.26 seconds
Started Jul 02 09:35:00 AM PDT 24
Finished Jul 02 09:35:01 AM PDT 24
Peak memory 201720 kb
Host smart-3a1069b4-10df-4308-9aae-174d4a6e35ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055504779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3055504779
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.703179170
Short name T790
Test name
Test status
Simulation time 6045310291 ps
CPU time 7.82 seconds
Started Jul 02 09:34:57 AM PDT 24
Finished Jul 02 09:35:05 AM PDT 24
Peak memory 201716 kb
Host smart-134e2b84-7856-4dff-b729-a167671314fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703179170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.703179170
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2061374415
Short name T345
Test name
Test status
Simulation time 336859018864 ps
CPU time 389.4 seconds
Started Jul 02 09:35:03 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 201960 kb
Host smart-2a86f8d6-f60d-41b1-a8b5-132028dbc0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061374415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2061374415
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.376670663
Short name T490
Test name
Test status
Simulation time 333021978 ps
CPU time 0.73 seconds
Started Jul 02 09:35:17 AM PDT 24
Finished Jul 02 09:35:18 AM PDT 24
Peak memory 201668 kb
Host smart-d86a0285-7ee8-4ac3-b882-b7fe558c6a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376670663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.376670663
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2612352818
Short name T738
Test name
Test status
Simulation time 177835152333 ps
CPU time 121.22 seconds
Started Jul 02 09:35:12 AM PDT 24
Finished Jul 02 09:37:14 AM PDT 24
Peak memory 201920 kb
Host smart-acc0aab5-d38f-4d60-9ad6-116fb2ed105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612352818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2612352818
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4246722433
Short name T213
Test name
Test status
Simulation time 489383553329 ps
CPU time 1070.54 seconds
Started Jul 02 09:35:08 AM PDT 24
Finished Jul 02 09:52:59 AM PDT 24
Peak memory 202184 kb
Host smart-36d1c7f6-51ac-487d-a357-386b2d198d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246722433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4246722433
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3866869359
Short name T507
Test name
Test status
Simulation time 164189321582 ps
CPU time 174.72 seconds
Started Jul 02 09:35:10 AM PDT 24
Finished Jul 02 09:38:05 AM PDT 24
Peak memory 201900 kb
Host smart-c3fbabf7-35db-4d97-98d0-9e315b6e0057
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866869359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3866869359
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1571510632
Short name T419
Test name
Test status
Simulation time 163069337864 ps
CPU time 94.51 seconds
Started Jul 02 09:35:11 AM PDT 24
Finished Jul 02 09:36:46 AM PDT 24
Peak memory 201852 kb
Host smart-1e17134a-541e-4cd0-9178-2ad8d9e7a28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571510632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1571510632
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3722957735
Short name T163
Test name
Test status
Simulation time 318967465537 ps
CPU time 344.68 seconds
Started Jul 02 09:35:10 AM PDT 24
Finished Jul 02 09:40:55 AM PDT 24
Peak memory 201972 kb
Host smart-17a2aeb3-1a89-4655-b5a6-6b214c6b4e8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722957735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3722957735
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3978374534
Short name T209
Test name
Test status
Simulation time 407379833845 ps
CPU time 216.3 seconds
Started Jul 02 09:35:14 AM PDT 24
Finished Jul 02 09:38:50 AM PDT 24
Peak memory 201808 kb
Host smart-b7e1fde6-245a-4cfd-b5ec-8d1005e71bd3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978374534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3978374534
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4242942724
Short name T477
Test name
Test status
Simulation time 84369354277 ps
CPU time 443.76 seconds
Started Jul 02 09:35:11 AM PDT 24
Finished Jul 02 09:42:35 AM PDT 24
Peak memory 202492 kb
Host smart-747d3d1d-7272-4909-8788-d43c43a69980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242942724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4242942724
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3824224982
Short name T803
Test name
Test status
Simulation time 26903044759 ps
CPU time 8.58 seconds
Started Jul 02 09:35:11 AM PDT 24
Finished Jul 02 09:35:20 AM PDT 24
Peak memory 201724 kb
Host smart-6037a4e5-39f2-439a-b305-73dcc6e9c73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824224982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3824224982
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3487701065
Short name T385
Test name
Test status
Simulation time 2947490531 ps
CPU time 6.38 seconds
Started Jul 02 09:35:10 AM PDT 24
Finished Jul 02 09:35:17 AM PDT 24
Peak memory 201692 kb
Host smart-6e617ff2-80a5-4036-9a91-427981923a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487701065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3487701065
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2880139818
Short name T416
Test name
Test status
Simulation time 5962119088 ps
CPU time 7.46 seconds
Started Jul 02 09:35:05 AM PDT 24
Finished Jul 02 09:35:12 AM PDT 24
Peak memory 201712 kb
Host smart-78f71ed0-3702-4396-bb9f-0f8febcb3865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880139818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2880139818
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2288627480
Short name T772
Test name
Test status
Simulation time 29887982359 ps
CPU time 70.51 seconds
Started Jul 02 09:35:10 AM PDT 24
Finished Jul 02 09:36:21 AM PDT 24
Peak memory 201672 kb
Host smart-0966fd66-6cd8-41ab-aba8-6d122f0bfec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288627480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2288627480
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2569653232
Short name T25
Test name
Test status
Simulation time 413293068357 ps
CPU time 494.43 seconds
Started Jul 02 09:35:13 AM PDT 24
Finished Jul 02 09:43:28 AM PDT 24
Peak memory 210556 kb
Host smart-9623645e-249a-4a65-bf14-b56e0d606559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569653232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2569653232
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1310754506
Short name T625
Test name
Test status
Simulation time 408889233 ps
CPU time 0.78 seconds
Started Jul 02 09:35:23 AM PDT 24
Finished Jul 02 09:35:24 AM PDT 24
Peak memory 201676 kb
Host smart-160e4c1b-011c-4768-9d6a-d8b659107710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310754506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1310754506
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2248324957
Short name T212
Test name
Test status
Simulation time 331418099942 ps
CPU time 370.4 seconds
Started Jul 02 09:35:16 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 201928 kb
Host smart-cd93c9ba-1975-462a-9894-ca5f5cb96e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248324957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2248324957
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2585078496
Short name T338
Test name
Test status
Simulation time 328875831804 ps
CPU time 396.52 seconds
Started Jul 02 09:35:14 AM PDT 24
Finished Jul 02 09:41:51 AM PDT 24
Peak memory 201936 kb
Host smart-6f315eea-07fa-4869-b5e2-f2e56c51421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585078496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2585078496
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3234706381
Short name T421
Test name
Test status
Simulation time 161738927571 ps
CPU time 352.78 seconds
Started Jul 02 09:35:17 AM PDT 24
Finished Jul 02 09:41:10 AM PDT 24
Peak memory 201900 kb
Host smart-15341db1-1fd3-41d5-93f8-8dbcc0ecb510
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234706381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3234706381
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.818711899
Short name T157
Test name
Test status
Simulation time 326163985913 ps
CPU time 413.62 seconds
Started Jul 02 09:35:14 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 201972 kb
Host smart-3213c670-991e-4709-8f98-7c6211e6f135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818711899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.818711899
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2862540133
Short name T404
Test name
Test status
Simulation time 324737330907 ps
CPU time 194.27 seconds
Started Jul 02 09:35:15 AM PDT 24
Finished Jul 02 09:38:29 AM PDT 24
Peak memory 201884 kb
Host smart-d3a42a91-b3e6-4eb7-94aa-aafcdb9cd4bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862540133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2862540133
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1865208194
Short name T726
Test name
Test status
Simulation time 204686070169 ps
CPU time 435.14 seconds
Started Jul 02 09:35:15 AM PDT 24
Finished Jul 02 09:42:30 AM PDT 24
Peak memory 201904 kb
Host smart-548138fc-6bd4-4da6-93c5-f6bfa9bc1657
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865208194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1865208194
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2739421574
Short name T236
Test name
Test status
Simulation time 112997640646 ps
CPU time 468.3 seconds
Started Jul 02 09:35:18 AM PDT 24
Finished Jul 02 09:43:06 AM PDT 24
Peak memory 202256 kb
Host smart-4cd673ab-b880-480d-bbb1-1eb666e6b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739421574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2739421574
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.540747042
Short name T518
Test name
Test status
Simulation time 42015002532 ps
CPU time 17.73 seconds
Started Jul 02 09:35:19 AM PDT 24
Finished Jul 02 09:35:37 AM PDT 24
Peak memory 201728 kb
Host smart-d85aa35e-b454-4731-976a-ace317e3471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540747042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.540747042
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2783239610
Short name T627
Test name
Test status
Simulation time 4413939833 ps
CPU time 3.45 seconds
Started Jul 02 09:35:19 AM PDT 24
Finished Jul 02 09:35:22 AM PDT 24
Peak memory 201692 kb
Host smart-fe6049d3-0df9-44bc-853c-ee71e373b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783239610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2783239610
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2049764000
Short name T393
Test name
Test status
Simulation time 5830655300 ps
CPU time 7.73 seconds
Started Jul 02 09:35:17 AM PDT 24
Finished Jul 02 09:35:25 AM PDT 24
Peak memory 201628 kb
Host smart-f0531bc9-2136-443e-9494-afc1cc793840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049764000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2049764000
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.255820253
Short name T37
Test name
Test status
Simulation time 169186138789 ps
CPU time 384.4 seconds
Started Jul 02 09:35:23 AM PDT 24
Finished Jul 02 09:41:48 AM PDT 24
Peak memory 201948 kb
Host smart-d0c124cb-4385-483d-b751-e4218d78160e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255820253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
255820253
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2504358330
Short name T17
Test name
Test status
Simulation time 71811566468 ps
CPU time 118.94 seconds
Started Jul 02 09:35:25 AM PDT 24
Finished Jul 02 09:37:24 AM PDT 24
Peak memory 210152 kb
Host smart-731de26d-088a-42ee-b85a-bfd231811f8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504358330 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2504358330
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2188232471
Short name T426
Test name
Test status
Simulation time 309879676 ps
CPU time 0.78 seconds
Started Jul 02 09:35:30 AM PDT 24
Finished Jul 02 09:35:31 AM PDT 24
Peak memory 201668 kb
Host smart-ca4d86db-d90e-4796-8bf9-70c491880eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188232471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2188232471
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3878359356
Short name T262
Test name
Test status
Simulation time 177981662665 ps
CPU time 111.08 seconds
Started Jul 02 09:35:27 AM PDT 24
Finished Jul 02 09:37:18 AM PDT 24
Peak memory 201928 kb
Host smart-eb638dd7-62ba-4d16-8d55-bdc3e628573b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878359356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3878359356
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.173729214
Short name T289
Test name
Test status
Simulation time 158728538701 ps
CPU time 203.76 seconds
Started Jul 02 09:35:22 AM PDT 24
Finished Jul 02 09:38:46 AM PDT 24
Peak memory 201840 kb
Host smart-51180463-de7b-43ff-96cb-672f169fb21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173729214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.173729214
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.617918333
Short name T115
Test name
Test status
Simulation time 494555442452 ps
CPU time 1171.74 seconds
Started Jul 02 09:35:28 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 201896 kb
Host smart-b33cf2af-c26e-4dff-9cca-2ab9f980d895
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=617918333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.617918333
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3825889338
Short name T706
Test name
Test status
Simulation time 487348883551 ps
CPU time 108.28 seconds
Started Jul 02 09:35:24 AM PDT 24
Finished Jul 02 09:37:13 AM PDT 24
Peak memory 201936 kb
Host smart-735f283b-6ecb-4547-b8c6-f485033d9194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825889338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3825889338
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1852597174
Short name T126
Test name
Test status
Simulation time 329307507052 ps
CPU time 223.73 seconds
Started Jul 02 09:35:23 AM PDT 24
Finished Jul 02 09:39:07 AM PDT 24
Peak memory 201952 kb
Host smart-b01bf96c-b110-4f03-bec7-d4feb6f36457
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852597174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1852597174
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3443500758
Short name T685
Test name
Test status
Simulation time 173109062473 ps
CPU time 103.43 seconds
Started Jul 02 09:35:27 AM PDT 24
Finished Jul 02 09:37:11 AM PDT 24
Peak memory 201912 kb
Host smart-13f533ec-50cc-4dc9-b631-e7848717e9f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443500758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3443500758
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.171748897
Short name T489
Test name
Test status
Simulation time 608450750489 ps
CPU time 1336.94 seconds
Started Jul 02 09:35:29 AM PDT 24
Finished Jul 02 09:57:46 AM PDT 24
Peak memory 201912 kb
Host smart-f24f1afd-5f0a-4fe6-bfa2-4c5bafe3ff92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171748897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.171748897
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4289311922
Short name T69
Test name
Test status
Simulation time 93716558265 ps
CPU time 489.24 seconds
Started Jul 02 09:35:30 AM PDT 24
Finished Jul 02 09:43:39 AM PDT 24
Peak memory 202276 kb
Host smart-73532546-fde3-4f4d-812c-759e5fe1d2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289311922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4289311922
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2605653230
Short name T637
Test name
Test status
Simulation time 30074858634 ps
CPU time 15.82 seconds
Started Jul 02 09:35:31 AM PDT 24
Finished Jul 02 09:35:48 AM PDT 24
Peak memory 201732 kb
Host smart-ac521173-bc57-4fd5-abe0-d0959c9b8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605653230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2605653230
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2954467270
Short name T730
Test name
Test status
Simulation time 4976167596 ps
CPU time 1.74 seconds
Started Jul 02 09:35:27 AM PDT 24
Finished Jul 02 09:35:29 AM PDT 24
Peak memory 201676 kb
Host smart-4927fbc1-0ed9-42ef-be25-52210feb6593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954467270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2954467270
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3927264395
Short name T496
Test name
Test status
Simulation time 6063658248 ps
CPU time 4.11 seconds
Started Jul 02 09:35:23 AM PDT 24
Finished Jul 02 09:35:28 AM PDT 24
Peak memory 201716 kb
Host smart-acfe23fb-9e56-459a-9f9f-07dc58c38fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927264395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3927264395
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2977131710
Short name T774
Test name
Test status
Simulation time 167637381912 ps
CPU time 355.19 seconds
Started Jul 02 09:35:30 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 201900 kb
Host smart-0eed1967-1047-4216-87f3-889e0d122db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977131710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2977131710
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2356031495
Short name T641
Test name
Test status
Simulation time 46522702637 ps
CPU time 113.1 seconds
Started Jul 02 09:35:36 AM PDT 24
Finished Jul 02 09:37:30 AM PDT 24
Peak memory 210520 kb
Host smart-567f5462-4a69-454a-8f5c-84408ba78a88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356031495 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2356031495
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.391015419
Short name T470
Test name
Test status
Simulation time 464610761 ps
CPU time 0.83 seconds
Started Jul 02 09:35:41 AM PDT 24
Finished Jul 02 09:35:42 AM PDT 24
Peak memory 201672 kb
Host smart-96bdd09d-f144-4a3f-b47a-ed9a57d29694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391015419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.391015419
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.4063332455
Short name T495
Test name
Test status
Simulation time 337088705014 ps
CPU time 276.57 seconds
Started Jul 02 09:35:34 AM PDT 24
Finished Jul 02 09:40:11 AM PDT 24
Peak memory 201976 kb
Host smart-c4ffced2-a5fc-49fd-bef5-37bf95400c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063332455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4063332455
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1180128788
Short name T547
Test name
Test status
Simulation time 495889757980 ps
CPU time 815.45 seconds
Started Jul 02 09:35:36 AM PDT 24
Finished Jul 02 09:49:12 AM PDT 24
Peak memory 201896 kb
Host smart-dc6aadbf-0184-43f2-9a10-3702b69ebf32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180128788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1180128788
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2753227069
Short name T536
Test name
Test status
Simulation time 160896059902 ps
CPU time 180.4 seconds
Started Jul 02 09:35:31 AM PDT 24
Finished Jul 02 09:38:31 AM PDT 24
Peak memory 201884 kb
Host smart-efbcc0f7-f435-4d79-bd87-3f35d032b8f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753227069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2753227069
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3242173854
Short name T273
Test name
Test status
Simulation time 530717469479 ps
CPU time 307.07 seconds
Started Jul 02 09:35:36 AM PDT 24
Finished Jul 02 09:40:44 AM PDT 24
Peak memory 201952 kb
Host smart-770c1977-62c9-477a-8a24-10d541935f76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242173854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3242173854
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3285994555
Short name T433
Test name
Test status
Simulation time 202366224231 ps
CPU time 443.13 seconds
Started Jul 02 09:35:37 AM PDT 24
Finished Jul 02 09:43:01 AM PDT 24
Peak memory 201900 kb
Host smart-91922d6d-563f-4608-bf65-272a4ef88701
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285994555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3285994555
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3407602205
Short name T732
Test name
Test status
Simulation time 97144142980 ps
CPU time 284.27 seconds
Started Jul 02 09:35:38 AM PDT 24
Finished Jul 02 09:40:23 AM PDT 24
Peak memory 202152 kb
Host smart-a79fa723-a757-46ff-9d76-5f8c91612a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407602205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3407602205
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3087122967
Short name T494
Test name
Test status
Simulation time 27556669422 ps
CPU time 31.05 seconds
Started Jul 02 09:35:38 AM PDT 24
Finished Jul 02 09:36:10 AM PDT 24
Peak memory 201700 kb
Host smart-1bccab0f-7153-403f-af3f-b5605a5a443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087122967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3087122967
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2573382201
Short name T112
Test name
Test status
Simulation time 3489940572 ps
CPU time 9.7 seconds
Started Jul 02 09:35:38 AM PDT 24
Finished Jul 02 09:35:48 AM PDT 24
Peak memory 201720 kb
Host smart-60a324d6-fe1d-468e-95f2-33b8da20dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573382201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2573382201
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3089292120
Short name T525
Test name
Test status
Simulation time 5980666020 ps
CPU time 14.16 seconds
Started Jul 02 09:35:32 AM PDT 24
Finished Jul 02 09:35:46 AM PDT 24
Peak memory 201728 kb
Host smart-3ebadbdb-80da-4c31-a98d-e1758c6bae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089292120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3089292120
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1631059373
Short name T704
Test name
Test status
Simulation time 471233260 ps
CPU time 1.58 seconds
Started Jul 02 09:35:49 AM PDT 24
Finished Jul 02 09:35:52 AM PDT 24
Peak memory 201668 kb
Host smart-2d353ac1-2321-4101-93e1-af09551fdbdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631059373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1631059373
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3163655220
Short name T284
Test name
Test status
Simulation time 366867078817 ps
CPU time 188.69 seconds
Started Jul 02 09:35:41 AM PDT 24
Finished Jul 02 09:38:50 AM PDT 24
Peak memory 201912 kb
Host smart-4f9aefd5-90c9-4864-b727-fe9ff8bde9a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163655220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3163655220
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1894588086
Short name T120
Test name
Test status
Simulation time 502417555325 ps
CPU time 393.56 seconds
Started Jul 02 09:35:50 AM PDT 24
Finished Jul 02 09:42:24 AM PDT 24
Peak memory 201896 kb
Host smart-3ce3262c-1d86-41e6-ae5a-78db23cce474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894588086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1894588086
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3275618175
Short name T467
Test name
Test status
Simulation time 162139545225 ps
CPU time 390.62 seconds
Started Jul 02 09:35:42 AM PDT 24
Finished Jul 02 09:42:13 AM PDT 24
Peak memory 201896 kb
Host smart-bb2e411f-9328-4ff4-8efd-66fa0faa721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275618175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3275618175
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2362922985
Short name T643
Test name
Test status
Simulation time 167591577050 ps
CPU time 181.08 seconds
Started Jul 02 09:35:42 AM PDT 24
Finished Jul 02 09:38:43 AM PDT 24
Peak memory 201880 kb
Host smart-3c2148da-91eb-4614-a4f5-101a2758a584
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362922985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2362922985
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.990494831
Short name T101
Test name
Test status
Simulation time 498027638100 ps
CPU time 306.7 seconds
Started Jul 02 09:35:50 AM PDT 24
Finished Jul 02 09:40:57 AM PDT 24
Peak memory 201872 kb
Host smart-2ac9c9b4-6de6-4a89-80bd-70816b62622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990494831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.990494831
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2997639215
Short name T206
Test name
Test status
Simulation time 161925781786 ps
CPU time 347.2 seconds
Started Jul 02 09:35:50 AM PDT 24
Finished Jul 02 09:41:38 AM PDT 24
Peak memory 201804 kb
Host smart-09ffdf78-e5e1-4686-b731-32f259d6fe1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997639215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2997639215
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.4023509115
Short name T326
Test name
Test status
Simulation time 435339955614 ps
CPU time 1029.24 seconds
Started Jul 02 09:35:40 AM PDT 24
Finished Jul 02 09:52:49 AM PDT 24
Peak memory 201956 kb
Host smart-f5a4f655-2331-48f9-8fd8-16155ddf25b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023509115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.4023509115
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4150111472
Short name T739
Test name
Test status
Simulation time 609424808527 ps
CPU time 181.3 seconds
Started Jul 02 09:35:42 AM PDT 24
Finished Jul 02 09:38:44 AM PDT 24
Peak memory 201884 kb
Host smart-0633ac43-9a3e-42f6-817f-fcc668b33b0f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150111472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4150111472
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2333928580
Short name T232
Test name
Test status
Simulation time 76995372273 ps
CPU time 272.63 seconds
Started Jul 02 09:35:44 AM PDT 24
Finished Jul 02 09:40:17 AM PDT 24
Peak memory 202208 kb
Host smart-717f8050-b089-4791-96cd-9739a17bf095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333928580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2333928580
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2288271110
Short name T528
Test name
Test status
Simulation time 36795804380 ps
CPU time 4.81 seconds
Started Jul 02 09:35:45 AM PDT 24
Finished Jul 02 09:35:50 AM PDT 24
Peak memory 201732 kb
Host smart-ced3be7e-faec-4cc7-ae21-e744152aaf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288271110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2288271110
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.366914857
Short name T687
Test name
Test status
Simulation time 2813842292 ps
CPU time 7.06 seconds
Started Jul 02 09:35:50 AM PDT 24
Finished Jul 02 09:35:58 AM PDT 24
Peak memory 201696 kb
Host smart-369ae12d-9564-4f58-a207-9f3ea1a871c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366914857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.366914857
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1502420521
Short name T401
Test name
Test status
Simulation time 5975674881 ps
CPU time 4.36 seconds
Started Jul 02 09:35:49 AM PDT 24
Finished Jul 02 09:35:54 AM PDT 24
Peak memory 201688 kb
Host smart-0100dab5-45a4-418e-8316-852fff102b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502420521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1502420521
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1637589647
Short name T646
Test name
Test status
Simulation time 3697883323 ps
CPU time 2.78 seconds
Started Jul 02 09:35:49 AM PDT 24
Finished Jul 02 09:35:52 AM PDT 24
Peak memory 201712 kb
Host smart-f8eb1a38-62da-4888-9408-e189f7d39a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637589647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1637589647
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2863873302
Short name T21
Test name
Test status
Simulation time 131195694811 ps
CPU time 60.31 seconds
Started Jul 02 09:35:44 AM PDT 24
Finished Jul 02 09:36:45 AM PDT 24
Peak memory 202036 kb
Host smart-9b1ad778-deb8-4927-b19e-21abf431750b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863873302 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2863873302
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2449195728
Short name T753
Test name
Test status
Simulation time 382882645 ps
CPU time 1.42 seconds
Started Jul 02 09:35:59 AM PDT 24
Finished Jul 02 09:36:00 AM PDT 24
Peak memory 201588 kb
Host smart-6029dd6b-69ca-402a-aac2-24ef23c0634d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449195728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2449195728
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3740441951
Short name T185
Test name
Test status
Simulation time 495201966069 ps
CPU time 280.9 seconds
Started Jul 02 09:35:54 AM PDT 24
Finished Jul 02 09:40:35 AM PDT 24
Peak memory 201884 kb
Host smart-72417b59-55bb-4e15-8083-7c52586c19fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740441951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3740441951
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2700390100
Short name T29
Test name
Test status
Simulation time 171757920239 ps
CPU time 379.45 seconds
Started Jul 02 09:35:59 AM PDT 24
Finished Jul 02 09:42:19 AM PDT 24
Peak memory 201896 kb
Host smart-15592c3e-6656-4f96-8f51-ecb573d802c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700390100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2700390100
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.87547249
Short name T546
Test name
Test status
Simulation time 497944833032 ps
CPU time 294.56 seconds
Started Jul 02 09:35:49 AM PDT 24
Finished Jul 02 09:40:44 AM PDT 24
Peak memory 201876 kb
Host smart-9e549e3c-f75c-4cf8-809b-4aa592dfd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87547249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.87547249
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.905247411
Short name T602
Test name
Test status
Simulation time 159658147755 ps
CPU time 190.56 seconds
Started Jul 02 09:35:52 AM PDT 24
Finished Jul 02 09:39:04 AM PDT 24
Peak memory 201888 kb
Host smart-335dfd3f-c830-4975-921a-76094a154319
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=905247411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.905247411
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4236980781
Short name T558
Test name
Test status
Simulation time 322239507482 ps
CPU time 103.09 seconds
Started Jul 02 09:35:49 AM PDT 24
Finished Jul 02 09:37:33 AM PDT 24
Peak memory 201852 kb
Host smart-e2dc5407-7152-4872-b18e-607852fdde17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236980781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4236980781
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1182000348
Short name T614
Test name
Test status
Simulation time 328367522109 ps
CPU time 352.59 seconds
Started Jul 02 09:35:49 AM PDT 24
Finished Jul 02 09:41:42 AM PDT 24
Peak memory 201900 kb
Host smart-92d46aa5-c53a-491d-b6e0-ae766cb80f61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182000348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1182000348
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3945831697
Short name T328
Test name
Test status
Simulation time 177009476406 ps
CPU time 221.77 seconds
Started Jul 02 09:35:53 AM PDT 24
Finished Jul 02 09:39:35 AM PDT 24
Peak memory 201936 kb
Host smart-c96d20e2-a842-46a8-b66a-4490e02b42f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945831697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3945831697
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2430663512
Short name T644
Test name
Test status
Simulation time 208590267400 ps
CPU time 444.07 seconds
Started Jul 02 09:35:59 AM PDT 24
Finished Jul 02 09:43:24 AM PDT 24
Peak memory 201868 kb
Host smart-bf4aa122-6934-4bca-a59e-37755e55aed7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430663512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2430663512
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.302173300
Short name T229
Test name
Test status
Simulation time 100455216976 ps
CPU time 394.36 seconds
Started Jul 02 09:35:58 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 202244 kb
Host smart-6af56374-5e29-49d1-b926-7fd7bb3ab094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302173300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.302173300
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2838361751
Short name T787
Test name
Test status
Simulation time 38758958444 ps
CPU time 23.88 seconds
Started Jul 02 09:35:57 AM PDT 24
Finished Jul 02 09:36:21 AM PDT 24
Peak memory 201696 kb
Host smart-72d6ca34-715e-458b-a255-f85087ef0a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838361751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2838361751
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3779864809
Short name T480
Test name
Test status
Simulation time 3419334207 ps
CPU time 8.78 seconds
Started Jul 02 09:35:57 AM PDT 24
Finished Jul 02 09:36:06 AM PDT 24
Peak memory 201680 kb
Host smart-d4263726-5f59-4ad2-8995-e12f69ec6747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779864809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3779864809
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.551294655
Short name T621
Test name
Test status
Simulation time 6023723961 ps
CPU time 8.43 seconds
Started Jul 02 09:35:49 AM PDT 24
Finished Jul 02 09:35:58 AM PDT 24
Peak memory 201716 kb
Host smart-23b47e0e-58f2-437c-823d-5a4809b74c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551294655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.551294655
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1722046927
Short name T249
Test name
Test status
Simulation time 502908921744 ps
CPU time 556.66 seconds
Started Jul 02 09:35:57 AM PDT 24
Finished Jul 02 09:45:14 AM PDT 24
Peak memory 201884 kb
Host smart-346b145a-d0f7-4899-848d-e3949bd7a732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722046927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1722046927
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1688032986
Short name T628
Test name
Test status
Simulation time 302895373 ps
CPU time 0.8 seconds
Started Jul 02 09:36:07 AM PDT 24
Finished Jul 02 09:36:08 AM PDT 24
Peak memory 201664 kb
Host smart-4b185fa8-3adb-4890-b367-7e20f73d263b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688032986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1688032986
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1921674019
Short name T243
Test name
Test status
Simulation time 589389740968 ps
CPU time 1415.78 seconds
Started Jul 02 09:36:05 AM PDT 24
Finished Jul 02 09:59:41 AM PDT 24
Peak memory 201964 kb
Host smart-2043e90e-3e91-46df-ac4c-08ea84b712ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921674019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1921674019
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2851553699
Short name T48
Test name
Test status
Simulation time 181901887292 ps
CPU time 75.19 seconds
Started Jul 02 09:36:05 AM PDT 24
Finished Jul 02 09:37:21 AM PDT 24
Peak memory 201928 kb
Host smart-eca30eef-ec7d-45ce-bca1-4f9a46ab08d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851553699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2851553699
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4010194615
Short name T323
Test name
Test status
Simulation time 493052473281 ps
CPU time 1046 seconds
Started Jul 02 09:35:59 AM PDT 24
Finished Jul 02 09:53:26 AM PDT 24
Peak memory 201916 kb
Host smart-0a1f96a6-07c9-4c01-9452-14ea1cb77ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010194615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4010194615
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1215157541
Short name T650
Test name
Test status
Simulation time 490139612885 ps
CPU time 1021.58 seconds
Started Jul 02 09:36:00 AM PDT 24
Finished Jul 02 09:53:02 AM PDT 24
Peak memory 201868 kb
Host smart-cea4481b-046f-4d93-8a22-1c128bc7ce3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215157541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1215157541
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1666209918
Short name T410
Test name
Test status
Simulation time 166430702868 ps
CPU time 70.11 seconds
Started Jul 02 09:35:59 AM PDT 24
Finished Jul 02 09:37:10 AM PDT 24
Peak memory 201896 kb
Host smart-02c2b0da-f6b6-4aaa-9fd6-ee38a54b197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666209918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1666209918
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1347504323
Short name T737
Test name
Test status
Simulation time 168683346620 ps
CPU time 385.99 seconds
Started Jul 02 09:36:02 AM PDT 24
Finished Jul 02 09:42:28 AM PDT 24
Peak memory 201900 kb
Host smart-69265a0e-6d16-4bc8-a46e-6c61494bb084
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347504323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1347504323
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3150128157
Short name T563
Test name
Test status
Simulation time 169353583371 ps
CPU time 411.64 seconds
Started Jul 02 09:35:59 AM PDT 24
Finished Jul 02 09:42:51 AM PDT 24
Peak memory 201976 kb
Host smart-eedf95ad-af1c-471c-b367-56b099d4133f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150128157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3150128157
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1659526724
Short name T375
Test name
Test status
Simulation time 396526422748 ps
CPU time 132.21 seconds
Started Jul 02 09:36:04 AM PDT 24
Finished Jul 02 09:38:17 AM PDT 24
Peak memory 201892 kb
Host smart-873e16a5-ee67-44a2-ab7c-111660ceaa8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659526724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1659526724
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3527351235
Short name T678
Test name
Test status
Simulation time 98209723485 ps
CPU time 408.27 seconds
Started Jul 02 09:36:08 AM PDT 24
Finished Jul 02 09:42:56 AM PDT 24
Peak memory 202216 kb
Host smart-a239464d-76e2-4823-8170-34cfef42e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527351235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3527351235
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2711628864
Short name T749
Test name
Test status
Simulation time 40603961062 ps
CPU time 21.84 seconds
Started Jul 02 09:36:03 AM PDT 24
Finished Jul 02 09:36:26 AM PDT 24
Peak memory 201720 kb
Host smart-2df33f8c-8799-4ad6-9cfc-47705b5f0aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711628864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2711628864
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3026601380
Short name T61
Test name
Test status
Simulation time 3136356462 ps
CPU time 4.48 seconds
Started Jul 02 09:36:04 AM PDT 24
Finished Jul 02 09:36:09 AM PDT 24
Peak memory 201644 kb
Host smart-7fcce381-9516-40fc-bc90-856073ea5eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026601380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3026601380
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3504954472
Short name T731
Test name
Test status
Simulation time 5788664860 ps
CPU time 4.38 seconds
Started Jul 02 09:36:02 AM PDT 24
Finished Jul 02 09:36:07 AM PDT 24
Peak memory 201724 kb
Host smart-d06535e9-3235-485d-a0e9-379e61959a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504954472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3504954472
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.529403729
Short name T65
Test name
Test status
Simulation time 152009855359 ps
CPU time 81.55 seconds
Started Jul 02 09:36:10 AM PDT 24
Finished Jul 02 09:37:32 AM PDT 24
Peak memory 210204 kb
Host smart-2ed58bc0-d3a1-4604-91f0-934fed56de34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529403729 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.529403729
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1658212186
Short name T62
Test name
Test status
Simulation time 354500806 ps
CPU time 0.99 seconds
Started Jul 02 09:36:21 AM PDT 24
Finished Jul 02 09:36:22 AM PDT 24
Peak memory 201648 kb
Host smart-d171a3cf-a82d-4834-9412-8c3a96c4fedc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658212186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1658212186
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4263870780
Short name T158
Test name
Test status
Simulation time 479892944739 ps
CPU time 1043.63 seconds
Started Jul 02 09:36:11 AM PDT 24
Finished Jul 02 09:53:35 AM PDT 24
Peak memory 201968 kb
Host smart-c88d4d3f-dfaf-4e5c-a3b1-c74c8cff5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263870780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4263870780
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4203511310
Short name T217
Test name
Test status
Simulation time 494211793298 ps
CPU time 210.26 seconds
Started Jul 02 09:36:11 AM PDT 24
Finished Jul 02 09:39:42 AM PDT 24
Peak memory 201868 kb
Host smart-f7ed9ef7-96b8-4e98-a0ca-6f9e8c21c0d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203511310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.4203511310
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.843237561
Short name T288
Test name
Test status
Simulation time 163302970614 ps
CPU time 183.46 seconds
Started Jul 02 09:36:10 AM PDT 24
Finished Jul 02 09:39:14 AM PDT 24
Peak memory 201884 kb
Host smart-0a932c60-e31d-4d66-8b2d-ee1ba62e56f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843237561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.843237561
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1826023114
Short name T800
Test name
Test status
Simulation time 166004964367 ps
CPU time 73.72 seconds
Started Jul 02 09:36:13 AM PDT 24
Finished Jul 02 09:37:27 AM PDT 24
Peak memory 201872 kb
Host smart-5bbd201c-735c-4fad-a500-96646b5ffce8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826023114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1826023114
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.383126183
Short name T305
Test name
Test status
Simulation time 209465523589 ps
CPU time 207.03 seconds
Started Jul 02 09:36:14 AM PDT 24
Finished Jul 02 09:39:41 AM PDT 24
Peak memory 201932 kb
Host smart-c415570a-e40b-434d-b13d-fdb7ccc22bef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383126183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.383126183
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2530427833
Short name T162
Test name
Test status
Simulation time 593138471123 ps
CPU time 269.17 seconds
Started Jul 02 09:36:25 AM PDT 24
Finished Jul 02 09:40:55 AM PDT 24
Peak memory 201864 kb
Host smart-9c9beb26-7e38-4d21-9115-aacefaed2544
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530427833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2530427833
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1226262031
Short name T517
Test name
Test status
Simulation time 104217264617 ps
CPU time 383.95 seconds
Started Jul 02 09:36:24 AM PDT 24
Finished Jul 02 09:42:48 AM PDT 24
Peak memory 202208 kb
Host smart-60c31c55-dff7-463b-8f41-1f5cc0142577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226262031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1226262031
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2603932770
Short name T111
Test name
Test status
Simulation time 38711438065 ps
CPU time 76.81 seconds
Started Jul 02 09:36:15 AM PDT 24
Finished Jul 02 09:37:32 AM PDT 24
Peak memory 201716 kb
Host smart-24c8b977-5682-4ff7-8d91-4cf3e3bcf1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603932770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2603932770
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3330183287
Short name T386
Test name
Test status
Simulation time 2814282790 ps
CPU time 6.17 seconds
Started Jul 02 09:36:15 AM PDT 24
Finished Jul 02 09:36:22 AM PDT 24
Peak memory 201724 kb
Host smart-c363d498-5d7f-46f4-892e-6d1f60bc209f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330183287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3330183287
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2321778404
Short name T498
Test name
Test status
Simulation time 5676708751 ps
CPU time 3.92 seconds
Started Jul 02 09:36:09 AM PDT 24
Finished Jul 02 09:36:13 AM PDT 24
Peak memory 201700 kb
Host smart-c79b555f-b1ab-494d-951c-bb35e76cf15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321778404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2321778404
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1805402647
Short name T721
Test name
Test status
Simulation time 433716337139 ps
CPU time 526.17 seconds
Started Jul 02 09:36:21 AM PDT 24
Finished Jul 02 09:45:08 AM PDT 24
Peak memory 202288 kb
Host smart-e96725c4-fc6c-4e4c-ae54-61e39740c6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805402647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1805402647
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.401537043
Short name T22
Test name
Test status
Simulation time 107286383715 ps
CPU time 187.98 seconds
Started Jul 02 09:36:26 AM PDT 24
Finished Jul 02 09:39:34 AM PDT 24
Peak memory 210600 kb
Host smart-a0724c4d-f9ff-4f47-908a-4461689fdabf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401537043 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.401537043
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2542794749
Short name T743
Test name
Test status
Simulation time 487513136 ps
CPU time 1.72 seconds
Started Jul 02 09:36:31 AM PDT 24
Finished Jul 02 09:36:33 AM PDT 24
Peak memory 201628 kb
Host smart-c82fe22c-b9ad-4416-a584-0fc848782f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542794749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2542794749
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1299145570
Short name T334
Test name
Test status
Simulation time 197272867664 ps
CPU time 410.89 seconds
Started Jul 02 09:36:27 AM PDT 24
Finished Jul 02 09:43:18 AM PDT 24
Peak memory 201976 kb
Host smart-bd5b841d-e0c3-4e74-9da6-63238c67ecfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299145570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1299145570
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3173764654
Short name T176
Test name
Test status
Simulation time 486755831907 ps
CPU time 977.6 seconds
Started Jul 02 09:36:20 AM PDT 24
Finished Jul 02 09:52:38 AM PDT 24
Peak memory 201900 kb
Host smart-4964c268-c8e0-42d3-b190-48a9cfd39bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173764654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3173764654
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.667092046
Short name T394
Test name
Test status
Simulation time 161825753214 ps
CPU time 194.34 seconds
Started Jul 02 09:36:23 AM PDT 24
Finished Jul 02 09:39:38 AM PDT 24
Peak memory 201868 kb
Host smart-b4687e97-eebd-4a77-a46c-9ca03bff078e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=667092046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.667092046
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2853976209
Short name T781
Test name
Test status
Simulation time 490060448242 ps
CPU time 1176.99 seconds
Started Jul 02 09:36:18 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 201944 kb
Host smart-b8f4f7d1-3e29-4e5e-9b96-f7bcadbf9d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853976209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2853976209
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1107527061
Short name T586
Test name
Test status
Simulation time 479781028906 ps
CPU time 996.3 seconds
Started Jul 02 09:36:31 AM PDT 24
Finished Jul 02 09:53:08 AM PDT 24
Peak memory 201860 kb
Host smart-94dae989-2a7c-49e9-8d64-e75d13f9e866
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107527061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1107527061
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1404504910
Short name T314
Test name
Test status
Simulation time 184666212615 ps
CPU time 186.01 seconds
Started Jul 02 09:36:27 AM PDT 24
Finished Jul 02 09:39:33 AM PDT 24
Peak memory 201988 kb
Host smart-5006de5c-3655-4842-8094-ce41ea8c700c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404504910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1404504910
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.838807193
Short name T443
Test name
Test status
Simulation time 194070833750 ps
CPU time 438.42 seconds
Started Jul 02 09:36:31 AM PDT 24
Finished Jul 02 09:43:50 AM PDT 24
Peak memory 201864 kb
Host smart-4387e7ee-b6fe-435f-a0b6-f2fb29e9ec9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838807193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.838807193
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3013138975
Short name T669
Test name
Test status
Simulation time 73277375656 ps
CPU time 431.17 seconds
Started Jul 02 09:36:30 AM PDT 24
Finished Jul 02 09:43:41 AM PDT 24
Peak memory 202204 kb
Host smart-fd08df98-090e-4cee-89ef-10c629e34205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013138975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3013138975
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1171884066
Short name T629
Test name
Test status
Simulation time 39218480018 ps
CPU time 47.1 seconds
Started Jul 02 09:36:30 AM PDT 24
Finished Jul 02 09:37:18 AM PDT 24
Peak memory 201684 kb
Host smart-56ef4314-c3d3-4c84-844b-d32ec23ddb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171884066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1171884066
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1327470951
Short name T117
Test name
Test status
Simulation time 5176964519 ps
CPU time 11.31 seconds
Started Jul 02 09:36:31 AM PDT 24
Finished Jul 02 09:36:43 AM PDT 24
Peak memory 201684 kb
Host smart-f5498831-9706-4644-b9d5-76d0b3d9e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327470951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1327470951
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4139808274
Short name T439
Test name
Test status
Simulation time 5915972433 ps
CPU time 14.6 seconds
Started Jul 02 09:36:19 AM PDT 24
Finished Jul 02 09:36:34 AM PDT 24
Peak memory 201712 kb
Host smart-a5250f65-29ab-4c63-b118-c426849b51c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139808274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4139808274
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1870285828
Short name T12
Test name
Test status
Simulation time 176695209689 ps
CPU time 214.31 seconds
Started Jul 02 09:36:23 AM PDT 24
Finished Jul 02 09:39:58 AM PDT 24
Peak memory 201908 kb
Host smart-13a27f92-9009-4e8a-8cc6-20803e82e62a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870285828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1870285828
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1074392347
Short name T23
Test name
Test status
Simulation time 103445818254 ps
CPU time 182.8 seconds
Started Jul 02 09:36:25 AM PDT 24
Finished Jul 02 09:39:28 AM PDT 24
Peak memory 218500 kb
Host smart-869ca5a4-6c2a-4a15-a750-0dc3f1174c5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074392347 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1074392347
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.201459213
Short name T569
Test name
Test status
Simulation time 315837382 ps
CPU time 0.97 seconds
Started Jul 02 09:31:31 AM PDT 24
Finished Jul 02 09:31:33 AM PDT 24
Peak memory 201664 kb
Host smart-0f58c95c-1c85-41b5-98fe-5c3f308c8844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201459213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.201459213
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.365678174
Short name T478
Test name
Test status
Simulation time 344679836504 ps
CPU time 390.19 seconds
Started Jul 02 09:31:25 AM PDT 24
Finished Jul 02 09:37:56 AM PDT 24
Peak memory 201904 kb
Host smart-3838764c-8fe9-4abc-91f8-adad06e156c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365678174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.365678174
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1995166468
Short name T166
Test name
Test status
Simulation time 523526156595 ps
CPU time 1162.9 seconds
Started Jul 02 09:31:29 AM PDT 24
Finished Jul 02 09:50:52 AM PDT 24
Peak memory 201912 kb
Host smart-b185dd5c-e154-4b96-bd8b-8991035caabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995166468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1995166468
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3524605159
Short name T603
Test name
Test status
Simulation time 165523642266 ps
CPU time 88.88 seconds
Started Jul 02 09:31:26 AM PDT 24
Finished Jul 02 09:32:56 AM PDT 24
Peak memory 201912 kb
Host smart-1e72499b-521b-41e7-a485-e700aa4d4a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524605159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3524605159
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3013686841
Short name T675
Test name
Test status
Simulation time 496686786567 ps
CPU time 527.93 seconds
Started Jul 02 09:31:27 AM PDT 24
Finished Jul 02 09:40:15 AM PDT 24
Peak memory 201808 kb
Host smart-fbff15c0-aae6-4989-ba31-83d66c31fa23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013686841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3013686841
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3091854578
Short name T260
Test name
Test status
Simulation time 169751118122 ps
CPU time 407.86 seconds
Started Jul 02 09:31:26 AM PDT 24
Finished Jul 02 09:38:14 AM PDT 24
Peak memory 201928 kb
Host smart-84f7d7e1-c6ac-4995-9f94-a3df4b2ec84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091854578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3091854578
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1809031333
Short name T431
Test name
Test status
Simulation time 492743914011 ps
CPU time 265.93 seconds
Started Jul 02 09:31:27 AM PDT 24
Finished Jul 02 09:35:53 AM PDT 24
Peak memory 201904 kb
Host smart-de1536ca-66eb-4005-b383-b7fbf800ca49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809031333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1809031333
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1295785717
Short name T272
Test name
Test status
Simulation time 356087977272 ps
CPU time 344.35 seconds
Started Jul 02 09:31:26 AM PDT 24
Finished Jul 02 09:37:11 AM PDT 24
Peak memory 201832 kb
Host smart-e6f4cc2a-f1e2-45e8-954d-c44fe0be1fd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295785717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1295785717
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2356024915
Short name T57
Test name
Test status
Simulation time 617404415873 ps
CPU time 1269.89 seconds
Started Jul 02 09:31:26 AM PDT 24
Finished Jul 02 09:52:36 AM PDT 24
Peak memory 201872 kb
Host smart-35635a90-0c4d-4df7-ab99-bddcf395abfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356024915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2356024915
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2956963114
Short name T233
Test name
Test status
Simulation time 130589849359 ps
CPU time 610.96 seconds
Started Jul 02 09:31:28 AM PDT 24
Finished Jul 02 09:41:40 AM PDT 24
Peak memory 202240 kb
Host smart-c5b0b41a-6bdc-4d84-b471-ef7f931e6294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956963114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2956963114
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.400304103
Short name T686
Test name
Test status
Simulation time 32698862554 ps
CPU time 35.53 seconds
Started Jul 02 09:31:29 AM PDT 24
Finished Jul 02 09:32:05 AM PDT 24
Peak memory 201712 kb
Host smart-87087723-29b8-4387-8be2-1b49890d73ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400304103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.400304103
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3415247340
Short name T584
Test name
Test status
Simulation time 4305867921 ps
CPU time 10.18 seconds
Started Jul 02 09:31:30 AM PDT 24
Finished Jul 02 09:31:41 AM PDT 24
Peak memory 201728 kb
Host smart-96d6de99-5335-46a7-ba0c-bdb8a64f7e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415247340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3415247340
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2408097446
Short name T96
Test name
Test status
Simulation time 7802227560 ps
CPU time 16.67 seconds
Started Jul 02 09:31:30 AM PDT 24
Finished Jul 02 09:31:47 AM PDT 24
Peak memory 218288 kb
Host smart-6868c96b-f9ff-48db-847d-47016e7902ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408097446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2408097446
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1047077725
Short name T622
Test name
Test status
Simulation time 6194869065 ps
CPU time 13.02 seconds
Started Jul 02 09:31:24 AM PDT 24
Finished Jul 02 09:31:37 AM PDT 24
Peak memory 201720 kb
Host smart-5694d091-a6e7-498e-99f9-99234dc6c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047077725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1047077725
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.601628032
Short name T763
Test name
Test status
Simulation time 6421368346 ps
CPU time 4.98 seconds
Started Jul 02 09:31:28 AM PDT 24
Finished Jul 02 09:31:34 AM PDT 24
Peak memory 201716 kb
Host smart-ad299ee2-92ad-4e5a-a523-8834b08602d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601628032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.601628032
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.664138700
Short name T252
Test name
Test status
Simulation time 1234205560047 ps
CPU time 143.19 seconds
Started Jul 02 09:31:29 AM PDT 24
Finished Jul 02 09:33:53 AM PDT 24
Peak memory 210532 kb
Host smart-fc07f939-fd8f-486e-a7a1-f644ec8f33d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664138700 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.664138700
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3446521084
Short name T604
Test name
Test status
Simulation time 370740249 ps
CPU time 0.81 seconds
Started Jul 02 09:36:33 AM PDT 24
Finished Jul 02 09:36:34 AM PDT 24
Peak memory 201588 kb
Host smart-7b9b4667-7cee-465d-abcb-4dc775f9cb02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446521084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3446521084
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1343525614
Short name T247
Test name
Test status
Simulation time 335916509793 ps
CPU time 200.12 seconds
Started Jul 02 09:36:30 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 201932 kb
Host smart-6fe3094f-93af-472b-a0a8-75a8f322e65f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343525614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1343525614
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1953020699
Short name T68
Test name
Test status
Simulation time 166044353809 ps
CPU time 94.75 seconds
Started Jul 02 09:36:29 AM PDT 24
Finished Jul 02 09:38:05 AM PDT 24
Peak memory 201912 kb
Host smart-d626cc4c-abf6-4390-9960-920f3ec4d6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953020699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1953020699
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.421745156
Short name T320
Test name
Test status
Simulation time 326289072780 ps
CPU time 186.19 seconds
Started Jul 02 09:36:26 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 201984 kb
Host smart-1f9feb22-7727-4a4d-8414-6fea4de8f1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421745156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.421745156
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2074609517
Short name T618
Test name
Test status
Simulation time 326314019669 ps
CPU time 186.56 seconds
Started Jul 02 09:36:25 AM PDT 24
Finished Jul 02 09:39:32 AM PDT 24
Peak memory 201852 kb
Host smart-311a9299-619a-42b0-b2d2-fe4baf87f265
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074609517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2074609517
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3389668055
Short name T436
Test name
Test status
Simulation time 167355844118 ps
CPU time 366.19 seconds
Started Jul 02 09:36:26 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 201964 kb
Host smart-d9220298-2c9e-43c8-9e08-311a87d9c56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389668055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3389668055
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2787089193
Short name T476
Test name
Test status
Simulation time 327849492424 ps
CPU time 699.84 seconds
Started Jul 02 09:36:27 AM PDT 24
Finished Jul 02 09:48:07 AM PDT 24
Peak memory 201888 kb
Host smart-b4b16def-adcb-4b55-abbc-ea78ce412f46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787089193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2787089193
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2500159007
Short name T299
Test name
Test status
Simulation time 471115719924 ps
CPU time 282.9 seconds
Started Jul 02 09:36:29 AM PDT 24
Finished Jul 02 09:41:12 AM PDT 24
Peak memory 201844 kb
Host smart-c309c353-6130-462d-92c8-be338d0bbd6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500159007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2500159007
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2150358952
Short name T391
Test name
Test status
Simulation time 611979655947 ps
CPU time 1290.03 seconds
Started Jul 02 09:36:30 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 201880 kb
Host smart-5177acd0-c1bc-4e63-a103-9b3b043e0cc5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150358952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2150358952
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3122030916
Short name T572
Test name
Test status
Simulation time 71602434378 ps
CPU time 239.55 seconds
Started Jul 02 09:36:30 AM PDT 24
Finished Jul 02 09:40:30 AM PDT 24
Peak memory 202272 kb
Host smart-11c664c1-49dd-45c9-9a00-051bf724efa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122030916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3122030916
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.31533546
Short name T5
Test name
Test status
Simulation time 25068523732 ps
CPU time 54.24 seconds
Started Jul 02 09:36:31 AM PDT 24
Finished Jul 02 09:37:26 AM PDT 24
Peak memory 201672 kb
Host smart-9daa11b6-463f-414b-81c5-924c672d8cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31533546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.31533546
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3665134916
Short name T109
Test name
Test status
Simulation time 3471983959 ps
CPU time 8.32 seconds
Started Jul 02 09:36:30 AM PDT 24
Finished Jul 02 09:36:39 AM PDT 24
Peak memory 201712 kb
Host smart-a8bfd81d-4dc2-4f17-9457-d134b030d860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665134916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3665134916
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1539328847
Short name T462
Test name
Test status
Simulation time 5671982968 ps
CPU time 14.03 seconds
Started Jul 02 09:36:26 AM PDT 24
Finished Jul 02 09:36:40 AM PDT 24
Peak memory 201716 kb
Host smart-3d0149c4-17d8-4748-bf99-20125caed676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539328847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1539328847
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3600402556
Short name T168
Test name
Test status
Simulation time 170252287514 ps
CPU time 48.38 seconds
Started Jul 02 09:36:29 AM PDT 24
Finished Jul 02 09:37:18 AM PDT 24
Peak memory 201920 kb
Host smart-19ea7574-d4cf-4937-b655-0b8262786d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600402556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3600402556
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2788674109
Short name T440
Test name
Test status
Simulation time 334191879 ps
CPU time 0.95 seconds
Started Jul 02 09:36:42 AM PDT 24
Finished Jul 02 09:36:43 AM PDT 24
Peak memory 201636 kb
Host smart-6da2eedb-c24a-4ca5-9b16-0db56846887b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788674109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2788674109
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.486271935
Short name T593
Test name
Test status
Simulation time 320931981532 ps
CPU time 762.94 seconds
Started Jul 02 09:36:39 AM PDT 24
Finished Jul 02 09:49:23 AM PDT 24
Peak memory 201908 kb
Host smart-4cf94f42-e0e2-417b-b5de-6705d2808153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486271935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.486271935
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1610939465
Short name T792
Test name
Test status
Simulation time 162209192370 ps
CPU time 94.8 seconds
Started Jul 02 09:36:39 AM PDT 24
Finished Jul 02 09:38:14 AM PDT 24
Peak memory 201892 kb
Host smart-38a818e7-67a5-4f3b-9e2e-5cad13b48c88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610939465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1610939465
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.984950593
Short name T764
Test name
Test status
Simulation time 165270165719 ps
CPU time 96.78 seconds
Started Jul 02 09:36:34 AM PDT 24
Finished Jul 02 09:38:11 AM PDT 24
Peak memory 201936 kb
Host smart-78b2f851-e27f-485e-8e93-25ccb51a6e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984950593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.984950593
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2960348608
Short name T121
Test name
Test status
Simulation time 490664983446 ps
CPU time 1106.55 seconds
Started Jul 02 09:36:40 AM PDT 24
Finished Jul 02 09:55:07 AM PDT 24
Peak memory 201884 kb
Host smart-28139006-f259-44c0-a661-1b00460b500f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960348608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2960348608
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1203531899
Short name T699
Test name
Test status
Simulation time 539171629752 ps
CPU time 315.6 seconds
Started Jul 02 09:36:38 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 201976 kb
Host smart-30e8f812-d85b-4942-bfbf-784ac18dcbfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203531899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1203531899
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2097255122
Short name T465
Test name
Test status
Simulation time 410165621361 ps
CPU time 892.07 seconds
Started Jul 02 09:36:38 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 202080 kb
Host smart-eaa4ee04-83bb-410a-9e38-dbfaecc0041a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097255122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2097255122
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2283692463
Short name T464
Test name
Test status
Simulation time 101001477697 ps
CPU time 513.13 seconds
Started Jul 02 09:36:41 AM PDT 24
Finished Jul 02 09:45:15 AM PDT 24
Peak memory 202212 kb
Host smart-4cffaf45-3824-4fbe-9496-40ba8f55f312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283692463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2283692463
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.555289510
Short name T626
Test name
Test status
Simulation time 43551647667 ps
CPU time 104.87 seconds
Started Jul 02 09:36:41 AM PDT 24
Finished Jul 02 09:38:26 AM PDT 24
Peak memory 201720 kb
Host smart-7032d736-aa62-4523-94f9-5f41ac03fb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555289510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.555289510
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1052249632
Short name T549
Test name
Test status
Simulation time 4738585185 ps
CPU time 11.6 seconds
Started Jul 02 09:36:42 AM PDT 24
Finished Jul 02 09:36:54 AM PDT 24
Peak memory 201704 kb
Host smart-83a448d4-799a-4b47-a033-182541c5237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052249632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1052249632
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1357765097
Short name T8
Test name
Test status
Simulation time 6129498399 ps
CPU time 6.74 seconds
Started Jul 02 09:36:34 AM PDT 24
Finished Jul 02 09:36:41 AM PDT 24
Peak memory 201712 kb
Host smart-8eb53857-40cd-466a-91ce-8daa2fb89371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357765097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1357765097
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3306189203
Short name T693
Test name
Test status
Simulation time 370078446471 ps
CPU time 212.18 seconds
Started Jul 02 09:36:44 AM PDT 24
Finished Jul 02 09:40:16 AM PDT 24
Peak memory 201896 kb
Host smart-1cc2297e-9804-491e-aa66-4981ceed1d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306189203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3306189203
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1935023961
Short name T24
Test name
Test status
Simulation time 89443101405 ps
CPU time 133.04 seconds
Started Jul 02 09:36:41 AM PDT 24
Finished Jul 02 09:38:55 AM PDT 24
Peak memory 211180 kb
Host smart-b6f12772-baa8-400b-a4f8-0acae42d802b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935023961 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1935023961
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.349714636
Short name T701
Test name
Test status
Simulation time 478025841 ps
CPU time 0.93 seconds
Started Jul 02 09:36:56 AM PDT 24
Finished Jul 02 09:36:58 AM PDT 24
Peak memory 201652 kb
Host smart-46c35ea3-1fd6-46cb-acdc-b465e31c55b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349714636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.349714636
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2724398811
Short name T716
Test name
Test status
Simulation time 164027556792 ps
CPU time 359.28 seconds
Started Jul 02 09:36:53 AM PDT 24
Finished Jul 02 09:42:53 AM PDT 24
Peak memory 201900 kb
Host smart-2c939e4a-0c94-473d-8752-73ad4af7004d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724398811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2724398811
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.287272819
Short name T298
Test name
Test status
Simulation time 171713091175 ps
CPU time 97.34 seconds
Started Jul 02 09:36:55 AM PDT 24
Finished Jul 02 09:38:32 AM PDT 24
Peak memory 201920 kb
Host smart-991c96ee-e555-40a0-83e5-cf5de0abed96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287272819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.287272819
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1726117931
Short name T757
Test name
Test status
Simulation time 321547056682 ps
CPU time 326.61 seconds
Started Jul 02 09:36:48 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 201916 kb
Host smart-c4b9dea6-6cd9-419e-b197-5b937674999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726117931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1726117931
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1439887013
Short name T652
Test name
Test status
Simulation time 160239391355 ps
CPU time 177.2 seconds
Started Jul 02 09:36:51 AM PDT 24
Finished Jul 02 09:39:48 AM PDT 24
Peak memory 201952 kb
Host smart-29f804f3-5c9f-422f-a736-5214cf9f3eeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439887013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1439887013
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.44923915
Short name T116
Test name
Test status
Simulation time 327509866830 ps
CPU time 770.69 seconds
Started Jul 02 09:36:46 AM PDT 24
Finished Jul 02 09:49:37 AM PDT 24
Peak memory 201912 kb
Host smart-c26dde5e-eb0f-44ab-acc7-a61027ab2d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44923915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.44923915
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2881935966
Short name T47
Test name
Test status
Simulation time 483620909855 ps
CPU time 252.8 seconds
Started Jul 02 09:36:45 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 201812 kb
Host smart-3085bad7-c626-408a-8d86-62bd2441a707
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881935966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2881935966
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1372695273
Short name T160
Test name
Test status
Simulation time 428460735798 ps
CPU time 298.63 seconds
Started Jul 02 09:36:50 AM PDT 24
Finished Jul 02 09:41:49 AM PDT 24
Peak memory 201896 kb
Host smart-7f111605-0151-40b9-9194-7044bf2d1eea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372695273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1372695273
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1210107414
Short name T492
Test name
Test status
Simulation time 397014205983 ps
CPU time 194.02 seconds
Started Jul 02 09:36:53 AM PDT 24
Finished Jul 02 09:40:08 AM PDT 24
Peak memory 201896 kb
Host smart-0fa51871-095e-4780-806f-405c773a13b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210107414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1210107414
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2061640479
Short name T570
Test name
Test status
Simulation time 108320643080 ps
CPU time 381.03 seconds
Started Jul 02 09:36:51 AM PDT 24
Finished Jul 02 09:43:13 AM PDT 24
Peak memory 202248 kb
Host smart-2929be30-a211-4ab5-89b5-e8dbe54beae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061640479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2061640479
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3375898785
Short name T582
Test name
Test status
Simulation time 34911454767 ps
CPU time 9.39 seconds
Started Jul 02 09:36:52 AM PDT 24
Finished Jul 02 09:37:01 AM PDT 24
Peak memory 201604 kb
Host smart-97a31d1c-9708-483e-aaf6-f29b2f8ac250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375898785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3375898785
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.988299475
Short name T694
Test name
Test status
Simulation time 3222538464 ps
CPU time 2.45 seconds
Started Jul 02 09:36:52 AM PDT 24
Finished Jul 02 09:36:55 AM PDT 24
Peak memory 201744 kb
Host smart-5e8bf190-7b7f-4224-8bfa-40b188c1add1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988299475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.988299475
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3720414827
Short name T415
Test name
Test status
Simulation time 6149163598 ps
CPU time 12.61 seconds
Started Jul 02 09:36:48 AM PDT 24
Finished Jul 02 09:37:01 AM PDT 24
Peak memory 201712 kb
Host smart-cf965c4f-c41e-43cf-b75d-9dd713421a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720414827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3720414827
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3991688978
Short name T313
Test name
Test status
Simulation time 897946352775 ps
CPU time 2009.53 seconds
Started Jul 02 09:36:56 AM PDT 24
Finished Jul 02 10:10:26 AM PDT 24
Peak memory 201852 kb
Host smart-d505d133-2b9f-4131-bc5f-c33f0de32111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991688978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3991688978
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3182569260
Short name T119
Test name
Test status
Simulation time 285047795884 ps
CPU time 127.22 seconds
Started Jul 02 09:36:53 AM PDT 24
Finished Jul 02 09:39:00 AM PDT 24
Peak memory 210196 kb
Host smart-606f9188-fcf2-4071-b409-6687aa8e9824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182569260 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3182569260
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1745334572
Short name T509
Test name
Test status
Simulation time 487268566 ps
CPU time 0.91 seconds
Started Jul 02 09:37:07 AM PDT 24
Finished Jul 02 09:37:08 AM PDT 24
Peak memory 201672 kb
Host smart-c613b213-f1dd-468b-8911-dd9da80ef9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745334572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1745334572
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4119395498
Short name T251
Test name
Test status
Simulation time 159903912083 ps
CPU time 95.89 seconds
Started Jul 02 09:37:05 AM PDT 24
Finished Jul 02 09:38:41 AM PDT 24
Peak memory 201876 kb
Host smart-ccb24728-dfd9-4056-8fa4-e7f08a95e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119395498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4119395498
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.621804672
Short name T293
Test name
Test status
Simulation time 165656946189 ps
CPU time 204.07 seconds
Started Jul 02 09:36:59 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 201884 kb
Host smart-9b7ab2a3-b63e-4438-b772-5265837894a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621804672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.621804672
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.985240742
Short name T473
Test name
Test status
Simulation time 323372632996 ps
CPU time 187.98 seconds
Started Jul 02 09:37:02 AM PDT 24
Finished Jul 02 09:40:11 AM PDT 24
Peak memory 201868 kb
Host smart-17e4c296-fd05-4a41-93f8-17e9bd475aae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=985240742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.985240742
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1247535947
Short name T175
Test name
Test status
Simulation time 328127288024 ps
CPU time 713.34 seconds
Started Jul 02 09:36:57 AM PDT 24
Finished Jul 02 09:48:50 AM PDT 24
Peak memory 202000 kb
Host smart-65016525-b824-4878-99e6-57f30577ebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247535947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1247535947
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1543439040
Short name T651
Test name
Test status
Simulation time 489368003137 ps
CPU time 282.87 seconds
Started Jul 02 09:36:58 AM PDT 24
Finished Jul 02 09:41:41 AM PDT 24
Peak memory 201884 kb
Host smart-08df43fd-0788-4390-afb8-970276f9dec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543439040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1543439040
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3618479788
Short name T344
Test name
Test status
Simulation time 248310045536 ps
CPU time 577.8 seconds
Started Jul 02 09:36:59 AM PDT 24
Finished Jul 02 09:46:37 AM PDT 24
Peak memory 201940 kb
Host smart-90b4f1f2-80dc-49fa-8387-0e7290c74e3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618479788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3618479788
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.625404733
Short name T552
Test name
Test status
Simulation time 201736726798 ps
CPU time 464.96 seconds
Started Jul 02 09:36:59 AM PDT 24
Finished Jul 02 09:44:45 AM PDT 24
Peak memory 201868 kb
Host smart-33224bb4-8f22-40a8-a266-bde0ca983457
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625404733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.625404733
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2697316881
Short name T70
Test name
Test status
Simulation time 130320054180 ps
CPU time 418.87 seconds
Started Jul 02 09:37:05 AM PDT 24
Finished Jul 02 09:44:05 AM PDT 24
Peak memory 202212 kb
Host smart-1d6f2cba-4a26-4195-844c-f979ebe99470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697316881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2697316881
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2342576500
Short name T590
Test name
Test status
Simulation time 28412616071 ps
CPU time 69.82 seconds
Started Jul 02 09:37:07 AM PDT 24
Finished Jul 02 09:38:17 AM PDT 24
Peak memory 201716 kb
Host smart-95186490-593f-4c4c-8c45-c27271ae932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342576500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2342576500
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2960138175
Short name T595
Test name
Test status
Simulation time 4733309052 ps
CPU time 2.95 seconds
Started Jul 02 09:37:07 AM PDT 24
Finished Jul 02 09:37:11 AM PDT 24
Peak memory 201720 kb
Host smart-e09341f6-cc96-4917-8148-d6f45578b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960138175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2960138175
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3877912784
Short name T581
Test name
Test status
Simulation time 5653753263 ps
CPU time 12.89 seconds
Started Jul 02 09:36:56 AM PDT 24
Finished Jul 02 09:37:09 AM PDT 24
Peak memory 201704 kb
Host smart-45da2edb-6920-46e6-892c-d85be5ab0d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877912784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3877912784
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.4276471645
Short name T118
Test name
Test status
Simulation time 3649700102721 ps
CPU time 726.09 seconds
Started Jul 02 09:37:05 AM PDT 24
Finished Jul 02 09:49:11 AM PDT 24
Peak memory 218500 kb
Host smart-2a6060c9-4d55-4fd2-8474-86ecef7f6419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276471645 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.4276471645
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1049423489
Short name T469
Test name
Test status
Simulation time 556059685 ps
CPU time 0.69 seconds
Started Jul 02 09:37:15 AM PDT 24
Finished Jul 02 09:37:16 AM PDT 24
Peak memory 201648 kb
Host smart-be3f2425-5df2-473d-81f4-3f3438658ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049423489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1049423489
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3209263288
Short name T203
Test name
Test status
Simulation time 497791128323 ps
CPU time 176 seconds
Started Jul 02 09:37:14 AM PDT 24
Finished Jul 02 09:40:10 AM PDT 24
Peak memory 201972 kb
Host smart-ac2e615e-58eb-44dc-853a-1b1e39455cdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209263288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3209263288
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1055509012
Short name T127
Test name
Test status
Simulation time 161861051262 ps
CPU time 360.66 seconds
Started Jul 02 09:37:06 AM PDT 24
Finished Jul 02 09:43:07 AM PDT 24
Peak memory 201972 kb
Host smart-27b72979-a253-49c6-accf-61e10685c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055509012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1055509012
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.374340387
Short name T765
Test name
Test status
Simulation time 167334683720 ps
CPU time 179.6 seconds
Started Jul 02 09:37:11 AM PDT 24
Finished Jul 02 09:40:10 AM PDT 24
Peak memory 201896 kb
Host smart-8acbed2c-20ab-4d61-aef8-4aec19004528
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=374340387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.374340387
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2045476451
Short name T707
Test name
Test status
Simulation time 493882396635 ps
CPU time 1052.94 seconds
Started Jul 02 09:37:07 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 201932 kb
Host smart-81350272-b202-4ceb-bfb9-3a13c19bdb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045476451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2045476451
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3687540628
Short name T550
Test name
Test status
Simulation time 323791480844 ps
CPU time 55.82 seconds
Started Jul 02 09:37:07 AM PDT 24
Finished Jul 02 09:38:03 AM PDT 24
Peak memory 201908 kb
Host smart-811aa9c4-7456-4241-ad16-7fc39ef5af31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687540628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3687540628
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.159259728
Short name T717
Test name
Test status
Simulation time 375465733248 ps
CPU time 139.64 seconds
Started Jul 02 09:37:13 AM PDT 24
Finished Jul 02 09:39:33 AM PDT 24
Peak memory 201936 kb
Host smart-61ef8fb0-ed0e-4e62-86e5-471f1bd689e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159259728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.159259728
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.419010558
Short name T362
Test name
Test status
Simulation time 92875155084 ps
CPU time 339.22 seconds
Started Jul 02 09:37:14 AM PDT 24
Finished Jul 02 09:42:54 AM PDT 24
Peak memory 202252 kb
Host smart-969110c0-ccdc-4ac2-aa2c-5f5f577ab5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419010558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.419010558
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3002629522
Short name T191
Test name
Test status
Simulation time 44415692387 ps
CPU time 18.12 seconds
Started Jul 02 09:37:12 AM PDT 24
Finished Jul 02 09:37:31 AM PDT 24
Peak memory 201640 kb
Host smart-bc79d5ee-0b02-43e6-8e93-41ea0976df9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002629522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3002629522
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2855564538
Short name T688
Test name
Test status
Simulation time 4812560530 ps
CPU time 6.23 seconds
Started Jul 02 09:37:13 AM PDT 24
Finished Jul 02 09:37:19 AM PDT 24
Peak memory 201688 kb
Host smart-6a41fac5-e410-4aad-b15c-835052a40d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855564538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2855564538
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.806614319
Short name T770
Test name
Test status
Simulation time 5992745589 ps
CPU time 2.32 seconds
Started Jul 02 09:37:05 AM PDT 24
Finished Jul 02 09:37:07 AM PDT 24
Peak memory 201692 kb
Host smart-6dace3c2-cf8a-44c9-8c94-e900c7ddf1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806614319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.806614319
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1295161500
Short name T224
Test name
Test status
Simulation time 253344668382 ps
CPU time 385.09 seconds
Started Jul 02 09:37:17 AM PDT 24
Finished Jul 02 09:43:42 AM PDT 24
Peak memory 210416 kb
Host smart-e24c2136-bc6c-40a3-ba8d-ae61d6f645c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295161500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1295161500
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1522357129
Short name T55
Test name
Test status
Simulation time 151374277382 ps
CPU time 161.58 seconds
Started Jul 02 09:37:14 AM PDT 24
Finished Jul 02 09:39:55 AM PDT 24
Peak memory 210608 kb
Host smart-5d0743d9-ca07-4b06-bc71-2f5743c2af57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522357129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1522357129
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2742451757
Short name T399
Test name
Test status
Simulation time 386503753 ps
CPU time 0.75 seconds
Started Jul 02 09:37:22 AM PDT 24
Finished Jul 02 09:37:23 AM PDT 24
Peak memory 201652 kb
Host smart-5716985b-8f92-4033-9d58-5c59c722fff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742451757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2742451757
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.4276228187
Short name T654
Test name
Test status
Simulation time 191246519120 ps
CPU time 95.99 seconds
Started Jul 02 09:37:22 AM PDT 24
Finished Jul 02 09:38:59 AM PDT 24
Peak memory 201956 kb
Host smart-f89bab96-97ca-4c39-9859-5e719a56583e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276228187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.4276228187
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2918013446
Short name T521
Test name
Test status
Simulation time 168668161139 ps
CPU time 209.73 seconds
Started Jul 02 09:37:20 AM PDT 24
Finished Jul 02 09:40:50 AM PDT 24
Peak memory 202116 kb
Host smart-31b36d34-b0a9-46b8-a4b1-c688a2646e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918013446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2918013446
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1563700473
Short name T295
Test name
Test status
Simulation time 164808062240 ps
CPU time 98.3 seconds
Started Jul 02 09:37:23 AM PDT 24
Finished Jul 02 09:39:01 AM PDT 24
Peak memory 201944 kb
Host smart-7da16719-b77c-4ed8-90b6-0b36e3182bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563700473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1563700473
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3809274711
Short name T429
Test name
Test status
Simulation time 496600698241 ps
CPU time 1113.41 seconds
Started Jul 02 09:37:22 AM PDT 24
Finished Jul 02 09:55:56 AM PDT 24
Peak memory 201872 kb
Host smart-2b2dabd5-2feb-4b9d-8d40-cb086d397ac3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809274711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3809274711
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3290917089
Short name T532
Test name
Test status
Simulation time 493944651229 ps
CPU time 594.68 seconds
Started Jul 02 09:37:17 AM PDT 24
Finished Jul 02 09:47:12 AM PDT 24
Peak memory 201996 kb
Host smart-6c16c6e6-1cd6-4704-8653-a3a38b6210f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290917089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3290917089
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2734739952
Short name T182
Test name
Test status
Simulation time 494748663058 ps
CPU time 288.53 seconds
Started Jul 02 09:37:20 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 201860 kb
Host smart-973a65ac-3fc7-45f5-93e1-28f3b6b97126
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734739952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2734739952
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2686592789
Short name T755
Test name
Test status
Simulation time 192062864050 ps
CPU time 395.03 seconds
Started Jul 02 09:37:20 AM PDT 24
Finished Jul 02 09:43:55 AM PDT 24
Peak memory 201988 kb
Host smart-fb1bb6f9-1ec7-49eb-85f3-a4fa998a5b72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686592789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2686592789
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2539442499
Short name T596
Test name
Test status
Simulation time 195775399964 ps
CPU time 413.11 seconds
Started Jul 02 09:37:19 AM PDT 24
Finished Jul 02 09:44:13 AM PDT 24
Peak memory 201820 kb
Host smart-95d58d0e-ab29-4d0f-b55e-483a6645f148
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539442499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2539442499
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2599646154
Short name T600
Test name
Test status
Simulation time 61607254914 ps
CPU time 229.27 seconds
Started Jul 02 09:37:27 AM PDT 24
Finished Jul 02 09:41:16 AM PDT 24
Peak memory 202224 kb
Host smart-f3ae72e1-1e80-455a-a4e4-4d1f4e1c7c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599646154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2599646154
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.4195837889
Short name T540
Test name
Test status
Simulation time 35400344448 ps
CPU time 21.59 seconds
Started Jul 02 09:37:20 AM PDT 24
Finished Jul 02 09:37:42 AM PDT 24
Peak memory 201632 kb
Host smart-d79fa789-4842-49ce-bd97-e0bb722eed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195837889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.4195837889
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4105412834
Short name T712
Test name
Test status
Simulation time 3196539189 ps
CPU time 2.48 seconds
Started Jul 02 09:37:27 AM PDT 24
Finished Jul 02 09:37:30 AM PDT 24
Peak memory 201728 kb
Host smart-c12fffb7-dcde-4c2f-9749-8126e4ebe4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105412834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4105412834
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3585234009
Short name T414
Test name
Test status
Simulation time 5744743186 ps
CPU time 3.62 seconds
Started Jul 02 09:37:17 AM PDT 24
Finished Jul 02 09:37:21 AM PDT 24
Peak memory 201724 kb
Host smart-e8c1b34c-5b3b-44b6-ad49-ae62ad4c34a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585234009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3585234009
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3767437152
Short name T308
Test name
Test status
Simulation time 2203814752084 ps
CPU time 4665.2 seconds
Started Jul 02 09:37:23 AM PDT 24
Finished Jul 02 10:55:09 AM PDT 24
Peak memory 202272 kb
Host smart-07dace96-9b51-41eb-9c3b-00a735ad23ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767437152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3767437152
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2171980046
Short name T387
Test name
Test status
Simulation time 456164162 ps
CPU time 0.75 seconds
Started Jul 02 09:37:34 AM PDT 24
Finished Jul 02 09:37:35 AM PDT 24
Peak memory 201640 kb
Host smart-71d687d8-0a8a-423c-8e84-b68456da0639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171980046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2171980046
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2307851411
Short name T422
Test name
Test status
Simulation time 164734965105 ps
CPU time 200.22 seconds
Started Jul 02 09:37:29 AM PDT 24
Finished Jul 02 09:40:50 AM PDT 24
Peak memory 201880 kb
Host smart-28430feb-27c4-4bcf-a403-3690f3f20195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307851411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2307851411
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2758550737
Short name T615
Test name
Test status
Simulation time 496268012635 ps
CPU time 1170.44 seconds
Started Jul 02 09:37:29 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 201880 kb
Host smart-53a63053-b38c-48f8-a3b6-85740c3fd5af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758550737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2758550737
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2809226093
Short name T483
Test name
Test status
Simulation time 484738518076 ps
CPU time 380.25 seconds
Started Jul 02 09:37:28 AM PDT 24
Finished Jul 02 09:43:49 AM PDT 24
Peak memory 201932 kb
Host smart-f8699a5a-276a-45d4-8ea3-777a756b2567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809226093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2809226093
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2189451810
Short name T714
Test name
Test status
Simulation time 331311689797 ps
CPU time 44.99 seconds
Started Jul 02 09:37:27 AM PDT 24
Finished Jul 02 09:38:13 AM PDT 24
Peak memory 201888 kb
Host smart-7d6313b5-e8c0-4707-924b-ce1e1ed29fec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189451810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2189451810
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.682083055
Short name T187
Test name
Test status
Simulation time 351980437433 ps
CPU time 141.49 seconds
Started Jul 02 09:37:29 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 201932 kb
Host smart-b8fb7a8b-884c-4f42-926d-aec0fd9bc5b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682083055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.682083055
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.984680852
Short name T631
Test name
Test status
Simulation time 406648009303 ps
CPU time 507.24 seconds
Started Jul 02 09:37:28 AM PDT 24
Finished Jul 02 09:45:56 AM PDT 24
Peak memory 201820 kb
Host smart-66455657-1411-4934-92bc-ce378bd201f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984680852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.984680852
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.172514093
Short name T784
Test name
Test status
Simulation time 93347403521 ps
CPU time 299.15 seconds
Started Jul 02 09:37:35 AM PDT 24
Finished Jul 02 09:42:34 AM PDT 24
Peak memory 202252 kb
Host smart-93fdf4d7-36f0-4bef-a363-7db88c4d8e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172514093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.172514093
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2992494606
Short name T576
Test name
Test status
Simulation time 24870610075 ps
CPU time 14.17 seconds
Started Jul 02 09:37:31 AM PDT 24
Finished Jul 02 09:37:46 AM PDT 24
Peak memory 201644 kb
Host smart-87c2192a-0a8b-48e7-800c-21778971a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992494606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2992494606
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2704052835
Short name T526
Test name
Test status
Simulation time 3668252896 ps
CPU time 2.91 seconds
Started Jul 02 09:37:31 AM PDT 24
Finished Jul 02 09:37:34 AM PDT 24
Peak memory 201700 kb
Host smart-5d3cf0c3-d1b1-4a59-9940-8484535a28b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704052835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2704052835
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1173438358
Short name T672
Test name
Test status
Simulation time 5793267115 ps
CPU time 4.03 seconds
Started Jul 02 09:37:22 AM PDT 24
Finished Jul 02 09:37:27 AM PDT 24
Peak memory 201668 kb
Host smart-3ca5988a-8820-48b1-b7a5-8cbc83f9f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173438358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1173438358
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1616654453
Short name T339
Test name
Test status
Simulation time 627795876108 ps
CPU time 1858.55 seconds
Started Jul 02 09:37:36 AM PDT 24
Finished Jul 02 10:08:36 AM PDT 24
Peak memory 202200 kb
Host smart-4976fea4-08d1-4ce3-885d-132d2b13b389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616654453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1616654453
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1885142492
Short name T340
Test name
Test status
Simulation time 392767947649 ps
CPU time 263.73 seconds
Started Jul 02 09:37:34 AM PDT 24
Finished Jul 02 09:41:58 AM PDT 24
Peak memory 210544 kb
Host smart-9e9a1995-59d4-4cd5-b973-4553066d2760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885142492 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1885142492
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1810793084
Short name T409
Test name
Test status
Simulation time 356088196 ps
CPU time 1.05 seconds
Started Jul 02 09:37:44 AM PDT 24
Finished Jul 02 09:37:45 AM PDT 24
Peak memory 201656 kb
Host smart-925df4aa-07ca-4df4-989d-30e49e36c23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810793084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1810793084
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1006963992
Short name T46
Test name
Test status
Simulation time 419174745892 ps
CPU time 901.52 seconds
Started Jul 02 09:37:39 AM PDT 24
Finished Jul 02 09:52:42 AM PDT 24
Peak memory 201984 kb
Host smart-ed5345d6-cb64-4634-9bbe-8bf4add50d90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006963992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1006963992
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2797666900
Short name T580
Test name
Test status
Simulation time 170157104177 ps
CPU time 64.69 seconds
Started Jul 02 09:37:40 AM PDT 24
Finished Jul 02 09:38:45 AM PDT 24
Peak memory 201936 kb
Host smart-87dc6bbe-4a6b-4173-8a82-e84a17c09d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797666900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2797666900
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2271723682
Short name T266
Test name
Test status
Simulation time 333781871662 ps
CPU time 709.61 seconds
Started Jul 02 09:37:39 AM PDT 24
Finished Jul 02 09:49:30 AM PDT 24
Peak memory 201880 kb
Host smart-cd58be7a-0ffa-45d4-a3c9-aefb71d569c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271723682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2271723682
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1098086354
Short name T218
Test name
Test status
Simulation time 329087091165 ps
CPU time 394.45 seconds
Started Jul 02 09:37:40 AM PDT 24
Finished Jul 02 09:44:15 AM PDT 24
Peak memory 201812 kb
Host smart-9b491c87-2402-4675-8aba-7dabe46c02ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098086354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1098086354
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1343445193
Short name T679
Test name
Test status
Simulation time 165338882119 ps
CPU time 90.26 seconds
Started Jul 02 09:37:41 AM PDT 24
Finished Jul 02 09:39:12 AM PDT 24
Peak memory 201808 kb
Host smart-80b8b2b2-227b-4498-ae56-fb02948113f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343445193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1343445193
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.241038468
Short name T769
Test name
Test status
Simulation time 253761256991 ps
CPU time 173.42 seconds
Started Jul 02 09:37:39 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 201972 kb
Host smart-03950776-c1ee-47c2-baa2-c1a6ba7ede86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241038468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.241038468
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.395480985
Short name T50
Test name
Test status
Simulation time 587309148353 ps
CPU time 688.15 seconds
Started Jul 02 09:37:41 AM PDT 24
Finished Jul 02 09:49:10 AM PDT 24
Peak memory 201952 kb
Host smart-c6f3ae12-4b07-48f7-9a62-60747d76bcc2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395480985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.395480985
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1901512334
Short name T237
Test name
Test status
Simulation time 69910979044 ps
CPU time 276.45 seconds
Started Jul 02 09:37:44 AM PDT 24
Finished Jul 02 09:42:21 AM PDT 24
Peak memory 202200 kb
Host smart-adb2aa95-8a5d-46a9-94c8-9f2379203b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901512334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1901512334
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.437514324
Short name T215
Test name
Test status
Simulation time 31500216485 ps
CPU time 7.61 seconds
Started Jul 02 09:37:46 AM PDT 24
Finished Jul 02 09:37:54 AM PDT 24
Peak memory 201720 kb
Host smart-e934872e-a921-4ce5-93b2-702e4b1d0f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437514324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.437514324
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.851825952
Short name T527
Test name
Test status
Simulation time 3220862999 ps
CPU time 7.57 seconds
Started Jul 02 09:37:45 AM PDT 24
Finished Jul 02 09:37:53 AM PDT 24
Peak memory 201680 kb
Host smart-95cda037-a437-4157-95f5-5cba95c6e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851825952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.851825952
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.399071786
Short name T500
Test name
Test status
Simulation time 5528798045 ps
CPU time 13.65 seconds
Started Jul 02 09:37:41 AM PDT 24
Finished Jul 02 09:37:55 AM PDT 24
Peak memory 201640 kb
Host smart-f89df142-ec77-4ea3-b2cf-8d930a84fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399071786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.399071786
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3961831578
Short name T591
Test name
Test status
Simulation time 659387147518 ps
CPU time 1889.44 seconds
Started Jul 02 09:37:45 AM PDT 24
Finished Jul 02 10:09:15 AM PDT 24
Peak memory 210404 kb
Host smart-25d709c3-0db0-4bf2-8632-b4f3c0a7802f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961831578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3961831578
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1936126565
Short name T307
Test name
Test status
Simulation time 166802621372 ps
CPU time 220.17 seconds
Started Jul 02 09:37:47 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 210628 kb
Host smart-30e1822c-0ef4-4eff-aebb-0d714417ca66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936126565 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1936126565
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1143707984
Short name T453
Test name
Test status
Simulation time 523181974 ps
CPU time 0.91 seconds
Started Jul 02 09:37:50 AM PDT 24
Finished Jul 02 09:37:51 AM PDT 24
Peak memory 201672 kb
Host smart-f17c174e-5389-4b37-a8b6-dc03901aeeac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143707984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1143707984
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.727628448
Short name T768
Test name
Test status
Simulation time 171666559478 ps
CPU time 266.21 seconds
Started Jul 02 09:37:48 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 201848 kb
Host smart-5fcff034-5d39-4b7c-9277-f7621ba8cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727628448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.727628448
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2285771239
Short name T329
Test name
Test status
Simulation time 496875318029 ps
CPU time 1170.81 seconds
Started Jul 02 09:37:47 AM PDT 24
Finished Jul 02 09:57:18 AM PDT 24
Peak memory 201904 kb
Host smart-72418557-6ced-4044-8a6b-3aaeb3a0ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285771239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2285771239
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.202977943
Short name T508
Test name
Test status
Simulation time 508371208861 ps
CPU time 284.45 seconds
Started Jul 02 09:37:46 AM PDT 24
Finished Jul 02 09:42:32 AM PDT 24
Peak memory 201884 kb
Host smart-cec9bc9f-841f-4fd0-8213-fe4816f423d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=202977943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.202977943
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.707330518
Short name T100
Test name
Test status
Simulation time 160608792458 ps
CPU time 46.52 seconds
Started Jul 02 09:37:44 AM PDT 24
Finished Jul 02 09:38:31 AM PDT 24
Peak memory 201880 kb
Host smart-af6133c0-f274-4745-aa57-5459e503c769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707330518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.707330518
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2734274833
Short name T43
Test name
Test status
Simulation time 164774673860 ps
CPU time 27.76 seconds
Started Jul 02 09:37:46 AM PDT 24
Finished Jul 02 09:38:14 AM PDT 24
Peak memory 201856 kb
Host smart-a201a4b6-44d8-4330-9327-f3912f41b577
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734274833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2734274833
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3177904013
Short name T557
Test name
Test status
Simulation time 175618953087 ps
CPU time 363.57 seconds
Started Jul 02 09:37:48 AM PDT 24
Finished Jul 02 09:43:52 AM PDT 24
Peak memory 201924 kb
Host smart-6b85e20a-231d-445a-8626-3eb911562748
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177904013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3177904013
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.102174658
Short name T103
Test name
Test status
Simulation time 608990343698 ps
CPU time 373.13 seconds
Started Jul 02 09:37:47 AM PDT 24
Finished Jul 02 09:44:01 AM PDT 24
Peak memory 202128 kb
Host smart-da665908-b272-400e-bbc7-a8c1340a89a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102174658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.102174658
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.84519598
Short name T573
Test name
Test status
Simulation time 123585459349 ps
CPU time 618.46 seconds
Started Jul 02 09:37:50 AM PDT 24
Finished Jul 02 09:48:10 AM PDT 24
Peak memory 202204 kb
Host smart-dbdc2bd0-d716-4930-8a73-377c71cb4a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84519598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.84519598
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2593066236
Short name T402
Test name
Test status
Simulation time 40627642147 ps
CPU time 45.66 seconds
Started Jul 02 09:37:51 AM PDT 24
Finished Jul 02 09:38:37 AM PDT 24
Peak memory 201608 kb
Host smart-618fe17b-4073-47ec-8584-ebcc67bba48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593066236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2593066236
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1286360888
Short name T708
Test name
Test status
Simulation time 2803072861 ps
CPU time 7.48 seconds
Started Jul 02 09:37:46 AM PDT 24
Finished Jul 02 09:37:54 AM PDT 24
Peak memory 201712 kb
Host smart-1bc7cfd0-e0ad-48eb-94dc-085973fa7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286360888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1286360888
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1300988165
Short name T497
Test name
Test status
Simulation time 5668843564 ps
CPU time 2.41 seconds
Started Jul 02 09:37:44 AM PDT 24
Finished Jul 02 09:37:47 AM PDT 24
Peak memory 201696 kb
Host smart-5514dbb5-65f0-4ae0-8f3e-5173eb526ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300988165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1300988165
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3083327147
Short name T285
Test name
Test status
Simulation time 217945676139 ps
CPU time 86.34 seconds
Started Jul 02 09:37:50 AM PDT 24
Finished Jul 02 09:39:17 AM PDT 24
Peak memory 201892 kb
Host smart-25db0d85-06f3-45f2-a3d2-3c0050060e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083327147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3083327147
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.636174832
Short name T788
Test name
Test status
Simulation time 520370603 ps
CPU time 1.83 seconds
Started Jul 02 09:37:58 AM PDT 24
Finished Jul 02 09:38:00 AM PDT 24
Peak memory 201656 kb
Host smart-ee817959-e896-4cde-ad70-e1631e604b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636174832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.636174832
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2552166721
Short name T779
Test name
Test status
Simulation time 161259892512 ps
CPU time 165.05 seconds
Started Jul 02 09:37:58 AM PDT 24
Finished Jul 02 09:40:43 AM PDT 24
Peak memory 201828 kb
Host smart-d148acd0-7f1b-4a31-940f-c93f4f25d566
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552166721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2552166721
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2537385439
Short name T309
Test name
Test status
Simulation time 202529141653 ps
CPU time 415.91 seconds
Started Jul 02 09:37:58 AM PDT 24
Finished Jul 02 09:44:54 AM PDT 24
Peak memory 201904 kb
Host smart-7948de59-be68-4971-9c7c-c72303f15c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537385439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2537385439
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3280544347
Short name T349
Test name
Test status
Simulation time 327321570680 ps
CPU time 283.46 seconds
Started Jul 02 09:37:51 AM PDT 24
Finished Jul 02 09:42:35 AM PDT 24
Peak memory 201892 kb
Host smart-3ab1c2ef-cc1d-45b1-9181-19b40dde176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280544347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3280544347
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3475529069
Short name T728
Test name
Test status
Simulation time 326339372931 ps
CPU time 368.82 seconds
Started Jul 02 09:37:55 AM PDT 24
Finished Jul 02 09:44:04 AM PDT 24
Peak memory 201900 kb
Host smart-4382cd5f-c8cb-48c4-9fb9-d783a697f56f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475529069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3475529069
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2530142423
Short name T761
Test name
Test status
Simulation time 165979736984 ps
CPU time 191.88 seconds
Started Jul 02 09:37:52 AM PDT 24
Finished Jul 02 09:41:04 AM PDT 24
Peak memory 201900 kb
Host smart-3a0654e6-a85f-460d-9fa3-2926a9af3fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530142423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2530142423
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3311618085
Short name T767
Test name
Test status
Simulation time 489011497973 ps
CPU time 897.13 seconds
Started Jul 02 09:37:50 AM PDT 24
Finished Jul 02 09:52:48 AM PDT 24
Peak memory 201932 kb
Host smart-9d8c6440-0ecb-4a2b-8c28-3cb1f5d14d43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311618085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3311618085
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4184200905
Short name T585
Test name
Test status
Simulation time 167789720120 ps
CPU time 373.11 seconds
Started Jul 02 09:37:54 AM PDT 24
Finished Jul 02 09:44:08 AM PDT 24
Peak memory 201920 kb
Host smart-4caa56f0-a97d-4812-ad4c-7120b0ad3fb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184200905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4184200905
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3512758024
Short name T664
Test name
Test status
Simulation time 601810062510 ps
CPU time 338.55 seconds
Started Jul 02 09:37:55 AM PDT 24
Finished Jul 02 09:43:34 AM PDT 24
Peak memory 201864 kb
Host smart-410f9cd1-45d0-498a-bcc7-30845569cfe3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512758024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3512758024
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3218734874
Short name T227
Test name
Test status
Simulation time 88937678201 ps
CPU time 332.44 seconds
Started Jul 02 09:37:59 AM PDT 24
Finished Jul 02 09:43:31 AM PDT 24
Peak memory 202236 kb
Host smart-50b6a2df-c80f-4ec4-90f2-13b1eb1a94ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218734874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3218734874
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3099890140
Short name T559
Test name
Test status
Simulation time 34667046184 ps
CPU time 20.21 seconds
Started Jul 02 09:37:59 AM PDT 24
Finished Jul 02 09:38:20 AM PDT 24
Peak memory 201716 kb
Host smart-a119bc26-18ae-4563-91b5-4c3bd5591390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099890140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3099890140
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1195460271
Short name T601
Test name
Test status
Simulation time 4117559711 ps
CPU time 2.34 seconds
Started Jul 02 09:37:59 AM PDT 24
Finished Jul 02 09:38:02 AM PDT 24
Peak memory 201640 kb
Host smart-def64da3-655b-44d5-aa4d-0b0057f01d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195460271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1195460271
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3671602802
Short name T551
Test name
Test status
Simulation time 5872020873 ps
CPU time 14.92 seconds
Started Jul 02 09:37:51 AM PDT 24
Finished Jul 02 09:38:06 AM PDT 24
Peak memory 201728 kb
Host smart-5113dbe0-d1ef-4d69-85f5-b80a4f51ef27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671602802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3671602802
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2497838598
Short name T352
Test name
Test status
Simulation time 170407647821 ps
CPU time 100.76 seconds
Started Jul 02 09:38:06 AM PDT 24
Finished Jul 02 09:39:47 AM PDT 24
Peak memory 201860 kb
Host smart-2853c40f-6ec3-4c67-aed3-fa6c39f1c5a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497838598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2497838598
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1203823581
Short name T363
Test name
Test status
Simulation time 41267730742 ps
CPU time 105.28 seconds
Started Jul 02 09:38:06 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 210564 kb
Host smart-d4b1fcd2-923a-4ec2-9437-5e0160d46bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203823581 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1203823581
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1551277706
Short name T705
Test name
Test status
Simulation time 327990287 ps
CPU time 0.75 seconds
Started Jul 02 09:31:37 AM PDT 24
Finished Jul 02 09:31:39 AM PDT 24
Peak memory 201636 kb
Host smart-f6caa76f-42ab-4f93-ab91-c942cb6960b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551277706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1551277706
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3799478106
Short name T420
Test name
Test status
Simulation time 494685750318 ps
CPU time 185.37 seconds
Started Jul 02 09:31:36 AM PDT 24
Finished Jul 02 09:34:43 AM PDT 24
Peak memory 201896 kb
Host smart-dff715f6-238f-4652-a647-5d3061833454
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799478106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3799478106
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.412203396
Short name T296
Test name
Test status
Simulation time 487906840775 ps
CPU time 344.59 seconds
Started Jul 02 09:31:34 AM PDT 24
Finished Jul 02 09:37:19 AM PDT 24
Peak memory 201900 kb
Host smart-0cdefa7f-1676-408a-b94f-7b7fa0607459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412203396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.412203396
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3266159771
Short name T608
Test name
Test status
Simulation time 168770266446 ps
CPU time 99.11 seconds
Started Jul 02 09:31:34 AM PDT 24
Finished Jul 02 09:33:14 AM PDT 24
Peak memory 201772 kb
Host smart-4704cfd3-3b29-4bc1-bfba-b4bc178cec69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266159771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3266159771
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.310693681
Short name T577
Test name
Test status
Simulation time 333441335686 ps
CPU time 493.32 seconds
Started Jul 02 09:31:32 AM PDT 24
Finished Jul 02 09:39:46 AM PDT 24
Peak memory 201956 kb
Host smart-2f2a0d27-3c98-433e-b6ce-0317973e1fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310693681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.310693681
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2886934003
Short name T181
Test name
Test status
Simulation time 317725219366 ps
CPU time 105.51 seconds
Started Jul 02 09:31:32 AM PDT 24
Finished Jul 02 09:33:18 AM PDT 24
Peak memory 201820 kb
Host smart-bf853c54-e99a-4bd1-9c45-d20823ab5df1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886934003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2886934003
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1234555841
Short name T481
Test name
Test status
Simulation time 521087256477 ps
CPU time 1192.09 seconds
Started Jul 02 09:31:38 AM PDT 24
Finished Jul 02 09:51:31 AM PDT 24
Peak memory 202168 kb
Host smart-365fccf0-c2ee-4836-a092-1c137e2acece
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234555841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1234555841
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1382005200
Short name T793
Test name
Test status
Simulation time 196248904695 ps
CPU time 44.81 seconds
Started Jul 02 09:31:34 AM PDT 24
Finished Jul 02 09:32:19 AM PDT 24
Peak memory 201908 kb
Host smart-08974434-36af-4c4e-a11a-0ffb0b07a930
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382005200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1382005200
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3297525486
Short name T780
Test name
Test status
Simulation time 107528885224 ps
CPU time 336.72 seconds
Started Jul 02 09:31:32 AM PDT 24
Finished Jul 02 09:37:10 AM PDT 24
Peak memory 202216 kb
Host smart-2870b3d4-91c0-49be-9704-251c46114963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297525486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3297525486
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1892390607
Short name T658
Test name
Test status
Simulation time 44574859110 ps
CPU time 102.13 seconds
Started Jul 02 09:31:33 AM PDT 24
Finished Jul 02 09:33:15 AM PDT 24
Peak memory 201700 kb
Host smart-d3da1199-1432-48fd-a32d-f29c5b84d6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892390607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1892390607
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1798520259
Short name T430
Test name
Test status
Simulation time 4735220190 ps
CPU time 2.67 seconds
Started Jul 02 09:31:36 AM PDT 24
Finished Jul 02 09:31:40 AM PDT 24
Peak memory 201720 kb
Host smart-7db9f9bb-1243-466d-b576-f6d33612f253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798520259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1798520259
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.612690002
Short name T786
Test name
Test status
Simulation time 5635725781 ps
CPU time 4.17 seconds
Started Jul 02 09:31:32 AM PDT 24
Finished Jul 02 09:31:37 AM PDT 24
Peak memory 201680 kb
Host smart-4a028eb9-64a1-4f70-a1f1-997084e5521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612690002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.612690002
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3718621820
Short name T741
Test name
Test status
Simulation time 500093034808 ps
CPU time 841.59 seconds
Started Jul 02 09:31:37 AM PDT 24
Finished Jul 02 09:45:40 AM PDT 24
Peak memory 201908 kb
Host smart-1e34a114-a9a5-49fa-99dd-2bacf9f86ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718621820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3718621820
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1732633357
Short name T634
Test name
Test status
Simulation time 32800973299 ps
CPU time 76.11 seconds
Started Jul 02 09:31:37 AM PDT 24
Finished Jul 02 09:32:54 AM PDT 24
Peak memory 202040 kb
Host smart-1ae9b667-83c1-4e4a-8b17-24f164540418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732633357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1732633357
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1488095990
Short name T594
Test name
Test status
Simulation time 474337407 ps
CPU time 0.97 seconds
Started Jul 02 09:31:46 AM PDT 24
Finished Jul 02 09:31:47 AM PDT 24
Peak memory 201660 kb
Host smart-fdb96c85-43a7-46ef-aa3d-39cdfa78668b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488095990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1488095990
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.908076236
Short name T725
Test name
Test status
Simulation time 179922589143 ps
CPU time 408.49 seconds
Started Jul 02 09:31:41 AM PDT 24
Finished Jul 02 09:38:31 AM PDT 24
Peak memory 201900 kb
Host smart-70b912ab-f3ed-4b99-a817-faa24903e775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908076236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.908076236
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2395124411
Short name T306
Test name
Test status
Simulation time 169794660746 ps
CPU time 397.06 seconds
Started Jul 02 09:31:37 AM PDT 24
Finished Jul 02 09:38:15 AM PDT 24
Peak memory 201908 kb
Host smart-614f61c4-cea3-4b4a-96dd-b1a75aa2e031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395124411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2395124411
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1409647331
Short name T428
Test name
Test status
Simulation time 331205353167 ps
CPU time 713.75 seconds
Started Jul 02 09:31:49 AM PDT 24
Finished Jul 02 09:43:43 AM PDT 24
Peak memory 201836 kb
Host smart-cf95ce9d-e42f-4fde-98a4-9c6f10cf2122
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409647331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1409647331
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3383767909
Short name T332
Test name
Test status
Simulation time 492683838549 ps
CPU time 515 seconds
Started Jul 02 09:31:40 AM PDT 24
Finished Jul 02 09:40:16 AM PDT 24
Peak memory 202168 kb
Host smart-51c6374a-3d7e-4914-9051-1eca4308a455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383767909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3383767909
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.36989284
Short name T190
Test name
Test status
Simulation time 333504884422 ps
CPU time 174.44 seconds
Started Jul 02 09:31:40 AM PDT 24
Finished Jul 02 09:34:35 AM PDT 24
Peak memory 202168 kb
Host smart-b973f7b5-ad2e-40b9-84d9-e9a37b63c38f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.36989284
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3653533383
Short name T240
Test name
Test status
Simulation time 233044131050 ps
CPU time 33.25 seconds
Started Jul 02 09:31:41 AM PDT 24
Finished Jul 02 09:32:15 AM PDT 24
Peak memory 201892 kb
Host smart-6d41af81-1760-4884-b57c-0c574b22170d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653533383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3653533383
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4032849639
Short name T463
Test name
Test status
Simulation time 582316932863 ps
CPU time 238.72 seconds
Started Jul 02 09:31:41 AM PDT 24
Finished Jul 02 09:35:40 AM PDT 24
Peak memory 201904 kb
Host smart-79b0ea7f-a323-478d-ae1f-c37c784a17bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032849639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4032849639
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1977083839
Short name T511
Test name
Test status
Simulation time 110215065210 ps
CPU time 356.16 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:37:45 AM PDT 24
Peak memory 202200 kb
Host smart-7f73f6bc-2a6b-4b1d-97d9-a98ad0ab1479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977083839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1977083839
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2292683202
Short name T534
Test name
Test status
Simulation time 27506457921 ps
CPU time 26.49 seconds
Started Jul 02 09:31:46 AM PDT 24
Finished Jul 02 09:32:13 AM PDT 24
Peak memory 201680 kb
Host smart-3204463f-d922-4fd0-ac78-9dd383f8eac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292683202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2292683202
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2292005702
Short name T777
Test name
Test status
Simulation time 3633569533 ps
CPU time 2.03 seconds
Started Jul 02 09:31:40 AM PDT 24
Finished Jul 02 09:31:43 AM PDT 24
Peak memory 201712 kb
Host smart-11d83275-a672-48ba-92a3-75cd6a30b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292005702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2292005702
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4224963966
Short name T368
Test name
Test status
Simulation time 5967915070 ps
CPU time 7.86 seconds
Started Jul 02 09:31:37 AM PDT 24
Finished Jul 02 09:31:45 AM PDT 24
Peak memory 201696 kb
Host smart-a4e7a497-2930-4cfe-ab0e-5948122b4ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224963966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4224963966
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3732785561
Short name T297
Test name
Test status
Simulation time 177314845861 ps
CPU time 37.24 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:32:26 AM PDT 24
Peak memory 201864 kb
Host smart-eff54d1e-8315-41f8-a505-75da3dfdda19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732785561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3732785561
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.484763894
Short name T370
Test name
Test status
Simulation time 346580486 ps
CPU time 1.39 seconds
Started Jul 02 09:31:54 AM PDT 24
Finished Jul 02 09:31:56 AM PDT 24
Peak memory 201664 kb
Host smart-23e62f79-286c-4734-9c60-4e73effbd1f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484763894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.484763894
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.519132850
Short name T292
Test name
Test status
Simulation time 490925091248 ps
CPU time 1022.64 seconds
Started Jul 02 09:31:49 AM PDT 24
Finished Jul 02 09:48:52 AM PDT 24
Peak memory 201872 kb
Host smart-8e3c9372-584f-44fa-ab36-3c56c6665a5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519132850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.519132850
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1366581534
Short name T533
Test name
Test status
Simulation time 159725825271 ps
CPU time 336.34 seconds
Started Jul 02 09:31:47 AM PDT 24
Finished Jul 02 09:37:24 AM PDT 24
Peak memory 201984 kb
Host smart-a5487ee2-e688-4827-8553-9e40305175c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366581534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1366581534
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1819061635
Short name T99
Test name
Test status
Simulation time 332486967229 ps
CPU time 823.35 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:45:31 AM PDT 24
Peak memory 201860 kb
Host smart-27bd3d5a-31a0-4614-b3aa-fa2acdddaa8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819061635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1819061635
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2810343844
Short name T171
Test name
Test status
Simulation time 328912981346 ps
CPU time 189.31 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:34:58 AM PDT 24
Peak memory 201884 kb
Host smart-91bde62e-5f9a-4c71-a7c4-4b6228b92ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810343844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2810343844
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3580855310
Short name T381
Test name
Test status
Simulation time 490952172785 ps
CPU time 1169.84 seconds
Started Jul 02 09:31:49 AM PDT 24
Finished Jul 02 09:51:19 AM PDT 24
Peak memory 201968 kb
Host smart-d3859a50-d918-44e8-8d9c-c439f30aee4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580855310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3580855310
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.4141955851
Short name T734
Test name
Test status
Simulation time 385532060065 ps
CPU time 881.33 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:46:30 AM PDT 24
Peak memory 201948 kb
Host smart-947df3ec-b186-470d-a45f-dcf813c3db74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141955851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.4141955851
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.843488442
Short name T205
Test name
Test status
Simulation time 405856768940 ps
CPU time 824.56 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:45:34 AM PDT 24
Peak memory 201788 kb
Host smart-9edc3613-f5bb-444e-9122-03ef1bebbb8f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843488442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.843488442
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1490104857
Short name T574
Test name
Test status
Simulation time 84376700017 ps
CPU time 292.74 seconds
Started Jul 02 09:31:53 AM PDT 24
Finished Jul 02 09:36:46 AM PDT 24
Peak memory 202224 kb
Host smart-68ff694a-5c72-4bfc-bed8-2f5d898ea9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490104857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1490104857
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3807246707
Short name T369
Test name
Test status
Simulation time 36758968175 ps
CPU time 18.16 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:32:07 AM PDT 24
Peak memory 201720 kb
Host smart-ca6297cb-c64c-4e7c-b2dd-86447ae5a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807246707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3807246707
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.406888340
Short name T676
Test name
Test status
Simulation time 4890668096 ps
CPU time 8.36 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:31:57 AM PDT 24
Peak memory 201744 kb
Host smart-9d3417bc-033a-4662-b474-f969f13cc92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406888340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.406888340
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.507371581
Short name T412
Test name
Test status
Simulation time 5969774957 ps
CPU time 7.24 seconds
Started Jul 02 09:31:48 AM PDT 24
Finished Jul 02 09:31:56 AM PDT 24
Peak memory 201680 kb
Host smart-28bea749-0af8-46c1-811d-267a2713f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507371581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.507371581
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2870641025
Short name T544
Test name
Test status
Simulation time 346945598711 ps
CPU time 432.96 seconds
Started Jul 02 09:31:53 AM PDT 24
Finished Jul 02 09:39:07 AM PDT 24
Peak memory 201916 kb
Host smart-c43e7564-7386-4177-b0d5-204f8fc5f341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870641025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2870641025
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2392215251
Short name T702
Test name
Test status
Simulation time 382230214 ps
CPU time 0.79 seconds
Started Jul 02 09:31:55 AM PDT 24
Finished Jul 02 09:31:56 AM PDT 24
Peak memory 201620 kb
Host smart-7bc65ab1-dabd-40ad-ac09-bc7b26c7991b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392215251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2392215251
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3827605720
Short name T424
Test name
Test status
Simulation time 341682492112 ps
CPU time 195.23 seconds
Started Jul 02 09:31:53 AM PDT 24
Finished Jul 02 09:35:09 AM PDT 24
Peak memory 201996 kb
Host smart-c045279b-97c3-481d-a37a-40fa9a862906
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827605720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3827605720
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3950424045
Short name T192
Test name
Test status
Simulation time 323184483188 ps
CPU time 742.77 seconds
Started Jul 02 09:31:52 AM PDT 24
Finished Jul 02 09:44:15 AM PDT 24
Peak memory 201904 kb
Host smart-705633ce-ddee-4cc0-8e38-4ddfae2e5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950424045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3950424045
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2985492440
Short name T697
Test name
Test status
Simulation time 338850525486 ps
CPU time 716.59 seconds
Started Jul 02 09:31:54 AM PDT 24
Finished Jul 02 09:43:51 AM PDT 24
Peak memory 201872 kb
Host smart-288e71b3-0655-4383-86a5-e6f45ef54bfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985492440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2985492440
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3717639953
Short name T523
Test name
Test status
Simulation time 169040246146 ps
CPU time 56.46 seconds
Started Jul 02 09:31:55 AM PDT 24
Finished Jul 02 09:32:52 AM PDT 24
Peak memory 201952 kb
Host smart-a569223d-723e-45a8-86bf-5ce1ee43724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717639953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3717639953
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2707271411
Short name T382
Test name
Test status
Simulation time 492739065928 ps
CPU time 1041.6 seconds
Started Jul 02 09:32:01 AM PDT 24
Finished Jul 02 09:49:23 AM PDT 24
Peak memory 201884 kb
Host smart-6f0a9659-b6cb-4de4-bdb8-7b9d314bb384
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707271411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2707271411
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2120555269
Short name T667
Test name
Test status
Simulation time 169568560685 ps
CPU time 384.54 seconds
Started Jul 02 09:31:55 AM PDT 24
Finished Jul 02 09:38:20 AM PDT 24
Peak memory 201972 kb
Host smart-e1c17cf6-c35a-4e7f-8118-bda3e3d4fdfe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120555269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2120555269
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1237612647
Short name T27
Test name
Test status
Simulation time 589990314502 ps
CPU time 1208.3 seconds
Started Jul 02 09:31:55 AM PDT 24
Finished Jul 02 09:52:04 AM PDT 24
Peak memory 201892 kb
Host smart-2076514f-1d41-427d-8536-cb4a6295c873
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237612647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1237612647
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2439419191
Short name T484
Test name
Test status
Simulation time 72510436432 ps
CPU time 242.99 seconds
Started Jul 02 09:31:57 AM PDT 24
Finished Jul 02 09:36:00 AM PDT 24
Peak memory 202284 kb
Host smart-04c56191-4a15-43a7-be34-e95021cb2f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439419191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2439419191
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1981118559
Short name T553
Test name
Test status
Simulation time 45983660101 ps
CPU time 16.79 seconds
Started Jul 02 09:31:56 AM PDT 24
Finished Jul 02 09:32:13 AM PDT 24
Peak memory 201716 kb
Host smart-faa4eed8-bb3a-48ef-99fb-4cb1b4a1d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981118559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1981118559
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1330588786
Short name T698
Test name
Test status
Simulation time 3265824180 ps
CPU time 2.74 seconds
Started Jul 02 09:31:55 AM PDT 24
Finished Jul 02 09:31:58 AM PDT 24
Peak memory 201644 kb
Host smart-85189e56-4e83-40c1-a351-d6d98e8d6c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330588786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1330588786
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3519815154
Short name T216
Test name
Test status
Simulation time 5757354213 ps
CPU time 14.37 seconds
Started Jul 02 09:31:53 AM PDT 24
Finished Jul 02 09:32:08 AM PDT 24
Peak memory 201640 kb
Host smart-2f94bace-4591-42ce-909b-38d95bf2f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519815154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3519815154
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2233910116
Short name T392
Test name
Test status
Simulation time 3777633871 ps
CPU time 9.12 seconds
Started Jul 02 09:31:57 AM PDT 24
Finished Jul 02 09:32:07 AM PDT 24
Peak memory 201716 kb
Host smart-19e57edc-3cc3-4c4d-a8d8-3d1e69d36c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233910116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2233910116
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.258638559
Short name T364
Test name
Test status
Simulation time 153147037194 ps
CPU time 199.92 seconds
Started Jul 02 09:31:57 AM PDT 24
Finished Jul 02 09:35:17 AM PDT 24
Peak memory 210536 kb
Host smart-91e352cc-a3c2-4cc5-b358-997dea59f3ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258638559 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.258638559
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3652812031
Short name T491
Test name
Test status
Simulation time 429889600 ps
CPU time 0.91 seconds
Started Jul 02 09:32:01 AM PDT 24
Finished Jul 02 09:32:02 AM PDT 24
Peak memory 201848 kb
Host smart-72748651-0fa2-41a6-b6a0-fa14e56a2f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652812031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3652812031
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2198400565
Short name T519
Test name
Test status
Simulation time 566680304495 ps
CPU time 1187.66 seconds
Started Jul 02 09:31:55 AM PDT 24
Finished Jul 02 09:51:43 AM PDT 24
Peak memory 202004 kb
Host smart-0ed53a8e-b291-4ffe-81ef-d456ba463245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198400565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2198400565
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1431643566
Short name T456
Test name
Test status
Simulation time 331318942581 ps
CPU time 701.22 seconds
Started Jul 02 09:31:57 AM PDT 24
Finished Jul 02 09:43:39 AM PDT 24
Peak memory 201916 kb
Host smart-7186933c-d96f-41e3-91a8-dd2bbb8778cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431643566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1431643566
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2446528286
Short name T671
Test name
Test status
Simulation time 492383944457 ps
CPU time 332.69 seconds
Started Jul 02 09:32:01 AM PDT 24
Finished Jul 02 09:37:34 AM PDT 24
Peak memory 201968 kb
Host smart-e9e5b8ab-8c60-4c6d-aff3-827d1a440670
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446528286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2446528286
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3581127250
Short name T475
Test name
Test status
Simulation time 492585038129 ps
CPU time 1006.62 seconds
Started Jul 02 09:31:56 AM PDT 24
Finished Jul 02 09:48:43 AM PDT 24
Peak memory 201996 kb
Host smart-2fe9009a-d7dc-4882-af76-2a269fc5fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581127250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3581127250
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2848563267
Short name T208
Test name
Test status
Simulation time 168515695367 ps
CPU time 93.69 seconds
Started Jul 02 09:31:57 AM PDT 24
Finished Jul 02 09:33:31 AM PDT 24
Peak memory 201908 kb
Host smart-8f5c261d-8f8a-498c-9182-e5fedd34b9b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848563267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2848563267
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1136976607
Short name T713
Test name
Test status
Simulation time 533084925990 ps
CPU time 566.4 seconds
Started Jul 02 09:31:56 AM PDT 24
Finished Jul 02 09:41:23 AM PDT 24
Peak memory 201940 kb
Host smart-89121011-d5a9-4603-baf2-acf943158f9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136976607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1136976607
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.57603491
Short name T207
Test name
Test status
Simulation time 206421834149 ps
CPU time 245.24 seconds
Started Jul 02 09:31:56 AM PDT 24
Finished Jul 02 09:36:02 AM PDT 24
Peak memory 201904 kb
Host smart-5c9c0165-ca61-48b9-9093-ec5828869dad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57603491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.57603491
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2016223775
Short name T365
Test name
Test status
Simulation time 130301792192 ps
CPU time 467.78 seconds
Started Jul 02 09:32:00 AM PDT 24
Finished Jul 02 09:39:48 AM PDT 24
Peak memory 202212 kb
Host smart-a8e5e4c9-deec-4386-b2f3-70e4e562aae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016223775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2016223775
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3552693817
Short name T45
Test name
Test status
Simulation time 39417864193 ps
CPU time 89.82 seconds
Started Jul 02 09:32:00 AM PDT 24
Finished Jul 02 09:33:30 AM PDT 24
Peak memory 201652 kb
Host smart-1499d721-d161-4a14-9557-1c335192c75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552693817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3552693817
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1506136341
Short name T372
Test name
Test status
Simulation time 5102278089 ps
CPU time 6.42 seconds
Started Jul 02 09:32:01 AM PDT 24
Finished Jul 02 09:32:08 AM PDT 24
Peak memory 201728 kb
Host smart-5dc50aa8-f109-4357-9232-b3b1db4a7537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506136341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1506136341
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.183861191
Short name T797
Test name
Test status
Simulation time 5618836283 ps
CPU time 6.86 seconds
Started Jul 02 09:31:58 AM PDT 24
Finished Jul 02 09:32:05 AM PDT 24
Peak memory 201684 kb
Host smart-a0218103-d0e0-4950-9bed-d81524dd51ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183861191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.183861191
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.603316424
Short name T52
Test name
Test status
Simulation time 224341764400 ps
CPU time 107.27 seconds
Started Jul 02 09:31:59 AM PDT 24
Finished Jul 02 09:33:46 AM PDT 24
Peak memory 210536 kb
Host smart-3f3a9691-6e77-40f2-8147-5e978aa6093c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603316424 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.603316424
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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