Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7088	1			T1	10		T2	43		T6	5
testmodes[AdcCtrlTestmodeNormal]	5287	1			T1	10		T2	19		T3	1
testmodes[AdcCtrlTestmodeLowpower]	5459	1			T2	3		T4	2		T41	49
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3942	1			T1	4		T2	31		T6	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1703	1			T1	5		T2	11		T6	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1323	1			T41	12		T56	16		T57	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1706	1			T1	6		T2	12		T6	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1944	1			T1	4		T2	7		T5	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1311	1			T41	17		T49	1		T56	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1316	1			T41	11		T56	14		T40	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1315	1			T2	1		T41	18		T49	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2576	1			T2	2		T4	1		T41	20