Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22386

1

T1

20

T2

63

T4

35

auto[ADC_CTRL_FILTER_COND_OUT]

3291

1

T2

4

T3

1

T5

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19859

1

T1

20

T2

60

T3

1

auto[1]

5818

1

T2

7

T4

19

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T215	10		T216	2		-	-
values[0]	102	1			T217	1		T196	1		T16	3
values[1]	732	1			T9	29		T13	1		T52	7
values[2]	754	1			T40	2		T28	25		T29	28
values[3]	524	1			T49	17		T55	21		T165	13
values[4]	489	1			T4	19		T49	37		T50	1
values[5]	655	1			T7	20		T8	12		T49	13
values[6]	593	1			T4	16		T8	10		T51	2
values[7]	748	1			T2	4		T50	12		T53	16
values[8]	695	1			T5	1		T8	1		T12	10
values[9]	3445	1			T2	3		T3	1		T5	2
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	981	1			T9	29		T13	1		T90	7
values[1]	768	1			T49	17		T52	7		T40	2
values[2]	522	1			T4	19		T55	21		T165	13
values[3]	521	1			T7	20		T49	37		T50	9
values[4]	534	1			T8	12		T49	13		T51	2
values[5]	607	1			T2	4		T4	16		T15	11
values[6]	2975	1			T8	11		T11	15		T150	31
values[7]	782	1			T5	2		T12	10		T13	1
values[8]	862	1			T2	3		T3	1		T5	1
values[9]	155	1			T12	12		T218	12		T146	1
minimum	16970	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T9	2		T13	1		T28	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T90	1		T54	12		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	10		T40	2		T149	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T52	7		T104	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T4	13		T55	6		T26	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T55	15		T165	6		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	11		T155	10		T166	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T49	21		T50	9		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T8	1		T49	7		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T54	14		T28	19		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	7		T27	1		T220	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	3		T15	8		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T8	1		T11	2		T150	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T50	12		T53	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	1		T51	12		T52	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	2		T13	1		T62	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	3		T12	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T3	1		T5	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T12	1		T146	1		T221	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T218	6		T44	2		T222	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16830	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T9	27		T28	11		T43	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T90	6		T54	10		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	7		T223	8		T170	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T45	2		T141	1		T224	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	6		T26	13		T29	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T165	7		T43	1		T145	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	9		T46	19		T168	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T49	16		T225	14		T226	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	11		T49	6		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T54	11		T28	13		T227	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	9		T27	11		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	1		T15	3		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T11	13		T150	28		T30	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	9		T62	7		T26	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	9		T51	10		T90	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T62	13		T228	7		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	4		T163	2		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T51	1		T54	1		T230	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T12	11		T224	9		T231	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T218	6		T222	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T40	2		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T215	10		T216	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T196	1		T36	1		T232	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T217	1		T16	2		T233	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T9	2		T13	1		T28	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T52	7		T90	1		T54	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	2		T28	14		T29	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T104	1		T143	2		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T49	10		T55	6		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T55	15		T165	6		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	13		T218	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T49	21		T50	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	11		T8	1		T49	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	8		T54	14		T28	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	7		T51	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	1		T15	9		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T42	8		T220	6		T153	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	3		T50	12		T53	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T12	1		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T13	1		T62	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T2	3		T11	2		T12	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T3	1		T5	2		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T36	13		T232	13		T234	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T16	1		T233	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	27		T147	10		T235	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T90	6		T54	10		T141	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T28	11		T29	17		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T224	13		T178	1		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	7		T26	13		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T165	7		T45	2		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	6		T226	4		T238	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T49	16		T43	1		T145	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	9		T8	11		T49	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	11		T28	13		T225	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	9		T51	1		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	9		T15	3		T196	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	3		T147	10		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	1		T62	7		T26	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	9		T51	10		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T62	13		T183	18		T228	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T11	13		T12	15		T150	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T51	1		T54	1		T218	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T9	29		T13	1		T28	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T90	7		T54	11		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	8		T40	2		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T52	1		T104	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	7		T55	1		T26	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T55	1		T165	8		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	10		T155	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	17		T50	2		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	12		T49	7		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T54	12		T28	14		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	10		T27	12		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	3		T15	8		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T8	1		T11	15		T150	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	10		T50	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	10		T51	11		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	2		T13	1		T62	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	3		T12	5		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T3	1		T5	1		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T12	12		T146	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T218	7		T44	2		T222	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16933	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T28	14		T43	4		T235	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T54	11		T239	20		T193	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	9		T149	15		T223	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T52	6		T45	2		T240	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	12		T55	5		T26	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T55	14		T165	5		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	10		T155	9		T166	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T49	20		T50	7		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T49	6		T177	15		T242	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T54	13		T28	18		T227	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	6		T220	5		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	1		T15	3		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T42	3		T103	11		T108	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T50	11		T53	15		T62	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	11		T52	11		T53	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T62	2		T221	12		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	10		T29	10		T176	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T55	2		T230	14		T243	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T221	10		T155	14		T231	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T218	5		T222	9		T244	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T241	4		T245	15		T246	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T215	1		T216	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T196	1		T36	14		T232	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T217	1		T16	3		T233	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	29		T13	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T52	1		T90	7		T54	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	2		T28	12		T29	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T104	1		T143	2		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	8		T55	1		T26	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T55	1		T165	8		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	7		T218	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T49	17		T50	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	10		T8	12		T49	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T50	1		T54	12		T28	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	10		T51	2		T27	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	10		T15	9		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	8		T220	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	3		T50	1		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	1		T12	10		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T13	1		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T2	3		T11	15		T12	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T3	1		T5	2		T51	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T215	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T232	12		T234	2		T247	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T233	13		T248	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T28	1		T235	6		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T52	6		T54	11		T141	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T28	13		T29	10		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T239	20		T236	10		T180	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	9		T55	5		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T55	14		T165	5		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	12		T170	15		T215	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T49	20		T43	1		T249	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	10		T49	6		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T50	7		T54	13		T28	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	6		T183	22		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	3		T196	7		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	3		T220	5		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	1		T50	11		T53	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T51	11		T52	11		T53	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T62	2		T221	12		T183	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T53	10		T29	10		T103	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T55	2		T218	5		T230	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22044

1

T1

20

T2

64

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3633

1

T2

3

T3

1

T4

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19475

1

T1

20

T2

62

T3

1

auto[1]

6202

1

T2

5

T4

35

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	446	1			T2	1		T41	3		T56	3
values[0]	42	1			T179	11		T60	20		T251	1
values[1]	712	1			T12	10		T51	2		T52	12
values[2]	2804	1			T11	15		T150	31		T86	2
values[3]	658	1			T4	16		T5	1		T8	1
values[4]	787	1			T2	3		T50	12		T165	13
values[5]	758	1			T5	1		T8	10		T9	17
values[6]	639	1			T7	20		T12	12		T13	1
values[7]	641	1			T8	12		T13	1		T49	30
values[8]	555	1			T3	1		T5	1		T52	7
values[9]	1116	1			T2	4		T4	19		T9	12
minimum	16519	1			T1	20		T2	59		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T12	10		T51	2		T52	12
values[1]	2766	1			T8	1		T11	15		T150	31
values[2]	830	1			T4	16		T5	1		T12	5
values[3]	707	1			T2	3		T5	1		T50	8
values[4]	685	1			T7	20		T9	17		T49	37
values[5]	661	1			T8	10		T12	12		T13	1
values[6]	655	1			T8	12		T13	1		T49	30
values[7]	422	1			T3	1		T4	19		T5	1
values[8]	971	1			T2	4		T9	12		T50	1
values[9]	147	1			T26	26		T145	12		T252	13
minimum	16968	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T51	1		T52	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T54	14		T62	12		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T8	1		T11	2		T150	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T90	1		T54	1		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	7		T12	1		T50	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	1		T51	1		T53	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	8		T40	1		T165	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	3		T5	1		T55	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T49	21		T42	8		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	11		T9	1		T28	33
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T26	4		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	1		T13	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	1		T13	1		T49	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T90	1		T28	2		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T52	7		T147	1		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T4	13		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T2	3		T9	1		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T55	15		T219	1		T177	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T254	8		T255	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T26	13		T145	1		T252	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16816	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	9		T51	1		T145	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T54	11		T62	20		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T11	13		T150	28		T30	31
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T90	6		T54	1		T27	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	9		T12	4		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	1		T29	10		T224	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T165	7		T256	12		T257	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	4		T228	11		T245	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T49	16		T42	3		T178	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	9		T9	16		T28	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	11		T26	3		T145	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	9		T163	2		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	11		T49	13		T51	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T90	12		T183	18		T223	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T147	4		T156	6		T141	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T4	6		T16	1		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T9	11		T54	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T177	11		T147	10		T235	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T254	2		T186	1		T258	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T26	13		T145	11		T259	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T40	2		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T2	1		T41	3		T56	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T260	1		T261	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T179	1		T60	12		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T51	1		T52	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T62	12		T147	1		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1517	1			T11	2		T150	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T53	16		T54	15		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	7		T8	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T51	1		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T50	12		T165	6		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	3		T29	11		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T49	21		T50	8		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T8	1		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T145	1		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	11		T13	1		T55	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	1		T13	1		T49	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T90	1		T143	1		T196	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T52	7		T40	2		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T5	1		T53	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	3		T9	1		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T4	13		T55	15		T26	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16381	1			T1	20		T2	59		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T260	11		T261	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T179	10		T60	8		T264	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T262	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	9		T51	1		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T62	20		T147	10		T183	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T11	13		T150	28		T30	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T54	12		T27	11		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	9		T12	4		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	1		T90	6		T27	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T165	7		T256	12		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T29	10		T228	11		T178	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	16		T42	3		T178	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	9		T9	16		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	11		T145	17		T183	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	9		T28	11		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	11		T49	13		T51	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T90	12		T196	7		T46	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T156	6		T170	12		T265	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T183	18		T16	1		T236	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	1		T9	11		T54	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T4	6		T26	13		T145	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1