Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22470

1

T1

20

T2

63

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3207

1

T2

4

T3

1

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19946

1

T1

20

T2

64

T3

1

auto[1]

5731

1

T2

3

T4

35

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T156	7		T302	19		-	-
values[0]	60	1			T8	12		T12	10		T218	12
values[1]	583	1			T7	20		T9	17		T12	5
values[2]	2811	1			T11	15		T12	12		T150	31
values[3]	745	1			T4	19		T5	1		T52	7
values[4]	672	1			T4	16		T8	10		T90	13
values[5]	773	1			T49	13		T50	12		T54	27
values[6]	504	1			T3	1		T5	1		T8	1
values[7]	608	1			T5	1		T50	8		T52	12
values[8]	771	1			T13	1		T49	37		T51	22
values[9]	1196	1			T2	7		T51	4		T40	1
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	773	1			T7	20		T8	12		T9	17
values[1]	2808	1			T4	19		T11	15		T12	12
values[2]	937	1			T5	1		T8	10		T90	13
values[3]	545	1			T4	16		T49	13		T55	3
values[4]	762	1			T8	1		T9	12		T49	17
values[5]	454	1			T3	1		T5	1		T13	1
values[6]	608	1			T5	1		T50	8		T51	22
values[7]	804	1			T13	1		T49	37		T40	2
values[8]	933	1			T2	3		T51	2		T40	1
values[9]	105	1			T2	4		T51	2		T54	22
minimum	16948	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	11		T12	2		T27	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T9	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T4	13		T11	2		T150	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T144	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	1		T143	1		T221	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	1		T90	1		T165	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	3		T43	2		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	7		T49	7		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T9	1		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	12		T54	14		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	1		T13	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T90	1		T53	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T51	12		T55	6		T62	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	1		T50	8		T52	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T40	2		T53	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T49	21		T220	6		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T2	3		T40	1		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T51	1		T217	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T54	12		T225	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T2	3		T51	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T160	9		T187	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	9		T12	13		T27	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	11		T9	16		T43	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T4	6		T11	13		T150	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	11		T145	11		T196	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T273	11		T320	15		T237	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	9		T90	12		T165	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T43	1		T147	10		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T4	9		T49	6		T147	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	11		T49	7		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	11		T15	3		T145	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T54	1		T141	3		T224	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T90	6		T26	3		T257	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	10		T62	13		T29	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T228	7		T268	8		T182	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T178	5		T236	5		T321	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T49	16		T179	10		T60	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T29	10		T156	6		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T51	1		T45	2		T183	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T54	10		T225	14		T226	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T2	1		T51	1		T145	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T160	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T156	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T302	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T12	1		T218	6		T46	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T8	1		T48	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	11		T12	1		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	1		T15	1		T196	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T11	2		T150	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T50	1		T55	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	13		T5	1		T52	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T165	6		T142	1		T153	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T55	3		T43	2		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	7		T8	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T54	1		T143	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T49	7		T50	12		T54	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T8	1		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T90	1		T53	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T55	6		T62	3		T29	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T50	8		T52	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	1		T51	12		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	21		T220	6		T155	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T2	3		T40	1		T54	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T2	3		T51	2		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T156	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T302	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T12	9		T218	6		T46	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T8	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	9		T12	4		T27	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	16		T196	7		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T11	13		T150	28		T62	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	11		T43	4		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	6		T229	7		T273	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T165	7		T229	2		T157	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	1		T48	1		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	9		T8	9		T90	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T54	1		T147	10		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	6		T54	11		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T9	11		T49	7		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T90	6		T26	3		T230	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T62	13		T29	17		T141	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T257	4		T228	18		T268	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T51	10		T46	3		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T49	16		T179	10		T158	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T54	10		T29	10		T225	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	1		T51	2		T145	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	10		T12	15		T27	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	12		T9	17		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T4	7		T11	15		T150	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	12		T144	1		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	1		T143	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T8	10		T90	13		T165	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	1		T43	2		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T4	10		T49	7		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	1		T9	12		T49	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	1		T54	12		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	1		T13	1		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	1		T90	7		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T51	11		T55	1		T62	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T5	1		T50	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	1		T40	2		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T49	17		T220	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T2	3		T40	1		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T51	2		T217	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T54	11		T225	15		T226	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T2	3		T51	2		T145	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T160	11		T187	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	10		T28	14		T42	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T55	14		T43	4		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T4	12		T52	6		T53	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T196	7		T243	3		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T221	10		T241	4		T320	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T165	5		T176	6		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T55	2		T43	1		T235	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T4	6		T49	6		T183	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	9		T16	1		T266	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	11		T54	13		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T191	1		T215	9		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T53	15		T26	3		T257	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T51	11		T55	5		T62	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T50	7		T52	11		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T53	3		T166	6		T239	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T49	20		T220	5		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T29	10		T240	12		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	2		T183	15		T141	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T54	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T2	1		T194	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T160	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T156	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T302	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T12	10		T218	7		T46	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T8	12		T48	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	10		T12	5		T27	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	17		T15	1		T196	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T11	15		T150	31		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	12		T50	1		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	7		T5	1		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T165	8		T142	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T55	1		T43	2		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	10		T8	10		T90	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T54	2		T143	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T49	7		T50	1		T54	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	1		T8	1		T9	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T90	7		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T55	1		T62	14		T29	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T50	1		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	1		T51	11		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T49	17		T220	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T2	3		T40	1		T54	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T2	3		T51	4		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T302	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T218	5		T46	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	10		T28	13		T42	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T196	7		T241	4		T243	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T53	10		T62	8		T26	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T55	14		T43	4		T243	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	12		T52	6		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T165	5		T153	11		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T55	2		T43	1		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	6		T176	6		T177	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T235	6		T227	9		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T49	6		T50	11		T54	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T49	9		T266	8		T223	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T53	15		T26	3		T230	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T55	5		T62	2		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T50	7		T52	11		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T51	11		T53	3		T166	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T49	20		T220	5		T155	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T54	11		T29	10		T240	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T45	2		T183	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10