Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22442

1

T1

20

T2

63

T4

35

auto[ADC_CTRL_FILTER_COND_OUT]

3235

1

T2

4

T3

1

T5

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19824

1

T1

20

T2

60

T3

1

auto[1]

5853

1

T2

7

T4

19

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	298	1			T5	1		T53	11		T163	3
values[0]	30	1			T217	1		T147	11		T16	3
values[1]	851	1			T9	29		T13	1		T52	7
values[2]	749	1			T40	2		T28	25		T29	28
values[3]	497	1			T49	17		T55	21		T165	13
values[4]	524	1			T4	19		T7	20		T49	37
values[5]	610	1			T8	12		T49	13		T54	25
values[6]	494	1			T4	16		T51	2		T15	12
values[7]	848	1			T2	4		T8	10		T50	12
values[8]	695	1			T5	1		T8	1		T12	10
values[9]	3153	1			T2	3		T3	1		T5	1
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	743	1			T9	17		T13	1		T90	7
values[1]	825	1			T49	17		T52	7		T40	2
values[2]	531	1			T4	19		T55	21		T165	13
values[3]	451	1			T7	20		T49	37		T50	9
values[4]	578	1			T8	12		T49	13		T51	2
values[5]	593	1			T2	4		T4	16		T15	12
values[6]	2982	1			T8	10		T11	15		T150	31
values[7]	784	1			T5	2		T8	1		T12	10
values[8]	911	1			T2	3		T5	1		T12	17
values[9]	113	1			T3	1		T146	1		T44	2
minimum	17166	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T90	1		T28	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	1		T54	12		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T49	10		T40	2		T29	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T52	7		T104	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	13		T55	6		T26	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T55	15		T165	6		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	11		T50	8		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T49	21		T50	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	1		T49	7		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T54	14		T28	19		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	7		T220	6		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	3		T15	9		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T11	2		T150	3		T86	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T50	12		T53	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	1		T12	1		T52	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	2		T13	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	3		T12	2		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T5	1		T51	1		T54	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T146	1		T155	15		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T3	1		T44	2		T222	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16910	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T29	1		T217	1		T16	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T90	6		T28	11		T235	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	16		T54	10		T178	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	7		T29	17		T43	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	2		T141	1		T224	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	6		T26	13		T183	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T165	7		T145	7		T237	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T7	9		T168	2		T215	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	16		T43	1		T225	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	11		T49	6		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T54	11		T28	13		T156	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	9		T147	10		T323	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	1		T15	3		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T11	13		T150	28		T51	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	9		T62	20		T26	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	9		T147	4		T256	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T183	18		T228	7		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	15		T90	12		T163	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T51	1		T54	1		T218	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T295	11		T231	11		T238	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T222	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	1		T9	11		T40	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T16	1		T237	4		T280	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T53	11		T163	1		T176	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	1		T218	6		T60	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T147	1		T36	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T217	1		T16	2		T324	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T9	1		T13	1		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T52	7		T54	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	2		T28	14		T29	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T143	2		T144	1		T253	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	10		T55	6		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T55	15		T165	6		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	13		T7	11		T50	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T49	21		T50	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	1		T49	7		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T54	14		T28	19		T241	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T4	7		T51	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	9		T142	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T42	8		T153	12		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	3		T8	1		T50	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	1		T12	1		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	1		T13	1		T62	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T2	3		T11	2		T12	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T3	1		T5	1		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T163	2		T224	9		T295	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T218	6		T60	8		T277	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T147	10		T36	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T16	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	11		T90	6		T235	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	16		T54	10		T193	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T28	11		T29	17		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T141	1		T224	13		T178	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T49	7		T26	13		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T165	7		T45	2		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	6		T7	9		T170	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T49	16		T43	1		T145	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	11		T49	6		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T54	11		T28	13		T223	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T4	9		T51	1		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	3		T145	11		T156	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T42	3		T147	10		T183	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T8	9		T62	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	9		T51	10		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T62	13		T183	18		T228	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T11	13		T12	15		T150	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T51	1		T54	1		T230	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	1		T90	7		T28	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	17		T54	11		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T49	8		T40	2		T29	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T52	1		T104	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	7		T55	1		T26	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T55	1		T165	8		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	10		T50	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	17		T50	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	12		T49	7		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T54	12		T28	14		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	10		T220	1		T147	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	3		T15	9		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T11	15		T150	31		T86	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	10		T50	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	1		T12	10		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	2		T13	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	3		T12	17		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T5	1		T51	2		T54	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T146	1		T155	1		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T3	1		T44	2		T222	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17023	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T29	1		T217	1		T16	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T28	14		T235	6		T243	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	11		T239	20		T193	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	9		T29	10		T43	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	6		T45	2		T240	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	12		T55	5		T26	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T55	14		T165	5		T287	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	10		T50	7		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T49	20		T43	1		T296	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T49	6		T177	15		T166	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	13		T28	18		T227	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T4	6		T220	5		T250	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	1		T15	3		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T51	11		T42	3		T103	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	11		T53	15		T62	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T52	11		T53	3		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T221	12		T183	15		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T53	10		T29	10		T176	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T55	2		T218	5		T230	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T155	14		T295	1		T231	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T222	9		T244	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T241	4		T245	15		T325	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T237	1		T248	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T53	1		T163	3		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T5	1		T218	7		T60	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T147	11		T36	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T217	1		T16	3		T324	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	12		T13	1		T90	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	17		T52	1		T54	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	2		T28	12		T29	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T143	2		T144	1		T253	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	8		T55	1		T26	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T55	1		T165	8		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	7		T7	10		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	17		T50	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	12		T49	7		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T54	12		T28	14		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	10		T51	2		T27	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	9		T142	1		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T42	8		T153	1		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	3		T8	10		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	1		T12	10		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	1		T13	1		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T2	3		T11	15		T12	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T3	1		T5	1		T51	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T53	10		T176	6		T155	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T218	5		T60	5		T277	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T28	1		T235	6		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T52	6		T54	11		T193	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T28	13		T29	10		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	1		T239	20		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T49	9		T55	5		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T55	14		T165	5		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	12		T7	10		T50	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T49	20		T43	1		T296	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	6		T155	9		T177	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T54	13		T28	18		T241	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T4	6		T220	5		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	3		T227	9		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T42	3		T153	11		T183	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	1		T50	11		T53	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T51	11		T52	11		T53	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T62	2		T221	12		T183	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T29	10		T103	11		T108	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T55	2		T230	14		T241	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10