Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22211

1

T1

20

T2

63

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3466

1

T2

4

T4

19

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19801

1

T1

20

T2

64

T3

1

auto[1]

5876

1

T2

3

T4

16

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	282	1			T3	1		T12	10		T52	12
values[0]	42	1			T146	1		T279	1		T328	6
values[1]	666	1			T2	3		T52	7		T40	1
values[2]	651	1			T4	35		T8	12		T163	3
values[3]	558	1			T5	1		T50	12		T51	2
values[4]	778	1			T49	54		T51	22		T90	7
values[5]	2842	1			T2	4		T5	2		T7	20
values[6]	759	1			T8	10		T13	1		T50	8
values[7]	572	1			T9	17		T144	1		T183	34
values[8]	700	1			T8	1		T9	12		T49	13
values[9]	899	1			T12	5		T13	1		T51	2
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	700	1			T2	3		T4	19		T52	7
values[1]	640	1			T4	16		T8	12		T51	2
values[2]	478	1			T5	1		T50	12		T51	22
values[3]	2992	1			T2	4		T5	1		T11	15
values[4]	737	1			T7	20		T8	10		T12	12
values[5]	685	1			T5	1		T13	1		T50	8
values[6]	632	1			T9	29		T50	1		T28	32
values[7]	733	1			T8	1		T13	1		T49	13
values[8]	885	1			T12	5		T51	2		T52	12
values[9]	88	1			T3	1		T12	10		T54	22
minimum	17107	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	3		T40	1		T165	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	13		T52	7		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	7		T51	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	1		T26	13		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T50	12		T143	1		T166	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T51	12		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T5	1		T11	2		T49	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	3		T49	21		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	11		T12	1		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T29	11		T42	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T50	8		T54	1		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	1		T13	1		T53	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	1		T28	19		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	2		T218	6		T183	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T53	16		T54	14		T15	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T13	1		T49	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T51	1		T52	12		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T43	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T3	1		T12	1		T236	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T54	12		T290	1		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16850	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T146	1		T149	1		T328	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T165	7		T196	7		T177	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	6		T26	3		T268	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	9		T51	1		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	11		T26	13		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T16	1		T178	1		T295	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T51	10		T29	10		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T11	13		T49	7		T150	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T49	16		T90	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	9		T12	11		T90	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	9		T29	17		T42	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T54	1		T43	4		T243	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T62	7		T227	11		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T28	13		T179	8		T272	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	27		T218	6		T183	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T54	11		T15	3		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T49	6		T145	11		T183	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T51	1		T147	10		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	4		T43	1		T256	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T12	9		T236	5		T283	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T54	10		T290	6		T270	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	1		T40	2		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T328	4		T329	7		T330	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T3	1		T12	1		T52	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T54	12		T217	1		T159	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T279	1		T289	1		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T146	1		T328	2		T291	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	3		T40	1		T196	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T52	7		T26	4		T221	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	7		T163	1		T55	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	13		T8	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	12		T51	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	1		T15	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T49	10		T143	1		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T49	21		T51	12		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T5	1		T7	11		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	3		T5	1		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T50	8		T90	1		T54	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	1		T13	1		T53	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T144	1		T278	1		T239	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	1		T183	16		T166	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	1		T53	16		T54	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T9	1		T49	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T51	1		T15	8		T221	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T13	1		T43	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T12	9		T156	6		T283	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T54	10		T331	8		T271	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T292	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T328	4		T291	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T196	7		T223	8		T169	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	3		T268	10		T170	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	9		T163	2		T62	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	6		T8	11		T26	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T51	1		T27	9		T230	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T27	11		T29	10		T157	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	7		T45	2		T183	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	16		T51	10		T90	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T7	9		T11	13		T12	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T29	17		T42	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T90	12		T54	1		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	9		T62	7		T227	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T179	8		T272	9		T226	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T9	16		T183	18		T16	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T54	11		T28	13		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	11		T49	6		T218	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T51	1		T15	3		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	4		T43	1		T145	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	3		T40	1		T165	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	7		T52	1		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	10		T51	2		T163	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	12		T26	14		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T50	1		T143	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	1		T51	11		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T5	1		T11	15		T49	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	3		T49	17		T90	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	10		T12	12		T90	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	10		T29	18		T42	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	1		T54	2		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T13	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	1		T28	14		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	29		T218	7		T183	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T53	1		T54	12		T15	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T13	1		T49	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T51	2		T52	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	5		T43	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T3	1		T12	10		T236	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T54	11		T290	7		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16963	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T146	1		T149	1		T328	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T165	5		T196	7		T177	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	12		T52	6		T26	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	6		T55	5		T62	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T26	12		T228	13		T233	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T50	11		T166	6		T287	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	11		T29	10		T250	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T49	9		T103	11		T108	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T49	20		T53	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	10		T28	13		T240	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	10		T42	3		T141	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T50	7		T43	4		T220	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T53	3		T55	2		T62	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T28	18		T239	2		T272	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T218	5		T183	15		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T53	15		T54	13		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T49	6		T183	18		T168	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T52	11		T55	14		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	1		T46	3		T257	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T236	7		T244	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T54	11		T270	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T155	9		T170	8		T332	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T329	7		T330	13		T333	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T3	1		T12	10		T52	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T54	11		T217	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T279	1		T289	1		T292	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T146	1		T328	6		T291	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	3		T40	1		T196	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T52	1		T26	4		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	10		T163	3		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	7		T8	12		T26	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	1		T51	2		T27	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T15	1		T27	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T49	8		T143	1		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	17		T51	11		T90	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T5	1		T7	10		T11	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	3		T5	1		T29	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	1		T90	13		T54	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	10		T13	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T144	1		T278	1		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	17		T183	19		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	1		T53	1		T54	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	1		T9	12		T49	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T51	2		T15	8		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	5		T13	1		T43	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T52	11		T55	14		T254	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T54	11		T159	12		T271	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T196	7		T155	9		T223	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T52	6		T26	3		T221	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	6		T55	5		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	12		T26	12		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T50	11		T153	11		T230	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T29	10		T250	2		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	9		T45	2		T183	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	20		T51	11		T53	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T7	10		T28	13		T103	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	1		T29	10		T42	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T50	7		T43	4		T220	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T53	3		T55	2		T62	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T239	2		T272	11		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T183	15		T166	6		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T53	15		T54	13		T28	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	6		T218	5		T183	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T15	3		T221	10		T240	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T43	1		T46	3		T257	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10