Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22499

1

T1

20

T2

63

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3178

1

T2

4

T3

1

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19934

1

T1

20

T2

64

T3

1

auto[1]

5743

1

T2

3

T4

35

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	168	1			T51	2		T29	21		T219	1
values[0]	36	1			T12	10		T27	10		T185	16
values[1]	599	1			T7	20		T8	12		T9	17
values[2]	2833	1			T11	15		T12	12		T150	31
values[3]	827	1			T4	19		T5	1		T52	7
values[4]	646	1			T4	16		T8	10		T90	13
values[5]	666	1			T8	1		T49	13		T50	12
values[6]	561	1			T3	1		T5	1		T9	12
values[7]	613	1			T5	1		T50	8		T52	12
values[8]	755	1			T13	1		T49	37		T51	22
values[9]	1045	1			T2	7		T51	2		T40	1
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	495	1			T9	17		T50	1		T55	15
values[1]	2838	1			T4	19		T11	15		T12	12
values[2]	868	1			T5	1		T8	10		T165	13
values[3]	586	1			T4	16		T90	13		T55	3
values[4]	732	1			T8	1		T49	30		T50	12
values[5]	530	1			T3	1		T5	1		T9	12
values[6]	585	1			T5	1		T50	8		T52	12
values[7]	831	1			T13	1		T49	37		T51	22
values[8]	909	1			T2	7		T51	2		T40	1
values[9]	92	1			T51	2		T145	8		T226	13
minimum	17211	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T27	1		T28	2		T42	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T9	1		T50	1		T55	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T4	13		T11	2		T150	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T144	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	1		T143	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	1		T165	6		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T55	3		T43	2		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	7		T90	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T49	10		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	7		T50	12		T54	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T9	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T90	1		T53	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T55	6		T29	11		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T50	8		T52	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	1		T49	21		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T220	6		T154	1		T155	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	3		T40	1		T54	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	3		T51	1		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T226	1		T170	9		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T51	1		T145	1		T194	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16842	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T8	1		T48	1		T241	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T27	11		T42	3		T183	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	16		T43	4		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T4	6		T11	13		T150	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	11		T145	11		T196	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T273	11		T320	15		T237	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	9		T165	7		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	1		T147	10		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T4	9		T90	12		T183	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	7		T163	2		T256	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	6		T54	11		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T9	11		T54	1		T62	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T90	6		T230	21		T257	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T29	17		T46	3		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T228	7		T268	8		T288	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	16		T51	10		T178	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T179	10		T60	8		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T54	10		T29	10		T225	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T51	1		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T226	12		T170	6		T297	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T51	1		T145	7		T302	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	10		T12	13		T40	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T8	11		T242	1		T276	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T29	11		T219	1		T156	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T51	1		T225	1		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T12	1		T27	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T185	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	11		T12	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	1		T9	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T11	2		T150	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T50	1		T55	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	13		T5	1		T52	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T165	6		T142	1		T153	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T55	3		T43	2		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	7		T8	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	1		T143	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T49	7		T50	12		T54	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T9	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T53	16		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T55	6		T62	3		T29	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T50	8		T52	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	1		T49	21		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T220	6		T155	10		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T2	3		T40	1		T54	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	3		T51	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T29	10		T156	6		T226	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T51	1		T249	8		T297	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T12	9		T27	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T185	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	9		T12	4		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	11		T9	16		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T11	13		T150	28		T62	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	11		T43	4		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	6		T273	14		T320	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T165	7		T177	11		T147	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T43	1		T235	13		T227	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T4	9		T8	9		T90	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	10		T256	12		T16	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	6		T54	11		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T9	11		T49	7		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T230	21		T168	2		T237	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T62	13		T29	17		T141	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T90	6		T257	4		T228	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	16		T51	10		T46	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T179	10		T158	8		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T54	10		T225	14		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	1		T51	1		T145	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T27	12		T28	1		T42	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	17		T50	1		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T4	7		T11	15		T150	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	12		T144	1		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	1		T143	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	10		T165	8		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	1		T43	2		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T4	10		T90	13		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T49	8		T163	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T49	7		T50	1		T54	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	1		T9	12		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T90	7		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T55	1		T29	18		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	1		T50	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T49	17		T51	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T220	1		T154	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	3		T40	1		T54	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	3		T51	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T226	13		T170	7		T297	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T51	2		T145	8		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17038	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T8	12		T48	1		T241	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T28	1		T42	3		T221	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T55	14		T43	4		T243	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T4	12		T52	6		T53	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T196	7		T243	3		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T241	4		T320	17		T239	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T165	5		T176	6		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T55	2		T43	1		T221	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T4	6		T183	22		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	9		T16	1		T266	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	6		T50	11		T54	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T62	2		T26	3		T295	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T53	15		T230	14		T257	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T55	5		T29	10		T46	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T50	7		T52	11		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T49	20		T51	11		T53	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T220	5		T155	9		T60	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T54	11		T29	10		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T45	2		T183	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T170	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T194	12		T302	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T7	10		T28	13		T218	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T241	4		T242	1		T287	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T29	11		T219	1		T156	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T51	2		T225	1		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T12	10		T27	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T185	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	10		T12	5		T27	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	12		T9	17		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T11	15		T150	31		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	12		T50	1		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	7		T5	1		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T165	8		T142	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	1		T43	2		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	10		T8	10		T90	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	1		T143	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	7		T50	1		T54	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T9	12		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T53	1		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	1		T62	14		T29	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T50	1		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	1		T49	17		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T220	1		T155	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T2	3		T40	1		T54	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	3		T51	2		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T29	10		T170	8		T310	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T249	8		T332	9		T334	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T185	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	10		T28	13		T42	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T241	4		T243	11		T242	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T53	10		T62	8		T26	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	14		T43	4		T196	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	12		T52	6		T266	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T165	5		T153	11		T177	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T55	2		T43	1		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	6		T176	6		T183	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T16	1		T266	8		T193	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T49	6		T50	11		T54	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T49	9		T26	3		T223	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	15		T230	14		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T55	5		T62	2		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T50	7		T52	11		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T49	20		T51	11		T53	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T220	5		T155	9		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T54	11		T240	12		T241	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T45	2		T183	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10